* [PATCH 1/9] MIPS: ar933x: pbl: add pbl_ar9331_pll macro
2015-11-02 21:43 [PATCH 0/9] MIPS: add ar9331 pbl support Antony Pavlov
@ 2015-11-02 21:43 ` Antony Pavlov
2015-11-02 21:43 ` [PATCH 2/9] MIPS: ar933x: pbl: add pbl_ar9331_ddr2_config macro Antony Pavlov
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Antony Pavlov @ 2015-11-02 21:43 UTC (permalink / raw)
To: barebox; +Cc: Oleksij Rempel
From: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/include/asm/pbl_macros.h | 21 ++++++++++++
arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1 +
arch/mips/mach-ath79/include/mach/pbl_macros.h | 43 +++++++++++++++++++++++++
3 files changed, 65 insertions(+)
diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h
index 1d9d6ab..db46d0d 100644
--- a/arch/mips/include/asm/pbl_macros.h
+++ b/arch/mips/include/asm/pbl_macros.h
@@ -28,6 +28,27 @@
#include <generated/compile.h>
#include <generated/utsrelease.h>
+ .macro pbl_reg_writel val addr
+ .set push
+ .set noreorder
+ li t9, \addr
+ li t8, \val
+ sw t8, 0(t9)
+ .set pop
+ .endm
+
+ .macro pbl_reg_clr clr addr
+ .set push
+ .set noreorder
+ li t9, \addr
+ li t8, \clr
+ lw t7, 0(t9)
+ not t8, t8
+ and t7, t8
+ sw t7, 0(t9)
+ .set pop
+ .endm
+
.macro pbl_sleep reg count
.set push
.set noreorder
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index b82a8c3..a1d7db0 100644
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -63,6 +63,7 @@
#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
+#define AR933X_PLL_CPU_CONFIG_PLLPWD BIT(30)
#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
diff --git a/arch/mips/mach-ath79/include/mach/pbl_macros.h b/arch/mips/mach-ath79/include/mach/pbl_macros.h
new file mode 100644
index 0000000..1fc6eb5
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/pbl_macros.h
@@ -0,0 +1,43 @@
+#ifndef __ASM_MACH_ATH79_PBL_MACROS_H
+#define __ASM_MACH_ATH79_PBL_MACROS_H
+
+#include <asm/addrspace.h>
+#include <asm/regdef.h>
+#include <mach/ar71xx_regs.h>
+
+#define PLL_BASE (KSEG1 | AR71XX_PLL_BASE)
+#define PLL_CPU_CONFIG_REG (PLL_BASE | AR933X_PLL_CPU_CONFIG_REG)
+#define PLL_CPU_CONFIG2_REG (PLL_BASE | AR933X_PLL_CPU_CONFIG2_REG)
+#define PLL_CLOCK_CTRL_REG (PLL_BASE | AR933X_PLL_CLOCK_CTRL_REG)
+
+#define DEF_25MHZ_PLL_CLOCK_CTRL \
+ ((2 - 1) << AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT \
+ | (1 - 1) << AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT \
+ | (1 - 1) << AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT)
+#define DEF_25MHZ_SETTLE_TIME (34000 / 40)
+#define DEF_25MHZ_PLL_CONFIG ( 1 << AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT \
+ | 1 << AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT \
+ | 32 << AR933X_PLL_CPU_CONFIG_NINT_SHIFT)
+
+.macro pbl_ar9331_pll
+ .set push
+ .set noreorder
+
+ /* Most devices have 25 MHz Ref clock. */
+ pbl_reg_writel (DEF_25MHZ_PLL_CLOCK_CTRL | AR933X_PLL_CLOCK_CTRL_BYPASS), \
+ PLL_CLOCK_CTRL_REG
+ pbl_reg_writel DEF_25MHZ_SETTLE_TIME, PLL_CPU_CONFIG2_REG
+ pbl_reg_writel (DEF_25MHZ_PLL_CONFIG | AR933X_PLL_CPU_CONFIG_PLLPWD), \
+ PLL_CPU_CONFIG_REG
+
+ /* power on CPU PLL */
+ pbl_reg_clr AR933X_PLL_CPU_CONFIG_PLLPWD, PLL_CPU_CONFIG_REG
+ /* disable PLL bypass */
+ pbl_reg_clr AR933X_PLL_CLOCK_CTRL_BYPASS, PLL_CLOCK_CTRL_REG
+
+ pbl_sleep t2, 40
+
+ .set pop
+.endm
+
+#endif /* __ASM_MACH_ATH79_PBL_MACROS_H */
--
2.6.2
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 2/9] MIPS: ar933x: pbl: add pbl_ar9331_ddr2_config macro
2015-11-02 21:43 [PATCH 0/9] MIPS: add ar9331 pbl support Antony Pavlov
2015-11-02 21:43 ` [PATCH 1/9] MIPS: ar933x: pbl: add pbl_ar9331_pll macro Antony Pavlov
@ 2015-11-02 21:43 ` Antony Pavlov
2015-11-02 21:43 ` [PATCH 3/9] MIPS: mach-ath79: add pbl_ar9331_uart_enable macro Antony Pavlov
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Antony Pavlov @ 2015-11-02 21:43 UTC (permalink / raw)
To: barebox; +Cc: Oleksij Rempel
See also u-boot_mod/u-boot/cpu/mips/ar7240/hornet_ddr_init.S
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 20 ++++++
arch/mips/mach-ath79/include/mach/pbl_macros.h | 89 +++++++++++++++++++++++++
2 files changed, 109 insertions(+)
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index a1d7db0..0b84c55 100644
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -23,6 +23,8 @@
#define AR71XX_APB_BASE 0x18000000
+#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
+#define AR71XX_DDR_CTRL_SIZE 0x100
#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
#define AR71XX_GPIO_SIZE 0x100
#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
@@ -34,6 +36,24 @@
#define AR933X_UART_SIZE 0x14
/*
+ * DDR_CTRL block
+ */
+#define AR933X_DDR_CONFIG 0x00
+#define AR933X_DDR_CONFIG2 0x04
+#define AR933X_DDR_MODE 0x08
+#define AR933X_DDR_EXT_MODE 0x0c
+#define AR933X_DDR_CTRL 0x10
+#define AR933X_DDR_REFRESH 0x14
+#define AR933X_DDR_RD_DATA 0x18
+#define AR933X_DDR_TAP_CTRL0 0x1c
+#define AR933X_DDR_TAP_CTRL1 0x20
+#define AR933X_DDR_TAP_CTRL1 0x20
+
+#define AR933X_DDR_DDR_DDR2_CONFIG 0x8c
+#define AR933X_DDR_DDR_EMR2 0x90
+#define AR933X_DDR_DDR_EMR3 0x94
+
+/*
* GPIO block
*/
#define AR71XX_GPIO_REG_OE 0x00
diff --git a/arch/mips/mach-ath79/include/mach/pbl_macros.h b/arch/mips/mach-ath79/include/mach/pbl_macros.h
index 1fc6eb5..f0e0174 100644
--- a/arch/mips/mach-ath79/include/mach/pbl_macros.h
+++ b/arch/mips/mach-ath79/include/mach/pbl_macros.h
@@ -40,4 +40,93 @@
.set pop
.endm
+#define DDR_BASE (KSEG1 | AR71XX_DDR_CTRL_BASE)
+#define DDR_CONFIG (DDR_BASE | AR933X_DDR_CONFIG)
+#define DDR_CONFIG2 (DDR_BASE | AR933X_DDR_CONFIG2)
+#define DDR_MODE (DDR_BASE | AR933X_DDR_MODE)
+#define DDR_EXT_MODE (DDR_BASE | AR933X_DDR_EXT_MODE)
+
+#define DDR_CTRL (DDR_BASE | AR933X_DDR_CTRL)
+/* Forces an EMR3S (Extended Mode Register 3 Set) update cycle */
+#define DDR_CTRL_EMR3 BIT(5)
+/* Forces an EMR2S (Extended Mode Register 2 Set) update cycle */
+#define DDR_CTRL_EMR2 BIT(4)
+#define DDR_CTRL_PREA BIT(3) /* Forces a PRECHARGE ALL cycle */
+#define DDR_CTRL_REF BIT(2) /* Forces an AUTO REFRESH cycle */
+/* Forces an EMRS (Extended Mode Register 2 Set) update cycle */
+#define DDR_CTRL_EMRS BIT(1)
+/* Forces a MRS (Mode Register Set) update cycle */
+#define DDR_CTRL_MRS BIT(0)
+
+#define DDR_REFRESH (DDR_BASE | AR933X_DDR_REFRESH)
+#define DDR_RD_DATA (DDR_BASE | AR933X_DDR_RD_DATA)
+#define DDR_TAP_CTRL0 (DDR_BASE | AR933X_DDR_TAP_CTRL0)
+#define DDR_TAP_CTRL1 (DDR_BASE | AR933X_DDR_TAP_CTRL1)
+
+#define DDR_DDR2_CONFIG (DDR_BASE | AR933X_DDR_DDR_DDR2_CONFIG)
+#define DDR_EMR2 (DDR_BASE | AR933X_DDR_DDR_EMR2)
+#define DDR_EMR3 (DDR_BASE | AR933X_DDR_DDR_EMR3)
+
+.macro pbl_ar9331_ddr2_config
+ .set push
+ .set noreorder
+
+ pbl_reg_writel 0x7fbc8cd0, DDR_CONFIG
+ pbl_reg_writel 0x9dd0e6a8, DDR_CONFIG2
+
+ /* Enable DDR2 */
+ pbl_reg_writel 0x00000a59, DDR_DDR2_CONFIG
+ pbl_reg_writel DDR_CTRL_PREA, DDR_CTRL
+
+ /* Disable High Temperature Self-Refresh Rate */
+ pbl_reg_writel 0x00000000, DDR_EMR2
+ pbl_reg_writel DDR_CTRL_EMR2, DDR_CTRL
+
+ pbl_reg_writel 0x00000000, DDR_EMR3
+ pbl_reg_writel DDR_CTRL_EMR3, DDR_CTRL
+
+ /* Enable DLL */
+ pbl_reg_writel 0x00000000, DDR_EXT_MODE
+ pbl_reg_writel DDR_CTRL_EMRS, DDR_CTRL
+
+ /* Reset DLL */
+ pbl_reg_writel 0x00000100, DDR_MODE
+ pbl_reg_writel DDR_CTRL_MRS, DDR_CTRL
+
+ pbl_reg_writel DDR_CTRL_PREA, DDR_CTRL
+ pbl_reg_writel DDR_CTRL_REF, DDR_CTRL
+ pbl_reg_writel DDR_CTRL_REF, DDR_CTRL
+
+ /* Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8 */
+ pbl_reg_writel 0x00000a33, DDR_MODE
+ pbl_reg_writel DDR_CTRL_MRS, DDR_CTRL
+
+ /*
+ * DDR_EXT_MODE[9:7] = 0x7: (OCD Calibration defaults)
+ * DDR_EXT_MODE[1] = 1: Reduced Drive Strength
+ * DDR_EXT_MODE[0] = 0: Enable DLL
+ */
+ pbl_reg_writel 0x00000382, DDR_EXT_MODE
+ pbl_reg_writel DDR_CTRL_EMRS, DDR_CTRL
+
+ /*
+ * DDR_EXT_MODE[9:7] = 0x0: (OCD exit)
+ * DDR_EXT_MODE[1] = 1: Reduced Drive Strength
+ * DDR_EXT_MODE[0] = 0: Enable DLL
+ */
+ pbl_reg_writel 0x00000402, DDR_EXT_MODE
+ pbl_reg_writel DDR_CTRL_EMRS, DDR_CTRL
+
+ /* Refresh control. Bit 14 is enable. Bits <13:0> Refresh time */
+ pbl_reg_writel 0x00004186, DDR_REFRESH
+ /* DQS 0 Tap Control (needs tuning) */
+ pbl_reg_writel 0x00000008, DDR_TAP_CTRL0
+ /* DQS 1 Tap Control (needs tuning) */
+ pbl_reg_writel 0x00000009, DDR_TAP_CTRL1
+ /* For 16-bit DDR */
+ pbl_reg_writel 0x000000ff, DDR_RD_DATA
+
+ .set pop
+.endm
+
#endif /* __ASM_MACH_ATH79_PBL_MACROS_H */
--
2.6.2
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 3/9] MIPS: mach-ath79: add pbl_ar9331_uart_enable macro
2015-11-02 21:43 [PATCH 0/9] MIPS: add ar9331 pbl support Antony Pavlov
2015-11-02 21:43 ` [PATCH 1/9] MIPS: ar933x: pbl: add pbl_ar9331_pll macro Antony Pavlov
2015-11-02 21:43 ` [PATCH 2/9] MIPS: ar933x: pbl: add pbl_ar9331_ddr2_config macro Antony Pavlov
@ 2015-11-02 21:43 ` Antony Pavlov
2015-11-02 21:43 ` [PATCH 4/9] MIPS: mach-ath79: add debug_ll_ar9331_init macro Antony Pavlov
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Antony Pavlov @ 2015-11-02 21:43 UTC (permalink / raw)
To: barebox; +Cc: Oleksij Rempel
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/include/asm/pbl_macros.h | 11 +++++++++++
arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 3 +++
arch/mips/mach-ath79/include/mach/pbl_macros.h | 7 +++++++
3 files changed, 21 insertions(+)
diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h
index db46d0d..681b40a 100644
--- a/arch/mips/include/asm/pbl_macros.h
+++ b/arch/mips/include/asm/pbl_macros.h
@@ -37,6 +37,17 @@
.set pop
.endm
+ .macro pbl_reg_set val addr
+ .set push
+ .set noreorder
+ li t9, \addr
+ li t8, \val
+ lw t7, 0(t9)
+ or t7, t8
+ sw t7, 0(t9)
+ .set pop
+ .endm
+
.macro pbl_reg_clr clr addr
.set push
.set noreorder
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index 0b84c55..4cbe94a 100644
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -67,6 +67,9 @@
#define AR71XX_GPIO_REG_INT_PENDING 0x20
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
+/* Warning! GPIO_FUNC[15] must be written with 1 */
+#define AR933X_GPIO_FUNC_RSRV15 BIT(15)
+#define AR933X_GPIO_FUNC_UART_EN BIT(1)
/*
* PLL block
diff --git a/arch/mips/mach-ath79/include/mach/pbl_macros.h b/arch/mips/mach-ath79/include/mach/pbl_macros.h
index f0e0174..4ef90dc 100644
--- a/arch/mips/mach-ath79/include/mach/pbl_macros.h
+++ b/arch/mips/mach-ath79/include/mach/pbl_macros.h
@@ -129,4 +129,11 @@
.set pop
.endm
+#define GPIO_FUNC ((KSEG1 | AR71XX_GPIO_BASE) | AR71XX_GPIO_REG_FUNC)
+
+.macro pbl_ar9331_uart_enable
+ pbl_reg_set AR933X_GPIO_FUNC_UART_EN \
+ | AR933X_GPIO_FUNC_RSRV15, GPIO_FUNC
+.endm
+
#endif /* __ASM_MACH_ATH79_PBL_MACROS_H */
--
2.6.2
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 4/9] MIPS: mach-ath79: add debug_ll_ar9331_init macro
2015-11-02 21:43 [PATCH 0/9] MIPS: add ar9331 pbl support Antony Pavlov
` (2 preceding siblings ...)
2015-11-02 21:43 ` [PATCH 3/9] MIPS: mach-ath79: add pbl_ar9331_uart_enable macro Antony Pavlov
@ 2015-11-02 21:43 ` Antony Pavlov
2015-11-02 21:43 ` [PATCH 5/9] MIPS: ath79: add black-swift board support Antony Pavlov
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Antony Pavlov @ 2015-11-02 21:43 UTC (permalink / raw)
To: barebox
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/mach-ath79/include/mach/debug_ll.h | 29 ++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/mips/mach-ath79/include/mach/debug_ll.h b/arch/mips/mach-ath79/include/mach/debug_ll.h
index d3813af..e0c3f79 100644
--- a/arch/mips/mach-ath79/include/mach/debug_ll.h
+++ b/arch/mips/mach-ath79/include/mach/debug_ll.h
@@ -63,6 +63,35 @@ static inline void PUTC_LL(int ch)
* Macros for use in assembly language code
*/
+#define AR933X_UART_CS_REG 0x04
+#define UART_CS_REG ((KSEG1 | AR933X_UART_BASE) | AR933X_UART_CS_REG)
+#define AR933X_UART_CS_IF_MODE_S 2
+#define AR933X_UART_CS_IF_MODE_DCE 2
+#define AR933X_UART_CS_TX_READY_ORIDE BIT(7)
+#define AR933X_UART_CS_RX_READY_ORIDE BIT(8)
+
+/*
+ * simple uart clock setup
+ * from u-boot_mod/u-boot/cpu/mips/ar7240/hornet_serial.c
+ */
+#define BAUD_CLOCK 25000000
+#define CLOCK_SCALE ((BAUD_CLOCK / (16 * CONFIG_BAUDRATE)) - 1)
+#define CLOCK_STEP 0x2000
+
+#define AR933X_UART_CLOCK_REG 0x08
+#define CLOCK_REG ((KSEG1 | AR933X_UART_BASE) | AR933X_UART_CLOCK_REG)
+
+.macro debug_ll_ar9331_init
+#ifdef CONFIG_DEBUG_LL
+
+ pbl_reg_writel ((AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) \
+ | AR933X_UART_CS_TX_READY_ORIDE \
+ | AR933X_UART_CS_RX_READY_ORIDE), UART_CS_REG
+ pbl_reg_writel ((CLOCK_SCALE << 16) | CLOCK_STEP), CLOCK_REG
+
+#endif /* CONFIG_DEBUG_LL */
+.endm
+
/*
* output a character in a0
*/
--
2.6.2
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 5/9] MIPS: ath79: add black-swift board support
2015-11-02 21:43 [PATCH 0/9] MIPS: add ar9331 pbl support Antony Pavlov
` (3 preceding siblings ...)
2015-11-02 21:43 ` [PATCH 4/9] MIPS: mach-ath79: add debug_ll_ar9331_init macro Antony Pavlov
@ 2015-11-02 21:43 ` Antony Pavlov
2015-11-02 21:43 ` [PATCH 6/9] MIPS: mach-ath79: add black-swift_defconfig Antony Pavlov
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Antony Pavlov @ 2015-11-02 21:43 UTC (permalink / raw)
To: barebox
Black Swift is a tiny coin-sized embedded computer based on AR9331 SoC.
See http://www.black-swift.com/ for details.
See also Black Swift kickstarter page:
https://www.kickstarter.com/projects/1133560316/black-swift-tiny-wireless-computer
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/Makefile | 1 +
arch/mips/boards/black-swift/Makefile | 1 +
arch/mips/boards/black-swift/board.c | 27 ++++++++++++++
.../black-swift/include/board/board_pbl_start.h | 41 ++++++++++++++++++++++
arch/mips/dts/black-swift.dts | 34 ++++++++++++++++++
arch/mips/mach-ath79/Kconfig | 6 ++++
6 files changed, 110 insertions(+)
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 6ef2bf7..75761b5 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -80,6 +80,7 @@ board-$(CONFIG_BOARD_NETGEAR_WG102) := netgear-wg102
machine-$(CONFIG_MACH_MIPS_ATH79) := ath79
board-$(CONFIG_BOARD_TPLINK_MR3020) := tplink-mr3020
+board-$(CONFIG_BOARD_BLACK_SWIFT) := black-swift
machine-$(CONFIG_MACH_MIPS_BCM47XX) := bcm47xx
board-$(CONFIG_BOARD_DLINK_DIR320) := dlink-dir-320
diff --git a/arch/mips/boards/black-swift/Makefile b/arch/mips/boards/black-swift/Makefile
new file mode 100644
index 0000000..dcfc293
--- /dev/null
+++ b/arch/mips/boards/black-swift/Makefile
@@ -0,0 +1 @@
+obj-y += board.o
diff --git a/arch/mips/boards/black-swift/board.c b/arch/mips/boards/black-swift/board.c
new file mode 100644
index 0000000..2e2ed20
--- /dev/null
+++ b/arch/mips/boards/black-swift/board.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2015 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+
+static int model_hostname_init(void)
+{
+ barebox_set_hostname("black-swift");
+
+ return 0;
+}
+postcore_initcall(model_hostname_init);
diff --git a/arch/mips/boards/black-swift/include/board/board_pbl_start.h b/arch/mips/boards/black-swift/include/board/board_pbl_start.h
new file mode 100644
index 0000000..f78e0d9
--- /dev/null
+++ b/arch/mips/boards/black-swift/include/board/board_pbl_start.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2013, 2015 Antony Pavlov <antonynpavlov@gmail.com>
+ * Copyright (C) 2013 Oleksij Rempel <linux@rempel-privat.de>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm/pbl_macros.h>
+#include <mach/pbl_macros.h>
+#include <asm/pbl_nmon.h>
+
+ .macro board_pbl_start
+ .set push
+ .set noreorder
+
+ mips_barebox_10h
+
+ mips_disable_interrupts
+
+ pbl_ar9331_pll
+ pbl_ar9331_ddr2_config
+
+ pbl_ar9331_uart_enable
+ debug_ll_ar9331_init
+ mips_nmon
+
+ copy_to_link_location pbl_start
+
+ .set pop
+ .endm
diff --git a/arch/mips/dts/black-swift.dts b/arch/mips/dts/black-swift.dts
new file mode 100644
index 0000000..270374d
--- /dev/null
+++ b/arch/mips/dts/black-swift.dts
@@ -0,0 +1,34 @@
+/dts-v1/;
+
+#include "ar9331.dtsi"
+
+/ {
+ model = "Black Swift";
+ compatible = "smartlx,black-swift";
+
+ memory {
+ reg = <0x00000000 0x4000000>;
+ };
+
+ aliases {
+ spiflash = &spiflash;
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&spi {
+ num-chipselects = <1>;
+ status = "okay";
+
+ /* Winbond W25Q128FV SPI flash */
+ spiflash: m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p80";
+ spi-max-frequency = <104000000>;
+ reg = <0>;
+ };
+};
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index f730b37..9b8e394 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -13,6 +13,12 @@ config BOARD_TPLINK_MR3020
select HAVE_IMAGE_COMPRESSION
select HAS_NMON
+config BOARD_BLACK_SWIFT
+ bool "Black Swift"
+ select HAVE_PBL_IMAGE
+ select HAVE_IMAGE_COMPRESSION
+ select HAS_NMON
+
endchoice
endif
--
2.6.2
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 6/9] MIPS: mach-ath79: add black-swift_defconfig
2015-11-02 21:43 [PATCH 0/9] MIPS: add ar9331 pbl support Antony Pavlov
` (4 preceding siblings ...)
2015-11-02 21:43 ` [PATCH 5/9] MIPS: ath79: add black-swift board support Antony Pavlov
@ 2015-11-02 21:43 ` Antony Pavlov
2015-11-02 21:43 ` [PATCH 7/9] MIPS: mach-ath79: add pbl_ar9331_ddr1_config macro Antony Pavlov
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Antony Pavlov @ 2015-11-02 21:43 UTC (permalink / raw)
To: barebox
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/configs/black-swift_defconfig | 46 +++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/mips/configs/black-swift_defconfig b/arch/mips/configs/black-swift_defconfig
new file mode 100644
index 0000000..7444968
--- /dev/null
+++ b/arch/mips/configs/black-swift_defconfig
@@ -0,0 +1,46 @@
+CONFIG_BUILTIN_DTB=y
+CONFIG_BUILTIN_DTB_NAME="black-swift"
+CONFIG_MACH_MIPS_ATH79=y
+CONFIG_BOARD_BLACK_SWIFT=y
+CONFIG_NMON=y
+CONFIG_NMON_USER_START=y
+CONFIG_NMON_1S_DELAY=0x100000
+CONFIG_NMON_USER_START_DELAY=0x5
+CONFIG_NMON_HELP=y
+CONFIG_PBL_IMAGE=y
+CONFIG_IMAGE_COMPRESSION_XZKERN=y
+CONFIG_MALLOC_TLSF=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_IMD=y
+CONFIG_PARTITION=y
+CONFIG_DEBUG_LL=y
+CONFIG_LONGHELP=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_BOOTM is not set
+CONFIG_CMD_GO=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_GLOBAL=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_LET=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_MM=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OFTREE=y
+CONFIG_OFDEVICE=y
+CONFIG_DRIVER_SERIAL_AR933X=y
+CONFIG_DRIVER_SPI_ATH79=y
+CONFIG_MTD=y
+# CONFIG_MTD_OOB_DEVICE is not set
+CONFIG_MTD_M25P80=y
+CONFIG_DIGEST_SHA224_GENERIC=y
+CONFIG_DIGEST_SHA256_GENERIC=y
--
2.6.2
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 7/9] MIPS: mach-ath79: add pbl_ar9331_ddr1_config macro
2015-11-02 21:43 [PATCH 0/9] MIPS: add ar9331 pbl support Antony Pavlov
` (5 preceding siblings ...)
2015-11-02 21:43 ` [PATCH 6/9] MIPS: mach-ath79: add black-swift_defconfig Antony Pavlov
@ 2015-11-02 21:43 ` Antony Pavlov
2015-11-02 21:43 ` [PATCH 8/9] MIPS: tplink-mr3020: add pbl low level init Antony Pavlov
2015-11-02 21:43 ` [PATCH 9/9] MIPS: tplink-mr3020_defconfig: enable pbl; make image shorter Antony Pavlov
8 siblings, 0 replies; 10+ messages in thread
From: Antony Pavlov @ 2015-11-02 21:43 UTC (permalink / raw)
To: barebox; +Cc: Oleksij Rempel
See also u-boot_mod/u-boot/cpu/mips/ar7240/hornet_ddr_init.S
See also this openocd commit:
commit f59d2d9ecfee8899df531b87b7acaa468725f238
Author: Oleksij Rempel <linux@rempel-privat.de>
Date: Fri Jan 30 13:05:31 2015 +0100
tcl/target|board: add config Atheros ar9331
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/mach-ath79/include/mach/pbl_macros.h | 43 ++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/mips/mach-ath79/include/mach/pbl_macros.h b/arch/mips/mach-ath79/include/mach/pbl_macros.h
index 4ef90dc..c00dd28 100644
--- a/arch/mips/mach-ath79/include/mach/pbl_macros.h
+++ b/arch/mips/mach-ath79/include/mach/pbl_macros.h
@@ -67,6 +67,49 @@
#define DDR_EMR2 (DDR_BASE | AR933X_DDR_DDR_EMR2)
#define DDR_EMR3 (DDR_BASE | AR933X_DDR_DDR_EMR3)
+.macro pbl_ar9331_ddr1_config
+ .set push
+ .set noreorder
+
+ pbl_reg_writel 0x7fbc8cd0, DDR_CONFIG
+ pbl_reg_writel 0x9dd0e6a8, DDR_CONFIG2
+
+ pbl_reg_writel DDR_CTRL_PREA, DDR_CTRL
+
+ /* 0x133: on reset Mode Register value */
+ pbl_reg_writel 0x133, DDR_MODE
+ pbl_reg_writel DDR_CTRL_MRS, DDR_CTRL
+
+ /*
+ * DDR_EXT_MODE[1] = 1: Reduced Drive Strength
+ * DDR_EXT_MODE[0] = 0: Enable DLL
+ */
+ pbl_reg_writel 0x2, DDR_EXT_MODE
+ pbl_reg_writel DDR_CTRL_EMRS, DDR_CTRL
+
+ pbl_reg_writel DDR_CTRL_PREA, DDR_CTRL
+
+ /* DLL out of reset, CAS Latency 3 */
+ pbl_reg_writel 0x33, DDR_MODE
+ pbl_reg_writel DDR_CTRL_MRS, DDR_CTRL
+
+ /* Refresh control. Bit 14 is enable. Bits<13:0> Refresh time */
+ pbl_reg_writel 0x4186, DDR_REFRESH
+ /* This register is used along with DQ Lane 0; DQ[7:0], DQS_0 */
+ pbl_reg_writel 0x8, DDR_TAP_CTRL0
+ /* This register is used along with DQ Lane 1; DQ[15:8], DQS_1 */
+ pbl_reg_writel 0x9, DDR_TAP_CTRL1
+
+ /*
+ * DDR read and capture bit mask.
+ * Each bit represents a cycle of valid data.
+ * 0xff: use 16-bit DDR
+ */
+ pbl_reg_writel 0xff, DDR_RD_DATA
+
+ .set pop
+.endm
+
.macro pbl_ar9331_ddr2_config
.set push
.set noreorder
--
2.6.2
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 8/9] MIPS: tplink-mr3020: add pbl low level init
2015-11-02 21:43 [PATCH 0/9] MIPS: add ar9331 pbl support Antony Pavlov
` (6 preceding siblings ...)
2015-11-02 21:43 ` [PATCH 7/9] MIPS: mach-ath79: add pbl_ar9331_ddr1_config macro Antony Pavlov
@ 2015-11-02 21:43 ` Antony Pavlov
2015-11-02 21:43 ` [PATCH 9/9] MIPS: tplink-mr3020_defconfig: enable pbl; make image shorter Antony Pavlov
8 siblings, 0 replies; 10+ messages in thread
From: Antony Pavlov @ 2015-11-02 21:43 UTC (permalink / raw)
To: barebox
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h b/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h
index 944a510..08204fe 100644
--- a/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h
+++ b/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h
@@ -17,6 +17,7 @@
*/
#include <asm/pbl_macros.h>
+#include <mach/pbl_macros.h>
#include <asm/pbl_nmon.h>
.macro board_pbl_start
@@ -27,6 +28,11 @@
mips_disable_interrupts
+ pbl_ar9331_pll
+ pbl_ar9331_ddr1_config
+
+ pbl_ar9331_uart_enable
+ debug_ll_ar9331_init
mips_nmon
copy_to_link_location pbl_start
--
2.6.2
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 9/9] MIPS: tplink-mr3020_defconfig: enable pbl; make image shorter
2015-11-02 21:43 [PATCH 0/9] MIPS: add ar9331 pbl support Antony Pavlov
` (7 preceding siblings ...)
2015-11-02 21:43 ` [PATCH 8/9] MIPS: tplink-mr3020: add pbl low level init Antony Pavlov
@ 2015-11-02 21:43 ` Antony Pavlov
8 siblings, 0 replies; 10+ messages in thread
From: Antony Pavlov @ 2015-11-02 21:43 UTC (permalink / raw)
To: barebox
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/configs/tplink-mr3020_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/mips/configs/tplink-mr3020_defconfig b/arch/mips/configs/tplink-mr3020_defconfig
index b675993..f2ba2da 100644
--- a/arch/mips/configs/tplink-mr3020_defconfig
+++ b/arch/mips/configs/tplink-mr3020_defconfig
@@ -1,6 +1,9 @@
CONFIG_BUILTIN_DTB=y
CONFIG_BUILTIN_DTB_NAME="tplink-mr3020"
CONFIG_MACH_MIPS_ATH79=y
+CONFIG_PBL_IMAGE=y
+CONFIG_IMAGE_COMPRESSION_XZKERN=y
+CONFIG_MALLOC_TLSF=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_LONGHELP=y
--
2.6.2
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