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From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
To: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
	barebox@lists.infradead.org
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
	Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Subject: [PATCH v2 15/19] mtd: nand_mrvl_nfc: Add support for 8bit BCH HW ECC
Date: Fri, 20 Nov 2015 20:36:08 +0100	[thread overview]
Message-ID: <1448048172-10080-16-git-send-email-sebastian.hesselbarth@gmail.com> (raw)
In-Reply-To: <1448048172-10080-1-git-send-email-sebastian.hesselbarth@gmail.com>

Add support for 8bit HW ECC modes supported by later IP versions.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index 3e9fccdffefe..f43200dcf2c7 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -252,6 +252,17 @@ static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
 	.oobfree = { {1, 4}, {6, 26}, {64, 32} }
 };
 
+static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
+	.eccbytes = 64,
+	.eccpos = {
+		32,  33,  34,  35,  36,  37,  38,  39,
+		40,  41,  42,  43,  44,  45,  46,  47,
+		48,  49,  50,  51,  52,  53,  54,  55,
+		56,  57,  58,  59,  60,  61,  62,  63},
+	/* Bootrom looks in bytes 0 & 5 for bad blocks */
+	.oobfree = { {1, 4}, {6, 26} }
+};
+
 #define NDTR0_tCH(c)	(min((c), 7) << 19)
 #define NDTR0_tCS(c)	(min((c), 7) << 16)
 #define NDTR0_tWH(c)	(min((c), 7) << 11)
@@ -928,6 +939,31 @@ static int pxa_ecc_strength4(struct mrvl_nand_host *host,
 	return -ENODEV;
 }
 
+static int pxa_ecc_strength8(struct mrvl_nand_host *host,
+		struct nand_ecc_ctrl *ecc, int ecc_stepsize, int page_size)
+{
+	if (!(host->hwflags & HWFLAGS_ECC_BCH))
+		return -ENODEV;
+
+	/*
+	 * Required ECC: 8-bit correction per 512 bytes
+	 * Select: 16-bit correction per 1024 bytes
+	 */
+	if (ecc_stepsize == 512 && page_size == 4096) {
+		host->chunk_size = 1024;
+		host->spare_size = 0;
+		host->ecc_size = 32;
+		host->ecc_bch = 1;
+		ecc->mode = NAND_ECC_HW;
+		ecc->size = 1024;
+		ecc->layout = &ecc_layout_4KB_bch8bit;
+		ecc->strength = 16;
+		return 0;
+	}
+
+	return -ENODEV;
+}
+
 static int pxa_ecc_init(struct mrvl_nand_host *host,
 			struct nand_ecc_ctrl *ecc,
 			int strength, int ecc_stepsize, int page_size)
@@ -941,6 +977,9 @@ static int pxa_ecc_init(struct mrvl_nand_host *host,
 	case 4:
 		ret = pxa_ecc_strength4(host, ecc, ecc_stepsize, page_size);
 		break;
+	case 8:
+		ret = pxa_ecc_strength8(host, ecc, ecc_stepsize, page_size);
+		break;
 	}
 
 	if (ret) {
-- 
2.1.4


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  parent reply	other threads:[~2015-11-20 19:36 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-20 19:35 [PATCH v2 00/19] Armada 370/XP NAND driver Sebastian Hesselbarth
2015-11-20 19:35 ` [PATCH v2 01/19] of: mtd: Import of_get_nand_ecc_{step_size, strength} from Linux Sebastian Hesselbarth
2015-11-20 19:35 ` [PATCH v2 02/19] mtd: nand: Clarify Marvell Orion Kconfig prompt Sebastian Hesselbarth
2015-11-20 19:35 ` [PATCH v2 03/19] arm: pxa: Prepare for NAND clkdev lookup on PXA3xx Sebastian Hesselbarth
2015-11-20 19:35 ` [PATCH v2 04/19] arm: pxa: Add clock for Zylonite NFC Sebastian Hesselbarth
2015-11-20 19:35 ` [PATCH v2 05/19] mtd: nand_mrvl_nfc: Use common clock for core clock Sebastian Hesselbarth
2015-11-20 19:35 ` [PATCH v2 06/19] arm: pxa: Remove pxa_get_nandclk() Sebastian Hesselbarth
2015-11-20 19:36 ` [PATCH v2 07/19] mtd: nand_mrvl_nfc: Clear OOB data with 0xff instead of 0x00 Sebastian Hesselbarth
2015-11-20 19:36 ` [PATCH v2 08/19] mtd: nand_mrvl_nfc: Use Auto Read Status on program/erase Sebastian Hesselbarth
2015-11-20 19:36 ` [PATCH v2 09/19] mtd: nand_mrvl_nfc: Protect mrvl_nand_probe_dt Sebastian Hesselbarth
2015-11-20 19:36 ` [PATCH v2 10/19] mtd: nand_mrvl_nfc: Fix num-cs property parsing Sebastian Hesselbarth
2015-11-20 19:36 ` [PATCH v2 11/19] mtd: nand_mrvl_nfc: Get ecc parameters from DT Sebastian Hesselbarth
2015-11-20 19:36 ` [PATCH v2 12/19] mtd: nand_mrvl_nfc: Prepare for different HW ECC strengths Sebastian Hesselbarth
2015-11-20 20:38   ` Trent Piepho
2015-11-23  7:18     ` Sascha Hauer
2015-11-20 19:36 ` [PATCH v2 13/19] mtd: nand_mrvl_nfc: Add hwflags to distinguish different HW versions Sebastian Hesselbarth
2015-11-20 19:36 ` [PATCH v2 14/19] mtd: nand_mrvl_nfc: Add support for 4bit BCH HW ECC Sebastian Hesselbarth
2015-11-20 19:36 ` Sebastian Hesselbarth [this message]
2015-11-20 19:36 ` [PATCH v2 16/19] mtd: nand_mrvl_nfc: Add support for HW BCH ECC Sebastian Hesselbarth
2015-11-20 19:36 ` [PATCH v2 17/19] mtd: nand_mrvl_nfc: Add support for NDCB3 register Sebastian Hesselbarth
2015-11-20 19:36 ` [PATCH v2 18/19] mtd: nand_mrvl_nfc: Add support for Marvell Armada 370/XP Sebastian Hesselbarth
2015-11-20 19:36 ` [PATCH v2 19/19] mtd: nand_mrvl_nfc: Add optimized timings for Samsung K9K8G08U Sebastian Hesselbarth
2015-11-23  7:19 ` [PATCH v2 00/19] Armada 370/XP NAND driver Sascha Hauer

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