[PATCH v2 00/19] Armada 370/XP NAND driver

[PATCH v2 00/19] Armada 370/XP NAND driver

[Sebastian Hesselbarth]

This is v2 of the patch set that adds support for the NAND flash
controller found on Marvell Armada 370/XP SoCs. The IP is the same
as for PXA3xx SoCs, so we can also reuse the driver. However, this
needs some rework of the existing driver.

Patch 1 imports some mtd OF helpers from Linux for ECC propery
parsing.

Patch 2 clarifies Marvell Orion NAND Kconfig entry to distinguish
it from Armada 370/XP NAND support in PXA3xx NAND.

Patches 3-6 free nand_mrvl_nfc from mach-pxa dependency by
adding common clock support to mach-pxa and rework the driver
to get rid of pxa_get_nandclk().

Patches 7-13 comprise cleanup and preparation for the
addition of Armada 370/XP version of the NAND controller IP.

Patches 14-18 add features found on Armada XP NAND controller
only.

Finally, Patch 19 adds optimized timings for the NAND flash
found on Lenovo ix4-300d.

The series is based on today's next with Robert's patiently
confirmed Tested-by on mach-pxa. I have tested this on IX4.

Sebastian Hesselbarth (19):
  of: mtd: Import of_get_nand_ecc_{step_size,strength} from Linux
  mtd: nand: Clarify Marvell Orion Kconfig prompt
  arm: pxa: Prepare for NAND clkdev lookup on PXA3xx
  arm: pxa: Add clock for Zylonite NFC
  mtd: nand_mrvl_nfc: Use common clock for core clock
  arm: pxa: Remove pxa_get_nandclk()
  mtd: nand_mrvl_nfc: Clear OOB data with 0xff instead of 0x00
  mtd: nand_mrvl_nfc: Use Auto Read Status on program/erase
  mtd: nand_mrvl_nfc: Protect mrvl_nand_probe_dt
  mtd: nand_mrvl_nfc: Fix num-cs property parsing
  mtd: nand_mrvl_nfc: Get ecc parameters from DT
  mtd: nand_mrvl_nfc: Prepare for different HW ECC strengths
  mtd: nand_mrvl_nfc: Add hwflags to distinguish different HW versions
  mtd: nand_mrvl_nfc: Add support for 4bit BCH HW ECC
  mtd: nand_mrvl_nfc: Add support for 8bit BCH HW ECC
  mtd: nand_mrvl_nfc: Add support for HW BCH ECC
  mtd: nand_mrvl_nfc: Add support for NDCB3 register
  mtd: nand_mrvl_nfc: Add support for Marvell Armada 370/XP
  mtd: nand_mrvl_nfc: Add optimized timings for Samsung K9K8G08U

 arch/arm/Kconfig                       |   1 +
 arch/arm/boards/zylonite/board.c       |   7 +
 arch/arm/mach-pxa/Kconfig              |   2 +
 arch/arm/mach-pxa/include/mach/clock.h |   1 -
 arch/arm/mach-pxa/speed-pxa3xx.c       |  20 ++-
 drivers/mtd/nand/Kconfig               |   9 +-
 drivers/mtd/nand/nand_mrvl_nfc.c       | 236 +++++++++++++++++++++++++++++++--
 drivers/of/of_mtd.c                    |  34 +++++
 include/of_mtd.h                       |   2 +
 9 files changed, 289 insertions(+), 23 deletions(-)

-- 
2.1.4


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[PATCH v2 01/19] of: mtd: Import of_get_nand_ecc_{step_size, strength} from Linux

[Sebastian Hesselbarth]

This imports DT helpers for MTD ECC step size and strength from
Linux kernel.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
 drivers/of/of_mtd.c | 34 ++++++++++++++++++++++++++++++++++
 include/of_mtd.h    |  2 ++
 2 files changed, 36 insertions(+)

diff --git a/drivers/of/of_mtd.c b/drivers/of/of_mtd.c
index 97f3095740f7..0956ee15d393 100644
--- a/drivers/of/of_mtd.c
+++ b/drivers/of/of_mtd.c
@@ -49,6 +49,40 @@ int of_get_nand_ecc_mode(struct device_node *np)
 EXPORT_SYMBOL_GPL(of_get_nand_ecc_mode);
 
 /**
+ * of_get_nand_ecc_step_size - Get ECC step size associated to
+ * the required ECC strength (see below).
+ * @np:	Pointer to the given device_node
+ *
+ * return the ECC step size, or errno in error case.
+ */
+int of_get_nand_ecc_step_size(struct device_node *np)
+{
+	int ret;
+	u32 val;
+
+	ret = of_property_read_u32(np, "nand-ecc-step-size", &val);
+	return ret ? ret : val;
+}
+EXPORT_SYMBOL_GPL(of_get_nand_ecc_step_size);
+
+/**
+ * of_get_nand_ecc_strength - Get required ECC strength over the
+ * correspnding step size as defined by 'nand-ecc-size'
+ * @np:	Pointer to the given device_node
+ *
+ * return the ECC strength, or errno in error case.
+ */
+int of_get_nand_ecc_strength(struct device_node *np)
+{
+	int ret;
+	u32 val;
+
+	ret = of_property_read_u32(np, "nand-ecc-strength", &val);
+	return ret ? ret : val;
+}
+EXPORT_SYMBOL_GPL(of_get_nand_ecc_strength);
+
+/**
  * of_get_nand_bus_width - Get nand bus witdh for given device_node
  * @np:	Pointer to the given device_node
  *
diff --git a/include/of_mtd.h b/include/of_mtd.h
index a5a8f20daff6..9f5b8a2796a2 100644
--- a/include/of_mtd.h
+++ b/include/of_mtd.h
@@ -12,6 +12,8 @@
 #include <of.h>
 
 int of_get_nand_ecc_mode(struct device_node *np);
+int of_get_nand_ecc_step_size(struct device_node *np);
+int of_get_nand_ecc_strength(struct device_node *np);
 int of_get_nand_bus_width(struct device_node *np);
 bool of_get_nand_on_flash_bbt(struct device_node *np);
 
-- 
2.1.4


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[PATCH v2 02/19] mtd: nand: Clarify Marvell Orion Kconfig prompt

[Sebastian Hesselbarth]

Kconfig prompt for Marvell Orion SoCs is missing a "Marvell"
prefix, add it to the prompt.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
 drivers/mtd/nand/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index ff265848459a..3426ec055756 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -92,7 +92,7 @@ config NAND_OMAP_GPMC
 
 config NAND_ORION
 	bool
-	prompt "Orion NAND driver"
+	prompt "Marvell Orion NAND driver"
 	depends on ARCH_KIRKWOOD
 	help
 	  Support for the Orion NAND controller, present in Kirkwood SoCs.
-- 
2.1.4


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[PATCH v2 03/19] arm: pxa: Prepare for NAND clkdev lookup on PXA3xx

[Sebastian Hesselbarth]

To allow PXA3xx nand driver to be reused on Marvell Armada 370/XP,
prepare to provide a common clock for the NAND driver on PXA3xx.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 arch/arm/Kconfig                 |  1 +
 arch/arm/mach-pxa/Kconfig        |  2 ++
 arch/arm/mach-pxa/speed-pxa3xx.c | 18 ++++++++++++++++++
 3 files changed, 21 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c03f7dc8830b..9f4d8e958794 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -152,6 +152,7 @@ config ARCH_PXA
 	bool "Intel/Marvell PXA based"
 	select GENERIC_GPIO
 	select HAS_POWEROFF
+	select HAVE_CLK
 
 config ARCH_ROCKCHIP
 	bool "Rockchip RX3xxx"
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 54094f4ca0ed..1c0894892b17 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -17,6 +17,8 @@ config ARCH_PXA2XX
 config ARCH_PXA3XX
        bool
        select CPU_XSC3
+       select CLKDEV_LOOKUP
+       select COMMON_CLK
 
 config ARCH_PXA310
        bool
diff --git a/arch/arm/mach-pxa/speed-pxa3xx.c b/arch/arm/mach-pxa/speed-pxa3xx.c
index 6a08ea78f065..102951736dc0 100644
--- a/arch/arm/mach-pxa/speed-pxa3xx.c
+++ b/arch/arm/mach-pxa/speed-pxa3xx.c
@@ -8,6 +8,9 @@
  */
 
 #include <common.h>
+#include <init.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
 #include <mach/clock.h>
 #include <mach/pxa-regs.h>
 
@@ -31,3 +34,18 @@ unsigned long pxa_get_nandclk(void)
 	else
 		return 156000000;
 }
+
+static int pxa3xx_clock_init(void)
+{
+	unsigned long nand_rate = (cpu_is_pxa320()) ? 104000000 : 156000000;
+	struct clk *clk;
+	int ret;
+
+	clk = clk_fixed("nand", nand_rate);
+	ret = clk_register_clkdev(clk, NULL, "nand");
+	if (ret)
+		return ret;
+
+	return 0;
+}
+postcore_initcall(pxa3xx_clock_init);
-- 
2.1.4


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[PATCH v2 04/19] arm: pxa: Add clock for Zylonite NFC

[Sebastian Hesselbarth]

Add a clock with clk_add_physbase for the NAND flash controller on
Zylonite board.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 arch/arm/boards/zylonite/board.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boards/zylonite/board.c b/arch/arm/boards/zylonite/board.c
index 2caadbcecc37..2ff08b79345f 100644
--- a/arch/arm/boards/zylonite/board.c
+++ b/arch/arm/boards/zylonite/board.c
@@ -28,6 +28,8 @@
 #include <net/smc91111.h>
 #include <platform_data/mtd-nand-mrvl.h>
 #include <pwm.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
 #include <linux/sizes.h>
 
 #include <mach/devices.h>
@@ -60,11 +62,16 @@ static mfp_cfg_t pxa310_mfp_cfg[] = {
 
 static int zylonite_devices_init(void)
 {
+	struct clk *clk;
+
 	armlinux_set_architecture(MACH_TYPE_ZYLONITE);
 	pxa_add_uart((void *)0x40100000, 0);
 	add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL,
 			   0x14000300, 0x100000, IORESOURCE_MEM,
 			   &smsc91x_pdata);
+	clk = clk_get_sys("nand", NULL);
+	if (!IS_ERR(clk))
+		clkdev_add_physbase(clk, 0x43100000, NULL);
 	add_generic_device("mrvl_nand", DEVICE_ID_DYNAMIC, NULL,
 			   0x43100000, 0x1000, IORESOURCE_MEM, &nand_pdata);
 	devfs_add_partition("nand0", SZ_1M, SZ_256K, DEVFS_PARTITION_FIXED,
-- 
2.1.4


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[PATCH v2 05/19] mtd: nand_mrvl_nfc: Use common clock for core clock

[Sebastian Hesselbarth]

With PXA3xx now providing a common clock for the NAND clock, use it
and get rid of the mach/clock.h. This will allow Marvell Armada 370/XP
to reuse the same driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index 1ec48cc09e59..bdf949de0e7f 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -24,7 +24,6 @@
 #include <linux/types.h>
 #include <linux/clk.h>
 #include <linux/err.h>
-#include <mach/clock.h>
 #include <malloc.h>
 #include <of_mtd.h>
 #include <stmp-device.h>
@@ -135,6 +134,7 @@ struct mrvl_nand_host {
 	struct nand_chip	chip;
 	struct mtd_partition	*parts;
 	struct device_d		*dev;
+	struct clk		*core_clk;
 
 	/* calculated from mrvl_nand_flash data */
 	unsigned int		col_addr_cycles;
@@ -281,10 +281,10 @@ static struct mrvl_nand_timing timings[] = {
 static void mrvl_nand_set_timing(struct mrvl_nand_host *host, bool use_default)
 {
 	struct mtd_info *mtd = &host->mtd;
+	unsigned long nand_clk = clk_get_rate(host->core_clk);
 	struct mrvl_nand_timing *t;
 	uint32_t ndtr0, ndtr1;
 	u16 id;
-	unsigned long nand_clk = pxa_get_nandclk();
 
 	if (use_default) {
 		id = 0;
@@ -954,6 +954,13 @@ static struct mrvl_nand_host *alloc_nand_resource(struct device_d *dev)
 		free(host);
 		return host->mmio_base;
 	}
+	host->core_clk = clk_get(dev, NULL);
+	if (IS_ERR(host->core_clk)) {
+		free(host);
+		return (void *)host->core_clk;
+	}
+	clk_enable(host->core_clk);
+
 	if (pdata) {
 		host->keep_config = pdata->keep_config;
 		host->flash_bbt = pdata->flash_bbt;
-- 
2.1.4


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[PATCH v2 06/19] arm: pxa: Remove pxa_get_nandclk()

[Sebastian Hesselbarth]

With a common clock provided for NAND controller, get rid of the
mach/clock.h way of getting the NAND clock.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 arch/arm/mach-pxa/include/mach/clock.h | 1 -
 arch/arm/mach-pxa/speed-pxa3xx.c       | 8 --------
 2 files changed, 9 deletions(-)

diff --git a/arch/arm/mach-pxa/include/mach/clock.h b/arch/arm/mach-pxa/include/mach/clock.h
index 40f6223cd982..f86152f7af50 100644
--- a/arch/arm/mach-pxa/include/mach/clock.h
+++ b/arch/arm/mach-pxa/include/mach/clock.h
@@ -14,7 +14,6 @@
 unsigned long pxa_get_uartclk(void);
 unsigned long pxa_get_mmcclk(void);
 unsigned long pxa_get_lcdclk(void);
-unsigned long pxa_get_nandclk(void);
 unsigned long pxa_get_pwmclk(void);
 
 #endif	/* !__MACH_CLOCK_H */
diff --git a/arch/arm/mach-pxa/speed-pxa3xx.c b/arch/arm/mach-pxa/speed-pxa3xx.c
index 102951736dc0..b24b7a8fc380 100644
--- a/arch/arm/mach-pxa/speed-pxa3xx.c
+++ b/arch/arm/mach-pxa/speed-pxa3xx.c
@@ -27,14 +27,6 @@ unsigned long pxa_get_pwmclk(void)
 	return BASE_CLK;
 }
 
-unsigned long pxa_get_nandclk(void)
-{
-	if (cpu_is_pxa320())
-		return 104000000;
-	else
-		return 156000000;
-}
-
 static int pxa3xx_clock_init(void)
 {
 	unsigned long nand_rate = (cpu_is_pxa320()) ? 104000000 : 156000000;
-- 
2.1.4


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[PATCH v2 07/19] mtd: nand_mrvl_nfc: Clear OOB data with 0xff instead of 0x00

[Sebastian Hesselbarth]

If OOB data is not required on page program, we have to clear
the corresponding data with 0xff instead of 0x00.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index bdf949de0e7f..60c34c21af25 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -719,7 +719,7 @@ static int mrvl_nand_write_page_hwecc(struct mtd_info *mtd,
 		memcpy(host->data_buff + mtd->writesize, chip->oob_poi,
 		       mtd->oobsize);
 	else
-		memset(host->data_buff + mtd->writesize, 0, mtd->oobsize);
+		memset(host->data_buff + mtd->writesize, 0xff, mtd->oobsize);
 	dev_dbg(host->dev, "%s(buf=%p, oob_required=%d) => 0\n",
 		__func__, buf, oob_required);
 	return 0;
-- 
2.1.4


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[PATCH v2 08/19] mtd: nand_mrvl_nfc: Use Auto Read Status on program/erase

[Sebastian Hesselbarth]

Marvell NAND controller allows to enable an Auto Read Status feature
that will automatically monitor NAND status during Erase and Program
operations. Ready bit in status register will be set after the
controller is sure the NAND device has finished the operation and
saves us from guessing the real timeout values.

Using the Auto Read Status feature prevents timeout issues on the
two operations with none or wrong timing register setup.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index 60c34c21af25..ac530fc62499 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -562,6 +562,7 @@ static int prepare_set_command(struct mrvl_nand_host *host, int command,
 
 	case NAND_CMD_PAGEPROG:
 		host->ndcb0 |= NDCB0_CMD_TYPE(0x1)
+				| NDCB0_AUTO_RS
 				| NDCB0_DBC
 				| (NAND_CMD_PAGEPROG << 8)
 				| NAND_CMD_SEQIN
@@ -599,6 +600,7 @@ static int prepare_set_command(struct mrvl_nand_host *host, int command,
 
 	case NAND_CMD_ERASE1:
 		host->ndcb0 |= NDCB0_CMD_TYPE(2)
+				| NDCB0_AUTO_RS
 				| NDCB0_ADDR_CYC(3)
 				| NDCB0_DBC
 				| (NAND_CMD_ERASE2 << 8)
-- 
2.1.4


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[PATCH v2 09/19] mtd: nand_mrvl_nfc: Protect mrvl_nand_probe_dt

[Sebastian Hesselbarth]

Parsing DT nodes if CONFIG_OFTREE isn't enabled is pointless, also
we should prefer potential platform_data passed earlier.
Protect mrvl_nand_probe_dt by bailing out early if either
CONFIG_OFTREE is not enabled or dev's platform_data is non-NULL.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index ac530fc62499..95abd4ddf243 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -983,6 +983,9 @@ static int mrvl_nand_probe_dt(struct mrvl_nand_host *host)
 {
 	struct device_node *np = host->dev->device_node;
 
+	if (!IS_ENABLED(CONFIG_OFTREE) || host->dev->platform_data)
+		return 0;
+
 	if (of_get_property(np, "marvell,nand-keep-config", NULL))
 		host->keep_config = 1;
 	of_property_read_u32(np, "num-cs", &host->cs);
-- 
2.1.4


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[PATCH v2 10/19] mtd: nand_mrvl_nfc: Fix num-cs property parsing

[Sebastian Hesselbarth]

The "num-cs" property does not encode flashes CS line but number
of available CS signals. Fix wrong property parsing to ->cs by
adding proper ->num_cs variable to host struct.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index 95abd4ddf243..5374e64965a2 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -153,6 +153,7 @@ struct mrvl_nand_host {
 	int			ecc_strength;
 	int			ecc_step;
 
+	int			num_cs;		/* avaiable CS signals */
 	int			cs;		/* selected chip 0/1 */
 	int			use_ecc;	/* use HW ECC ? */
 	int			use_spare;	/* use spare ? */
@@ -929,6 +930,7 @@ static struct mrvl_nand_host *alloc_nand_resource(struct device_d *dev)
 
 	pdata = dev->platform_data;
 	host = xzalloc(sizeof(*host));
+	host->num_cs = 1;
 	host->cs = 0;
 	mtd = &host->mtd;
 	mtd->priv = &host->chip;
@@ -988,7 +990,7 @@ static int mrvl_nand_probe_dt(struct mrvl_nand_host *host)
 
 	if (of_get_property(np, "marvell,nand-keep-config", NULL))
 		host->keep_config = 1;
-	of_property_read_u32(np, "num-cs", &host->cs);
+	of_property_read_u32(np, "num-cs", &host->num_cs);
 	if (of_get_nand_on_flash_bbt(np))
 		host->flash_bbt = 1;
 
-- 
2.1.4


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[PATCH v2 11/19] mtd: nand_mrvl_nfc: Get ecc parameters from DT

[Sebastian Hesselbarth]

With DT helpers for ECC step size and strength, now use them on
Marvell NAND driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index 5374e64965a2..8dcbc3dc045e 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -994,6 +994,14 @@ static int mrvl_nand_probe_dt(struct mrvl_nand_host *host)
 	if (of_get_nand_on_flash_bbt(np))
 		host->flash_bbt = 1;
 
+	host->ecc_strength = of_get_nand_ecc_strength(np);
+	if (host->ecc_strength < 0)
+		host->ecc_strength = 0;
+
+	host->ecc_step = of_get_nand_ecc_step_size(np);
+	if (host->ecc_step < 0)
+		host->ecc_step = 0;
+
 	return 0;
 }
 
-- 
2.1.4


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[PATCH v2 12/19] mtd: nand_mrvl_nfc: Prepare for different HW ECC strengths

[Sebastian Hesselbarth]

Newer versions of Marvell PXA3xx NFC also support BCH and therefore
higher ECC strengths than 1. Prepare for different ECC strength by
factoring out ECC init into separate functions by strength. Also,
add a new host variable that indicates BCH ECC.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 36 +++++++++++++++++++++++++++++-------
 1 file changed, 29 insertions(+), 7 deletions(-)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index 8dcbc3dc045e..217aacd7201a 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -156,6 +156,7 @@ struct mrvl_nand_host {
 	int			num_cs;		/* avaiable CS signals */
 	int			cs;		/* selected chip 0/1 */
 	int			use_ecc;	/* use HW ECC ? */
+	int			ecc_bch;	/* HW ECC is BCH */
 	int			use_spare;	/* use spare ? */
 	int			flash_bbt;
 
@@ -824,32 +825,53 @@ static void mrvl_nand_config_flash(struct mrvl_nand_host *host)
 	host->reg_ndcr = ndcr;
 }
 
-static int pxa_ecc_init(struct mrvl_nand_host *host,
-			struct nand_ecc_ctrl *ecc,
-			int strength, int ecc_stepsize, int page_size)
+static int pxa_ecc_strength1(struct mrvl_nand_host *host,
+		struct nand_ecc_ctrl *ecc, int ecc_stepsize, int page_size)
 {
-	if (strength == 1 && ecc_stepsize == 512 && page_size == 2048) {
+	if (ecc_stepsize == 512 && page_size == 2048) {
 		host->chunk_size = 2048;
 		host->spare_size = 40;
 		host->ecc_size = 24;
+		host->ecc_bch = 0;
 		ecc->mode = NAND_ECC_HW;
 		ecc->size = 512;
 		ecc->strength = 1;
 		ecc->layout = &ecc_layout_2KB_hwecc;
+		return 0;
+	}
 
-	} else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) {
+	if (ecc_stepsize == 512 && page_size == 512) {
 		host->chunk_size = 512;
 		host->spare_size = 8;
 		host->ecc_size = 8;
+		host->ecc_bch = 0;
 		ecc->mode = NAND_ECC_HW;
 		ecc->size = 512;
 		ecc->layout = &ecc_layout_512B_hwecc;
 		ecc->strength = 1;
-	} else {
+		return 0;
+	}
+
+	return -ENODEV;
+}
+
+static int pxa_ecc_init(struct mrvl_nand_host *host,
+			struct nand_ecc_ctrl *ecc,
+			int strength, int ecc_stepsize, int page_size)
+{
+	int ret = -ENODEV;
+
+	switch (strength) {
+	case 1:
+		ret = pxa_ecc_strength1(host, ecc, ecc_stepsize, page_size);
+		break;
+	}
+
+	if (ret) {
 		dev_err(host->dev,
 			"ECC strength %d at page size %d is not supported\n",
 			strength, page_size);
-		return -ENODEV;
+		return ret;
 	}
 
 	dev_info(host->dev, "ECC strength %d, ECC step size %d\n",
-- 
2.1.4


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[PATCH v2 13/19] mtd: nand_mrvl_nfc: Add hwflags to distinguish different HW versions

[Sebastian Hesselbarth]

Marvell PXA3xx NAND flash controller IP has been reused in later SoCs
with additional HW features. Add HW BCH ECC as the first known HW
difference.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index 217aacd7201a..ac1cb3fa9ae3 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -129,6 +129,10 @@
 #define nand_readsl(host, off, buf, nbbytes)		\
 	readsl((host)->mmio_base + (off), buf, nbbytes)
 
+struct mrvl_nand_variant {
+	unsigned int	hwflags;
+};
+
 struct mrvl_nand_host {
 	struct mtd_info		mtd;
 	struct nand_chip	chip;
@@ -142,6 +146,8 @@ struct mrvl_nand_host {
 	size_t			read_id_bytes;
 
 	void __iomem		*mmio_base;
+	unsigned int		hwflags;
+#define HWFLAGS_ECC_BCH		BIT(0)
 
 	unsigned int		buf_start;
 	unsigned int		buf_count;
@@ -235,9 +241,14 @@ static struct nand_ecclayout ecc_layout_2KB_hwecc = {
 #define mtd_info_to_host(mtd) ((struct mrvl_nand_host *) \
 			       (((struct nand_chip *)((mtd)->priv))->priv))
 
+static const struct mrvl_nand_variant pxa3xx_variant = {
+	.hwflags	= 0,
+};
+
 static struct of_device_id mrvl_nand_dt_ids[] = {
 	{
 		.compatible = "marvell,pxa3xx-nand",
+		.data = &pxa3xx_variant,
 	},
 	{}
 };
@@ -1006,10 +1017,17 @@ static struct mrvl_nand_host *alloc_nand_resource(struct device_d *dev)
 static int mrvl_nand_probe_dt(struct mrvl_nand_host *host)
 {
 	struct device_node *np = host->dev->device_node;
+	const struct of_device_id *match;
+	const struct mrvl_nand_variant *variant;
 
 	if (!IS_ENABLED(CONFIG_OFTREE) || host->dev->platform_data)
 		return 0;
 
+	match = of_match_node(mrvl_nand_dt_ids, np);
+	if (!match)
+		return -EINVAL;
+	variant = match->data;
+
 	if (of_get_property(np, "marvell,nand-keep-config", NULL))
 		host->keep_config = 1;
 	of_property_read_u32(np, "num-cs", &host->num_cs);
@@ -1024,6 +1042,8 @@ static int mrvl_nand_probe_dt(struct mrvl_nand_host *host)
 	if (host->ecc_step < 0)
 		host->ecc_step = 0;
 
+	host->hwflags = variant->hwflags;
+
 	return 0;
 }
 
-- 
2.1.4


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[PATCH v2 14/19] mtd: nand_mrvl_nfc: Add support for 4bit BCH HW ECC

[Sebastian Hesselbarth]

Add support for 4bit HW ECC modes supported by later IP versions.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 65 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index ac1cb3fa9ae3..3e9fccdffefe 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -227,6 +227,31 @@ static struct nand_ecclayout ecc_layout_2KB_hwecc = {
 	.oobfree = { {0, 40} }
 };
 
+static struct nand_ecclayout ecc_layout_2KB_bch4bit = {
+	.eccbytes = 32,
+	.eccpos = {
+		32, 33, 34, 35, 36, 37, 38, 39,
+		40, 41, 42, 43, 44, 45, 46, 47,
+		48, 49, 50, 51, 52, 53, 54, 55,
+		56, 57, 58, 59, 60, 61, 62, 63},
+	.oobfree = { {2, 30} }
+};
+
+static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
+	.eccbytes = 64,
+	.eccpos = {
+		32,  33,  34,  35,  36,  37,  38,  39,
+		40,  41,  42,  43,  44,  45,  46,  47,
+		48,  49,  50,  51,  52,  53,  54,  55,
+		56,  57,  58,  59,  60,  61,  62,  63,
+		96,  97,  98,  99,  100, 101, 102, 103,
+		104, 105, 106, 107, 108, 109, 110, 111,
+		112, 113, 114, 115, 116, 117, 118, 119,
+		120, 121, 122, 123, 124, 125, 126, 127},
+	/* Bootrom looks in bytes 0 & 5 for bad blocks */
+	.oobfree = { {1, 4}, {6, 26}, {64, 32} }
+};
+
 #define NDTR0_tCH(c)	(min((c), 7) << 19)
 #define NDTR0_tCS(c)	(min((c), 7) << 16)
 #define NDTR0_tWH(c)	(min((c), 7) << 11)
@@ -866,6 +891,43 @@ static int pxa_ecc_strength1(struct mrvl_nand_host *host,
 	return -ENODEV;
 }
 
+static int pxa_ecc_strength4(struct mrvl_nand_host *host,
+		struct nand_ecc_ctrl *ecc, int ecc_stepsize, int page_size)
+{
+	if (!(host->hwflags & HWFLAGS_ECC_BCH))
+		return -ENODEV;
+
+	/*
+	 * Required ECC: 4-bit correction per 512 bytes
+	 * Select: 16-bit correction per 2048 bytes
+	 */
+	if (ecc_stepsize == 512 && page_size == 2048) {
+		host->chunk_size = 2048;
+		host->spare_size = 32;
+		host->ecc_size = 32;
+		host->ecc_bch = 1;
+		ecc->mode = NAND_ECC_HW;
+		ecc->size = 2048;
+		ecc->layout = &ecc_layout_2KB_bch4bit;
+		ecc->strength = 16;
+		return 0;
+	}
+
+	if (ecc_stepsize == 512 && page_size == 4096) {
+		host->chunk_size = 2048;
+		host->spare_size = 32;
+		host->ecc_size = 32;
+		host->ecc_bch = 1;
+		ecc->mode = NAND_ECC_HW;
+		ecc->size = 2048;
+		ecc->layout = &ecc_layout_4KB_bch4bit;
+		ecc->strength = 16;
+		return 0;
+	}
+
+	return -ENODEV;
+}
+
 static int pxa_ecc_init(struct mrvl_nand_host *host,
 			struct nand_ecc_ctrl *ecc,
 			int strength, int ecc_stepsize, int page_size)
@@ -876,6 +938,9 @@ static int pxa_ecc_init(struct mrvl_nand_host *host,
 	case 1:
 		ret = pxa_ecc_strength1(host, ecc, ecc_stepsize, page_size);
 		break;
+	case 4:
+		ret = pxa_ecc_strength4(host, ecc, ecc_stepsize, page_size);
+		break;
 	}
 
 	if (ret) {
-- 
2.1.4


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[PATCH v2 15/19] mtd: nand_mrvl_nfc: Add support for 8bit BCH HW ECC

[Sebastian Hesselbarth]

Add support for 8bit HW ECC modes supported by later IP versions.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index 3e9fccdffefe..f43200dcf2c7 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -252,6 +252,17 @@ static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
 	.oobfree = { {1, 4}, {6, 26}, {64, 32} }
 };
 
+static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
+	.eccbytes = 64,
+	.eccpos = {
+		32,  33,  34,  35,  36,  37,  38,  39,
+		40,  41,  42,  43,  44,  45,  46,  47,
+		48,  49,  50,  51,  52,  53,  54,  55,
+		56,  57,  58,  59,  60,  61,  62,  63},
+	/* Bootrom looks in bytes 0 & 5 for bad blocks */
+	.oobfree = { {1, 4}, {6, 26} }
+};
+
 #define NDTR0_tCH(c)	(min((c), 7) << 19)
 #define NDTR0_tCS(c)	(min((c), 7) << 16)
 #define NDTR0_tWH(c)	(min((c), 7) << 11)
@@ -928,6 +939,31 @@ static int pxa_ecc_strength4(struct mrvl_nand_host *host,
 	return -ENODEV;
 }
 
+static int pxa_ecc_strength8(struct mrvl_nand_host *host,
+		struct nand_ecc_ctrl *ecc, int ecc_stepsize, int page_size)
+{
+	if (!(host->hwflags & HWFLAGS_ECC_BCH))
+		return -ENODEV;
+
+	/*
+	 * Required ECC: 8-bit correction per 512 bytes
+	 * Select: 16-bit correction per 1024 bytes
+	 */
+	if (ecc_stepsize == 512 && page_size == 4096) {
+		host->chunk_size = 1024;
+		host->spare_size = 0;
+		host->ecc_size = 32;
+		host->ecc_bch = 1;
+		ecc->mode = NAND_ECC_HW;
+		ecc->size = 1024;
+		ecc->layout = &ecc_layout_4KB_bch8bit;
+		ecc->strength = 16;
+		return 0;
+	}
+
+	return -ENODEV;
+}
+
 static int pxa_ecc_init(struct mrvl_nand_host *host,
 			struct nand_ecc_ctrl *ecc,
 			int strength, int ecc_stepsize, int page_size)
@@ -941,6 +977,9 @@ static int pxa_ecc_init(struct mrvl_nand_host *host,
 	case 4:
 		ret = pxa_ecc_strength4(host, ecc, ecc_stepsize, page_size);
 		break;
+	case 8:
+		ret = pxa_ecc_strength8(host, ecc, ecc_stepsize, page_size);
+		break;
 	}
 
 	if (ret) {
-- 
2.1.4


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[PATCH v2 16/19] mtd: nand_mrvl_nfc: Add support for HW BCH ECC

[Sebastian Hesselbarth]

Add support for HW BCH ECC for those HW versions that support it.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index f43200dcf2c7..a5ac66195217 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -92,6 +92,8 @@
 #define NDSR_RDDREQ		(0x1 << 1)
 #define NDSR_WRCMDREQ		(0x1)
 
+#define NDECCCTRL_BCH_EN	BIT(0)
+
 #define NDCB0_LEN_OVRD		(0x1 << 28)
 #define NDCB0_ST_ROW_EN         (0x1 << 26)
 #define NDCB0_AUTO_RS		(0x1 << 25)
@@ -426,6 +428,17 @@ static void mrvl_nand_start(struct mrvl_nand_host *host)
 {
 	uint32_t ndcr;
 
+	if (host->hwflags & HWFLAGS_ECC_BCH) {
+		uint32_t reg = nand_readl(host, NDECCCTRL);
+
+		if (host->use_ecc && host->ecc_bch)
+			reg |= NDECCCTRL_BCH_EN;
+		else
+			reg &= ~NDECCCTRL_BCH_EN;
+
+		nand_writel(host, NDECCCTRL, reg);
+	}
+
 	ndcr = host->reg_ndcr;
 	if (host->use_ecc)
 		ndcr |= NDCR_ECC_EN;
@@ -794,8 +807,14 @@ static int mrvl_nand_read_page_hwecc(struct mtd_info *mtd,
 		else
 			ret = -EBADMSG;
 	}
-	if (ndsr & NDSR_CORERR)
+	if (ndsr & NDSR_CORERR) {
 		ret = 1;
+		if ((host->hwflags & HWFLAGS_ECC_BCH) && host->ecc_bch) {
+			ret = NDSR_ERR_CNT(ndsr);
+			ndsr &= ~(NDSR_ERR_CNT_MASK << NDSR_ERR_CNT_OFF);
+			nand_writel(host, NDSR, ndsr);
+		}
+	}
 	dev_dbg(host->dev, "%s(buf=%p, page=%d, oob_required=%d) => %d\n",
 		__func__, buf, page, oob_required, ret);
 	return ret;
@@ -1008,6 +1027,11 @@ static int mrvl_nand_scan(struct mtd_info *mtd)
 	ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
 	host->reg_ndcr = ndcr;
 
+	/* Device detection must be done with BCH ECC disabled */
+	if (host->hwflags & HWFLAGS_ECC_BCH)
+		nand_writel(host, NDECCCTRL,
+			    nand_readl(host, NDECCCTRL) & ~NDECCCTRL_BCH_EN);
+
 	mrvl_nand_set_timing(host, true);
 	if (nand_scan_ident(mtd, 1, NULL)) {
 		host->reg_ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C;
-- 
2.1.4


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[PATCH v2 17/19] mtd: nand_mrvl_nfc: Add support for NDCB3 register

[Sebastian Hesselbarth]

Newer versions of PXA3xx NAND controller support a 4th Command Buffer
register. Add the required HWFLAGS and additional write to NDCB0.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index a5ac66195217..fec18d1fc95a 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -53,6 +53,7 @@
 #define NDCB0		(0x48) /* Command Buffer0 */
 #define NDCB1		(0x4C) /* Command Buffer1 */
 #define NDCB2		(0x50) /* Command Buffer2 */
+#define NDCB3		(0x54) /* Command Buffer3 */
 
 #define NDCR_SPARE_EN		(0x1 << 31)
 #define NDCR_ECC_EN		(0x1 << 30)
@@ -150,6 +151,7 @@ struct mrvl_nand_host {
 	void __iomem		*mmio_base;
 	unsigned int		hwflags;
 #define HWFLAGS_ECC_BCH		BIT(0)
+#define HWFLAGS_HAS_NDCB3	BIT(1)
 
 	unsigned int		buf_start;
 	unsigned int		buf_count;
@@ -465,12 +467,19 @@ static void mrvl_nand_start(struct mrvl_nand_host *host)
 		dev_err(host->dev, "Waiting for command request failed\n");
 	} else {
 		/*
-		 * Writing 12 bytes to NDBC0 sets NDBC0, NDBC1 and NDBC2 !
+		 * Command buffer registers NDCB{0-2,3}
+		 * must be loaded by writing directly either 12 or 16
+		 * bytes directly to NDCB0, four bytes at a time.
+		 *
+		 * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
+		 * but each NDCBx register can be read.
 		 */
 		nand_writel(host, NDSR, NDSR_WRCMDREQ);
 		nand_writel(host, NDCB0, host->ndcb0);
 		nand_writel(host, NDCB0, host->ndcb1);
 		nand_writel(host, NDCB0, host->ndcb2);
+		if (host->hwflags & HWFLAGS_HAS_NDCB3)
+			nand_writel(host, NDCB0, host->ndcb3);
 	}
 }
 
-- 
2.1.4


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[PATCH v2 18/19] mtd: nand_mrvl_nfc: Add support for Marvell Armada 370/XP

[Sebastian Hesselbarth]

Marvell PXA3xx and Armada 370/XP share the same NAND controller IP
with some minor differences. With support for controller IP v2, now
allow to build the driver on Armada 370/XP.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 drivers/mtd/nand/Kconfig         | 7 ++++---
 drivers/mtd/nand/nand_mrvl_nfc.c | 8 ++++++++
 2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 3426ec055756..2b4a478a03dd 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -99,10 +99,11 @@ config NAND_ORION
 
 config NAND_MRVL_NFC
 	bool
-	prompt "Marvell NAND driver"
-	depends on ARCH_PXA3XX
+	prompt "Marvell PXA3xx NAND driver"
+	depends on ARCH_ARMADA_370 || ARCH_ARMADA_XP || ARCH_PXA3XX
 	help
-	  Support for the PXA3xx NAND controller, present in pxa3xx SoCs.
+	  Support for the PXA3xx NAND controller, present in Armada 370/XP and
+	  PXA3xx SoCs.
 
 config NAND_ATMEL
 	bool
diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index fec18d1fc95a..ce5786c01920 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -285,11 +285,19 @@ static const struct mrvl_nand_variant pxa3xx_variant = {
 	.hwflags	= 0,
 };
 
+static const struct mrvl_nand_variant armada370_variant = {
+	.hwflags	= HWFLAGS_ECC_BCH | HWFLAGS_HAS_NDCB3,
+};
+
 static struct of_device_id mrvl_nand_dt_ids[] = {
 	{
 		.compatible = "marvell,pxa3xx-nand",
 		.data = &pxa3xx_variant,
 	},
+	{
+		.compatible = "marvell,armada370-nand",
+		.data = &armada370_variant,
+	},
 	{}
 };
 
-- 
2.1.4


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[PATCH v2 19/19] mtd: nand_mrvl_nfc: Add optimized timings for Samsung K9K8G08U

[Sebastian Hesselbarth]

This adds optimized timings for Samsung K9K8G08U 1Gb NAND flash.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
 drivers/mtd/nand/nand_mrvl_nfc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/nand/nand_mrvl_nfc.c b/drivers/mtd/nand/nand_mrvl_nfc.c
index ce5786c01920..284a3b68822a 100644
--- a/drivers/mtd/nand/nand_mrvl_nfc.c
+++ b/drivers/mtd/nand/nand_mrvl_nfc.c
@@ -331,6 +331,7 @@ static struct mrvl_nand_timing timings[] = {
 	{ 0x46ec, 10,  0, 20,  40, 30,  40, 11123, 110, 10, },
 	{ 0xdaec, 10,  0, 20,  40, 30,  40, 11123, 110, 10, },
 	{ 0xd7ec, 10,  0, 20,  40, 30,  40, 11123, 110, 10, },
+	{ 0xd3ec,  5, 20, 10,  12, 10,  12, 25000,  60, 10, },
 	{ 0xa12c, 10, 25, 15,  25, 15,  30, 25000,  60, 10, },
 	{ 0xb12c, 10, 25, 15,  25, 15,  30, 25000,  60, 10, },
 	{ 0xdc2c, 10, 25, 15,  25, 15,  30, 25000,  60, 10, },
-- 
2.1.4


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Re: [PATCH v2 12/19] mtd: nand_mrvl_nfc: Prepare for different HW ECC strengths

[Trent Piepho]

On Fri, 2015-11-20 at 20:36 +0100, Sebastian Hesselbarth wrote:

> +
> +static int pxa_ecc_init(struct mrvl_nand_host *host,
> +			struct nand_ecc_ctrl *ecc,
> +			int strength, int ecc_stepsize, int page_size)
> +{
> +	int ret = -ENODEV;
> +
> +	switch (strength) {
> +	case 1:
> +		ret = pxa_ecc_strength1(host, ecc, ecc_stepsize, page_size);
> +		break;
> +	}

It would be a bit more clear to write this as:

switch (strength) {
case 1:
        ret = pxa_ecc_strength1(...);
        break;
default:
        ret = -ENODEV;
        break;
}

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Re: [PATCH v2 12/19] mtd: nand_mrvl_nfc: Prepare for different HW ECC strengths

[Sascha Hauer]

On Fri, Nov 20, 2015 at 08:38:28PM +0000, Trent Piepho wrote:
> On Fri, 2015-11-20 at 20:36 +0100, Sebastian Hesselbarth wrote:
> 
> > +
> > +static int pxa_ecc_init(struct mrvl_nand_host *host,
> > +			struct nand_ecc_ctrl *ecc,
> > +			int strength, int ecc_stepsize, int page_size)
> > +{
> > +	int ret = -ENODEV;
> > +
> > +	switch (strength) {
> > +	case 1:
> > +		ret = pxa_ecc_strength1(host, ecc, ecc_stepsize, page_size);
> > +		break;
> > +	}
> 
> It would be a bit more clear to write this as:
> 
> switch (strength) {
> case 1:
>         ret = pxa_ecc_strength1(...);
>         break;
> default:
>         ret = -ENODEV;
>         break;
> }

Indeed. Changed that while applying.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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Re: [PATCH v2 00/19] Armada 370/XP NAND driver

[Sascha Hauer]

On Fri, Nov 20, 2015 at 08:35:53PM +0100, Sebastian Hesselbarth wrote:
> This is v2 of the patch set that adds support for the NAND flash
> controller found on Marvell Armada 370/XP SoCs. The IP is the same
> as for PXA3xx SoCs, so we can also reuse the driver. However, this
> needs some rework of the existing driver.
> 
> Patch 1 imports some mtd OF helpers from Linux for ECC propery
> parsing.
> 
> Patch 2 clarifies Marvell Orion NAND Kconfig entry to distinguish
> it from Armada 370/XP NAND support in PXA3xx NAND.
> 
> Patches 3-6 free nand_mrvl_nfc from mach-pxa dependency by
> adding common clock support to mach-pxa and rework the driver
> to get rid of pxa_get_nandclk().
> 
> Patches 7-13 comprise cleanup and preparation for the
> addition of Armada 370/XP version of the NAND controller IP.
> 
> Patches 14-18 add features found on Armada XP NAND controller
> only.
> 
> Finally, Patch 19 adds optimized timings for the NAND flash
> found on Lenovo ix4-300d.
> 
> The series is based on today's next with Robert's patiently
> confirmed Tested-by on mach-pxa. I have tested this on IX4.

Applied, thanks, and thanks for testing Robert.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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