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From: Lucas Stach <l.stach@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH 2/3] ARM: imx6: don't execute IPU QoS setup on MX6 SX/SL
Date: Thu, 15 Sep 2016 13:10:22 +0200	[thread overview]
Message-ID: <1473937823-30706-2-git-send-email-l.stach@pengutronix.de> (raw)
In-Reply-To: <1473937823-30706-1-git-send-email-l.stach@pengutronix.de>

SX and SL variants only include the PXP and have no IPU, so
skip any IPU related QoS setup.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/mach-imx/imx6.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 07d3f57d8dcc..567559033770 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -99,6 +99,10 @@ void imx6_setup_ipu_qos(void)
 	void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR;
 	uint32_t val;
 
+	if (!cpu_mx6_is_mx6q() && !cpu_mx6_is_mx6d() &&
+	    !cpu_mx6_is_mx6dl() && cpu_mx6_is_mx6s())
+		return;
+
 	val = readl(iomux + IOMUXC_GPR4);
 	val |= IMX6Q_GPR4_VPU_WR_CACHE_SEL | IMX6Q_GPR4_VPU_RD_CACHE_SEL |
 		IMX6Q_GPR4_VPU_P_WR_CACHE_VAL | IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |
-- 
2.8.1


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  reply	other threads:[~2016-09-15 11:10 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-15 11:10 [PATCH 1/3] ARM: imx6: split out IPU QoS setup Lucas Stach
2016-09-15 11:10 ` Lucas Stach [this message]
2016-09-15 11:10 ` [PATCH 3/3] ARM: imx6qp: set NoC regulator to bypass Lucas Stach
2016-09-16  7:47 ` [PATCH 1/3] ARM: imx6: split out IPU QoS setup Sascha Hauer

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