From: Christian Hemp <c.hemp@phytec.de>
To: barebox@lists.infradead.org
Cc: Daniel Schultz <d.schultz@phytec.de>
Subject: [PATCH 1/2] nand: imx6: Changed default NAND clock
Date: Thu, 20 Oct 2016 15:40:06 +0200 [thread overview]
Message-ID: <1476970807-43811-1-git-send-email-c.hemp@phytec.de> (raw)
From: Daniel Schultz <d.schultz@phytec.de>
The Barebox recognized false bad erase blocks while booting from a
Spansion NAND (1). This error occurred due a to high clock. The
Kernel sets the default NAND clock to 22Mhz. So, to fix this error and
to be more identical with the Kernel, the Barebox should be too.
1: nand: NAND device: Manufacturer ID: 0x01, Chip ID: 0xd3 (AMD/Spansion
S34ML08G2), 1024MiB, page size: 2048, OOB size: 128
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Tested-by: Stefan Lengfeld <s.lengfeld@phytec.de>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
---
drivers/mtd/nand/nand_mxs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
index 01aa063..fe955e8 100644
--- a/drivers/mtd/nand/nand_mxs.c
+++ b/drivers/mtd/nand/nand_mxs.c
@@ -2145,7 +2145,7 @@ static int mxs_nand_probe(struct device_d *dev)
if (mxs_nand_is_imx6(nand_info)) {
clk_disable(nand_info->clk);
- clk_set_rate(nand_info->clk, 96000000);
+ clk_set_rate(nand_info->clk, 22000000);
clk_enable(nand_info->clk);
nand_info->dma_channel_base = 0;
} else {
--
1.9.1
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next reply other threads:[~2016-10-20 13:40 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-20 13:40 Christian Hemp [this message]
2016-10-20 13:40 ` [PATCH 2/2] mtd: nand: nand_mxs: Fix readtotal calculation Christian Hemp
2016-10-21 7:18 ` Sascha Hauer
2016-10-24 8:51 ` Stefan Lengfeld
2016-10-21 7:11 ` [PATCH 1/2] nand: imx6: Changed default NAND clock Sascha Hauer
2016-10-24 9:20 ` Stefan Lengfeld
2016-10-25 6:21 ` Sascha Hauer
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