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From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: barebox@lists.infradead.org
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Subject: [PATCH v2 18/28] i.MX: i2c: Use read/write adapter functions
Date: Wed,  9 Nov 2016 08:14:06 -0800	[thread overview]
Message-ID: <1478708056-7875-19-git-send-email-andrew.smirnov@gmail.com> (raw)
In-Reply-To: <1478708056-7875-1-git-send-email-andrew.smirnov@gmail.com>

Use read/write adapter functions instead of directly calling to
readb/writeb. This is needed to prepare driver code to support Vybrid
SoC's variant of this block.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 drivers/i2c/busses/i2c-imx.c | 88 +++++++++++++++++++++++---------------------
 1 file changed, 46 insertions(+), 42 deletions(-)

diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index e407896..ec40475 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -115,14 +115,27 @@ struct fsl_i2c_struct {
 };
 #define to_fsl_i2c_struct(a)	container_of(a, struct fsl_i2c_struct, adapter)
 
+static inline void fsl_i2c_write_reg(unsigned int val,
+				     struct fsl_i2c_struct *i2c_fsl,
+				     unsigned int reg)
+{
+	writeb(val, i2c_fsl->base + reg);
+}
+
+static inline unsigned char fsl_i2c_read_reg(struct fsl_i2c_struct *i2c_fsl,
+					     unsigned int reg)
+{
+	return readb(i2c_fsl->base + reg);
+}
+
 #ifdef CONFIG_I2C_DEBUG
 static void i2c_fsl_dump_reg(struct i2c_adapter *adapter)
 {
 	struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
 	u32 reg_cr, reg_sr;
 
-	reg_cr = readb(i2c_fsl->base + FSL_I2C_I2CR);
-	reg_sr = readb(i2c_fsl->base + FSL_I2C_I2SR);
+	reg_cr = fsl_i2c_read_reg(i2c_fsl, FSL_I2C_I2CR);
+	reg_sr = fsl_i2c_read_reg(i2c_fsl, FSL_I2C_I2SR);
 
 	dev_dbg(adapter->dev, "CONTROL:\t"
 		"IEN =%d, IIEN=%d, MSTA=%d, MTX =%d, TXAK=%d, RSTA=%d\n",
@@ -144,16 +157,16 @@ static inline void i2c_fsl_dump_reg(struct i2c_adapter *adapter)
 }
 #endif
 
+
 static int i2c_fsl_bus_busy(struct i2c_adapter *adapter, int for_busy)
 {
 	struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
-	void __iomem *base = i2c_fsl->base;
 	uint64_t start;
 	unsigned int temp;
 
 	start = get_time_ns();
 	while (1) {
-		temp = readb(base + FSL_I2C_I2SR);
+		temp = fsl_i2c_read_reg(i2c_fsl, FSL_I2C_I2SR);
 		if (for_busy && (temp & I2SR_IBB))
 			break;
 		if (!for_busy && !(temp & I2SR_IBB))
@@ -172,12 +185,11 @@ static int i2c_fsl_bus_busy(struct i2c_adapter *adapter, int for_busy)
 static int i2c_fsl_trx_complete(struct i2c_adapter *adapter)
 {
 	struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
-	void __iomem *base = i2c_fsl->base;
 	uint64_t start;
 
 	start = get_time_ns();
 	while (1) {
-		unsigned int reg = readb(base + FSL_I2C_I2SR);
+		unsigned int reg = fsl_i2c_read_reg(i2c_fsl, FSL_I2C_I2SR);
 		if (reg & I2SR_IIF)
 			break;
 
@@ -186,7 +198,7 @@ static int i2c_fsl_trx_complete(struct i2c_adapter *adapter)
 			return -EIO;
 		}
 	}
-	writeb(0, base + FSL_I2C_I2SR);
+	fsl_i2c_write_reg(0, i2c_fsl, FSL_I2C_I2SR);
 
 	return 0;
 }
@@ -194,12 +206,11 @@ static int i2c_fsl_trx_complete(struct i2c_adapter *adapter)
 static int i2c_fsl_acked(struct i2c_adapter *adapter)
 {
 	struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
-	void __iomem *base = i2c_fsl->base;
 	uint64_t start;
 
 	start = get_time_ns();
 	while (1) {
-		unsigned int reg = readb(base + FSL_I2C_I2SR);
+		unsigned int reg = fsl_i2c_read_reg(i2c_fsl, FSL_I2C_I2SR);
 		if (!(reg & I2SR_RXAK))
 			break;
 
@@ -215,25 +226,24 @@ static int i2c_fsl_acked(struct i2c_adapter *adapter)
 static int i2c_fsl_start(struct i2c_adapter *adapter)
 {
 	struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
-	void __iomem *base = i2c_fsl->base;
 	unsigned int temp = 0;
 	int result;
 
-	writeb(i2c_fsl->ifdr, base + FSL_I2C_IFDR);
+	fsl_i2c_write_reg(i2c_fsl->ifdr, fsl_i2c, FSL_I2C_IFDR);
 	if (i2c_fsl->dfsrr != -1)
-		writeb(i2c_fsl->dfsrr, base + FSL_I2C_DFSRR);
+		fsl_i2c_write_reg(i2c_fsl->dfsrr, fsl_i2c, FSL_I2C_DFSRR);
 
 	/* Enable I2C controller */
-	writeb(0, base + FSL_I2C_I2SR);
-	writeb(I2CR_IEN, base + FSL_I2C_I2CR);
+	fsl_i2c_write_reg(0, fsl_i2c, FSL_I2C_I2SR);
+	fsl_i2c_write_reg(I2CR_IEN, fsl_i2c, FSL_I2C_I2CR);
 
 	/* Wait controller to be stable */
 	udelay(100);
 
 	/* Start I2C transaction */
-	temp = readb(base + FSL_I2C_I2CR);
+	temp = fsl_i2c_read_reg(i2c_fsl, FSL_I2C_I2CR);
 	temp |= I2CR_MSTA;
-	writeb(temp, base + FSL_I2C_I2CR);
+	fsl_i2c_write_reg(temp, fsl_i2c, FSL_I2C_I2CR);
 
 	result = i2c_fsl_bus_busy(adapter, 1);
 	if (result) {
@@ -246,7 +256,7 @@ static int i2c_fsl_start(struct i2c_adapter *adapter)
 	i2c_fsl->stopped = 0;
 
 	temp |= I2CR_MTX | I2CR_TXAK;
-	writeb(temp, base + FSL_I2C_I2CR);
+	fsl_i2c_write_reg(temp, fsl_i2c, FSL_I2C_I2CR);
 
 	return result;
 }
@@ -254,14 +264,13 @@ static int i2c_fsl_start(struct i2c_adapter *adapter)
 static void i2c_fsl_stop(struct i2c_adapter *adapter)
 {
 	struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
-	void __iomem *base = i2c_fsl->base;
 	unsigned int temp = 0;
 
 	if (!i2c_fsl->stopped) {
 		/* Stop I2C transaction */
-		temp = readb(base + FSL_I2C_I2CR);
+		temp = fsl_i2c_read_reg(i2c_fsl, FSL_I2C_I2CR);
 		temp &= ~(I2CR_MSTA | I2CR_MTX);
-		writeb(temp, base + FSL_I2C_I2CR);
+		fsl_i2c_write_reg(temp, fsl_i2c, FSL_I2C_I2CR);
 		/* wait for the stop condition to be send, otherwise the i2c
 		 * controller is disabled before the STOP is sent completely */
 		i2c_fsl->stopped = i2c_fsl_bus_busy(adapter, 0) ? 0 : 1;
@@ -273,14 +282,13 @@ static void i2c_fsl_stop(struct i2c_adapter *adapter)
 	}
 
 	/* Disable I2C controller, and force our state to stopped */
-	writeb(0, base + FSL_I2C_I2CR);
+	fsl_i2c_write_reg(0, fsl_i2c, FSL_I2C_I2CR);
 }
 
 #ifdef CONFIG_PPC
 static void i2c_fsl_set_clk(struct fsl_i2c_struct *i2c_fsl,
 				    unsigned int rate)
 {
-	void __iomem *base;
 	unsigned int i2c_clk;
 	unsigned short divider;
 	/*
@@ -295,7 +303,6 @@ static void i2c_fsl_set_clk(struct fsl_i2c_struct *i2c_fsl,
 	unsigned long c_div, est_div;
 
 	fdr = 0x31; /* Default if no FDR found */
-	base = i2c_fsl->base;
 	i2c_clk = fsl_get_i2c_freq();
 	divider = min((unsigned short)(i2c_clk / rate), (unsigned short) -1);
 
@@ -387,7 +394,6 @@ static void i2c_fsl_set_clk(struct fsl_i2c_struct *i2c_fsl,
 static int i2c_fsl_write(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 {
 	struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
-	void __iomem *base = i2c_fsl->base;
 	int i, result;
 
 	if ( !(msgs->flags & I2C_M_DATA_ONLY) ) {
@@ -396,7 +402,7 @@ static int i2c_fsl_write(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 			__func__, msgs->addr << 1);
 
 		/* write slave address */
-		writeb(msgs->addr << 1, base + FSL_I2C_I2DR);
+		fsl_i2c_write_reg(msgs->addr << 1, fsl_i2c, FSL_I2C_I2DR);
 
 		result = i2c_fsl_trx_complete(adapter);
 		if (result)
@@ -411,7 +417,7 @@ static int i2c_fsl_write(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 		dev_dbg(&adapter->dev,
 			"<%s> write byte: B%d=0x%02X\n",
 			__func__, i, msgs->buf[i]);
-		writeb(msgs->buf[i], base + FSL_I2C_I2DR);
+		fsl_i2c_write_reg(msgs->buf[i], fsl_i2c, FSL_I2C_I2DR);
 
 		result = i2c_fsl_trx_complete(adapter);
 		if (result)
@@ -426,12 +432,11 @@ static int i2c_fsl_write(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 static int i2c_fsl_read(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 {
 	struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
-	void __iomem *base = i2c_fsl->base;
 	int i, result;
 	unsigned int temp;
 
 	/* clear IIF */
-	writeb(0x0, base + FSL_I2C_I2SR);
+	fsl_i2c_write_reg(0x0, fsl_i2c, FSL_I2C_I2SR);
 
 	if ( !(msgs->flags & I2C_M_DATA_ONLY) ) {
 		dev_dbg(&adapter->dev,
@@ -439,7 +444,7 @@ static int i2c_fsl_read(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 			__func__, (msgs->addr << 1) | 0x01);
 
 		/* write slave address */
-		writeb((msgs->addr << 1) | 0x01, base + FSL_I2C_I2DR);
+		fsl_i2c_write_reg((msgs->addr << 1) | 0x01, fsl_i2c, FSL_I2C_I2DR);
 
 		result = i2c_fsl_trx_complete(adapter);
 		if (result)
@@ -450,13 +455,13 @@ static int i2c_fsl_read(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 	}
 
 	/* setup bus to read data */
-	temp = readb(base + FSL_I2C_I2CR);
+	temp = fsl_i2c_read_reg(i2c_fsl, FSL_I2C_I2CR);
 	temp &= ~I2CR_MTX;
 	if (msgs->len - 1)
 		temp &= ~I2CR_TXAK;
-	writeb(temp, base + FSL_I2C_I2CR);
+	fsl_i2c_write_reg(temp, fsl_i2c, FSL_I2C_I2CR);
 
-	readb(base + FSL_I2C_I2DR);	/* dummy read */
+	fsl_i2c_read_reg(i2c_fsl, FSL_I2C_I2DR);	/* dummy read */
 
 	/* read data */
 	for (i = 0; i < msgs->len; i++) {
@@ -469,9 +474,9 @@ static int i2c_fsl_read(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 			 * It must generate STOP before read I2DR to prevent
 			 * controller from generating another clock cycle
 			 */
-			temp = readb(base + FSL_I2C_I2CR);
+			temp = fsl_i2c_read_reg(i2c_fsl, FSL_I2C_I2CR);
 			temp &= ~(I2CR_MSTA | I2CR_MTX);
-			writeb(temp, base + FSL_I2C_I2CR);
+			fsl_i2c_write_reg(temp, fsl_i2c, FSL_I2C_I2CR);
 
 			/*
 			 * adding this delay helps on low bitrates
@@ -481,11 +486,11 @@ static int i2c_fsl_read(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 			i2c_fsl_bus_busy(adapter, 0);
 			i2c_fsl->stopped = 1;
 		} else if (i == (msgs->len - 2)) {
-			temp = readb(base + FSL_I2C_I2CR);
+			temp = fsl_i2c_read_reg(i2c_fsl, FSL_I2C_I2CR);
 			temp |= I2CR_TXAK;
-			writeb(temp, base + FSL_I2C_I2CR);
+			fsl_i2c_write_reg(temp, fsl_i2c, FSL_I2C_I2CR);
 		}
-		msgs->buf[i] = readb(base + FSL_I2C_I2DR);
+		msgs->buf[i] = fsl_i2c_read_reg(i2c_fsl, FSL_I2C_I2DR);
 
 		dev_dbg(&adapter->dev, "<%s> read byte: B%d=0x%02X\n",
 			__func__, i, msgs->buf[i]);
@@ -497,7 +502,6 @@ static int i2c_fsl_xfer(struct i2c_adapter *adapter,
 			struct i2c_msg *msgs, int num)
 {
 	struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
-	void __iomem *base = i2c_fsl->base;
 	unsigned int i, temp;
 	int result;
 
@@ -514,9 +518,9 @@ static int i2c_fsl_xfer(struct i2c_adapter *adapter,
 	/* read/write data */
 	for (i = 0; i < num; i++) {
 		if (i && !(msgs[i].flags & I2C_M_DATA_ONLY)) {
-			temp = readb(base + FSL_I2C_I2CR);
+			temp = fsl_i2c_read_reg(i2c_fsl, FSL_I2C_I2CR);
 			temp |= I2CR_RSTA;
-			writeb(temp, base + FSL_I2C_I2CR);
+			fsl_i2c_write_reg(temp, fsl_i2c, FSL_I2C_I2CR);
 
 			result = i2c_fsl_bus_busy(adapter, 1);
 			if (result)
@@ -623,8 +627,8 @@ static int __init i2c_fsl_probe(struct device_d *pdev)
 		i2c_fsl_set_clk(i2c_fsl, FSL_I2C_BIT_RATE);
 
 	/* Set up chip registers to defaults */
-	writeb(0, i2c_fsl->base + FSL_I2C_I2CR);
-	writeb(0, i2c_fsl->base + FSL_I2C_I2SR);
+	fsl_i2c_write_reg(0, i2c_fsl, FSL_I2C_I2CR);
+	fsl_i2c_write_reg(0, i2c_fsl, FSL_I2C_I2SR);
 
 	/* Add I2C adapter */
 	ret = i2c_add_numbered_adapter(&i2c_fsl->adapter);
-- 
2.5.5


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  parent reply	other threads:[~2016-11-09 16:15 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-09 16:13 [PATCH v2 00/28] Vybrid support in Barebox Andrey Smirnov
2016-11-09 16:13 ` [PATCH v2 01/28] i.MX: Add primitive functions for VF610 family Andrey Smirnov
2016-11-09 16:13 ` [PATCH v2 02/28] i.MX: Add register definitions for VF610 SoC Andrey Smirnov
2016-11-09 16:13 ` [PATCH v2 03/28] i.MX: Add DEBUG_LL hooks for VF610 Andrey Smirnov
2016-11-09 16:13 ` [PATCH v2 04/28] i.MX: scripts: Add "vf610" soc to imx-image Andrey Smirnov
2016-11-09 16:13 ` [PATCH v2 05/28] i.MX: Add support for VF610 Tower board Andrey Smirnov
2016-11-09 16:13 ` [PATCH v2 06/28] pinctrl: Add provisions to control GPIO pin direction Andrey Smirnov
2016-11-09 16:13 ` [PATCH v2 07/28] i.MX: Add pinctrl driver for VF610 Andrey Smirnov
2016-11-09 16:13 ` [PATCH v2 08/28] clk: Port clock dependency resolution code Andrey Smirnov
2016-11-09 16:13 ` [PATCH v2 09/28] clk: Port of_clk_set_defaults() Andrey Smirnov
2016-11-15  7:53   ` Sascha Hauer
2016-11-09 16:13 ` [PATCH v2 10/28] i.MX: Move clk code from 'mach-imx' to 'drivers' Andrey Smirnov
2016-11-09 16:13 ` [PATCH v2 11/28] i.MX: clk: Port imx_clk_gate2_cgr() Andrey Smirnov
2016-11-09 16:14 ` [PATCH v2 12/28] i.MX: clk: Add IMX_PLLV3_USB_VF610 support Andrey Smirnov
2016-11-09 16:14 ` [PATCH v2 13/28] i.MX: clk: Port imx_check_clocks() Andrey Smirnov
2016-11-09 16:14 ` [PATCH v2 14/28] i.MX: clk: Port imx_clk_mux_flags from Linux Andrey Smirnov
2016-11-09 16:14 ` [PATCH v2 15/28] i.MX: Add VF610 clock tree initialization code Andrey Smirnov
2016-11-09 16:14 ` [PATCH v2 16/28] vf610: Give enet_osc explicit "enet_ext" name Andrey Smirnov
2016-11-09 16:14 ` [PATCH v2 17/28] i.MX: Add 'lpuart' serial driver Andrey Smirnov
2016-11-09 16:14 ` Andrey Smirnov [this message]
2016-11-09 16:14 ` [PATCH v2 19/28] i.MX: i2c: Add Vybrid support Andrey Smirnov
2016-11-09 16:14 ` [PATCH v2 20/28] i.MX: esdhc: Do not rely on CPU type for quirks Andrey Smirnov
2016-11-09 16:14 ` [PATCH v2 21/28] i.MX: esdhc: Request "per" clock explicitly Andrey Smirnov
2016-11-09 16:14 ` [PATCH v2 22/28] i.MX: Kconfig: Enable OCOTP on Vybrid Andrey Smirnov
2016-11-09 16:14 ` [PATCH v2 23/28] i.MX: ocotp: Remove unused #define Andrey Smirnov
2016-11-09 16:14 ` [PATCH v2 24/28] i.MX: ocotp: Account for shadow memory gaps Andrey Smirnov
2016-11-09 16:14 ` [PATCH v2 25/28] i.MX: ocotp: Add Vybrid support Andrey Smirnov
2016-11-09 16:14 ` [PATCH v2 26/28] i.MX: fec: Enable all clocks specified for FEC Andrey Smirnov
2016-11-09 16:14 ` [PATCH v2 27/28] i.MX: fec: Add support for Vybrid variant Andrey Smirnov
2016-11-09 16:14 ` [PATCH v2 28/28] gpio: Add GPIO driver for Vybrid Andrey Smirnov
2016-11-11  8:21 ` [PATCH v2 00/28] Vybrid support in Barebox Sascha Hauer

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