* Information regarding iMX6 QuadPlus and iMX6 DualLite @ 2017-03-23 15:04 gianluca 2017-03-23 15:15 ` Lucas Stach 0 siblings, 1 reply; 6+ messages in thread From: gianluca @ 2017-03-23 15:04 UTC (permalink / raw) To: Sascha Hauer; +Cc: barebox Hello, I was looking around to have a common Barebox binary to bootup two boards based on iMX6 SoC. The PCB are at 99.8% the same. PCB#0 has iMX6QP and a VDDCore of 1.38V (LDO enabled) PCB#1 has iMX6DL and a VDDCore of 1.32V (LDO enabled) I was wondering how other boards (like Nitrogen6x) does for booting. As soon as my boards have the same DDR Memory routing and types, the oly thing I can think is the different memory address space for DDR controller. In fact, the Nitrogen6x boards, differs from the #include of the ddr controller (one is for dual-lite, the other for quad). But I do not found any switch between choosing one Soc or another. Where is done the startup entry? And the maximum clock speed??? Those SoC has different clock maximum speed, so I think someone has to tell it to run @800 Mhz or @1Ghz. Is this true? Are those stuff the only things that matters? Regards, -- Eurek s.r.l. | Electronic Engineering | http://www.eurek.it via Celletta 8/B, 40026 Imola, Italy | Phone: +39-(0)542-609120 p.iva 00690621206 - c.f. 04020030377 | Fax: +39-(0)542-609212 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Information regarding iMX6 QuadPlus and iMX6 DualLite 2017-03-23 15:04 Information regarding iMX6 QuadPlus and iMX6 DualLite gianluca @ 2017-03-23 15:15 ` Lucas Stach 2017-03-23 16:56 ` gianluca 2017-03-23 18:47 ` Sascha Hauer 0 siblings, 2 replies; 6+ messages in thread From: Lucas Stach @ 2017-03-23 15:15 UTC (permalink / raw) To: gianluca; +Cc: barebox Hi, Am Donnerstag, den 23.03.2017, 16:04 +0100 schrieb gianluca: > Hello, > I was looking around to have a common Barebox binary to bootup two > boards based on iMX6 SoC. > > The PCB are at 99.8% the same. > PCB#0 has iMX6QP and a VDDCore of 1.38V (LDO enabled) > PCB#1 has iMX6DL and a VDDCore of 1.32V (LDO enabled) > > I was wondering how other boards (like Nitrogen6x) does for booting. > > As soon as my boards have the same DDR Memory routing and types, the oly > thing I can think is the different memory address space for DDR controller. Even if the external memory is the same, you need 2 different DRAM setups. Quad and DualLite differ in IOMUX setup and maximum DRAM frequency, the QuadPlus needs additional setup for the NoC. > In fact, the Nitrogen6x boards, differs from the #include of the ddr > controller (one is for dual-lite, the other for quad). For the Nitrogen boards we just build multiple images for different SoC/DRAM configurations. This is the easiest and most reliable way of dealing with this issue. > > But I do not found any switch between choosing one Soc or another. > Where is done the startup entry? If you want a single binary, you need build a 2 stage barebox. First stage needs to be loaded into SRAM, then you can look at which board you are running and do the specific DRAM setup. Then you can load the bigger 2nd stage into DRAM, where you again need to look at the board you are running at and select the correct devicetree for barebox to use. > And the maximum clock speed??? Those SoC has different clock maximum > speed, so I think someone has to tell it to run @800 Mhz or @1Ghz. Is > this true? Clock speeds are defined by the CPU OPPs in the devicetree and the fuse settings of the SoC. Regards, Lucas _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Information regarding iMX6 QuadPlus and iMX6 DualLite 2017-03-23 15:15 ` Lucas Stach @ 2017-03-23 16:56 ` gianluca 2017-03-23 16:59 ` Lucas Stach 2017-03-23 18:47 ` Sascha Hauer 1 sibling, 1 reply; 6+ messages in thread From: gianluca @ 2017-03-23 16:56 UTC (permalink / raw) To: Lucas Stach; +Cc: barebox On 03/23/2017 04:15 PM, Lucas Stach wrote: > Hi, > > Am Donnerstag, den 23.03.2017, 16:04 +0100 schrieb gianluca: >> Hello, >> I was looking around to have a common Barebox binary to bootup two >> boards based on iMX6 SoC. >> >> The PCB are at 99.8% the same. >> PCB#0 has iMX6QP and a VDDCore of 1.38V (LDO enabled) >> PCB#1 has iMX6DL and a VDDCore of 1.32V (LDO enabled) >> >> I was wondering how other boards (like Nitrogen6x) does for booting. >> >> As soon as my boards have the same DDR Memory routing and types, the oly >> thing I can think is the different memory address space for DDR controller. > > Even if the external memory is the same, you need 2 different DRAM > setups. Quad and DualLite differ in IOMUX setup and maximum DRAM > frequency, the QuadPlus needs additional setup for the NoC. > So you need two DRAM setup only? And no problem for NoC. Our boards will have only QuadPlus and DualLite. >> In fact, the Nitrogen6x boards, differs from the #include of the ddr >> controller (one is for dual-lite, the other for quad). > > For the Nitrogen boards we just build multiple images for different > SoC/DRAM configurations. This is the easiest and most reliable way of > dealing with this issue. > So you will have different device-tree .dts file? One for each SoC even if the pinout are the same? In this way, having two DRAM Setups, two IOMUX setup, different DRAM Frequencies and two device-tree blobs, this leads me to a conclusion: -- They are TWO DIFFERENT BOARDS (even the PCB and the pinouts are the same) Luckly the Linux kernel is the same, and even the rootfilesystem too. >> >> But I do not found any switch between choosing one Soc or another. >> Where is done the startup entry? > > If you want a single binary, you need build a 2 stage barebox. First > stage needs to be loaded into SRAM, then you can look at which board you > are running and do the specific DRAM setup. Then you can load the bigger > 2nd stage into DRAM, where you again need to look at the board you are > running at and select the correct devicetree for barebox to use. > >> And the maximum clock speed??? Those SoC has different clock maximum >> speed, so I think someone has to tell it to run @800 Mhz or @1Ghz. Is >> this true? > > Clock speeds are defined by the CPU OPPs in the devicetree and the fuse > settings of the SoC. > Ok, I will check that. Thank you for now, -- Eurek s.r.l. | Electronic Engineering | http://www.eurek.it via Celletta 8/B, 40026 Imola, Italy | Phone: +39-(0)542-609120 p.iva 00690621206 - c.f. 04020030377 | Fax: +39-(0)542-609212 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Information regarding iMX6 QuadPlus and iMX6 DualLite 2017-03-23 16:56 ` gianluca @ 2017-03-23 16:59 ` Lucas Stach 2017-03-23 17:03 ` gianluca 0 siblings, 1 reply; 6+ messages in thread From: Lucas Stach @ 2017-03-23 16:59 UTC (permalink / raw) To: gianluca; +Cc: barebox Am Donnerstag, den 23.03.2017, 17:56 +0100 schrieb gianluca: > On 03/23/2017 04:15 PM, Lucas Stach wrote: > > Hi, > > > > Am Donnerstag, den 23.03.2017, 16:04 +0100 schrieb gianluca: > >> Hello, > >> I was looking around to have a common Barebox binary to bootup two > >> boards based on iMX6 SoC. > >> > >> The PCB are at 99.8% the same. > >> PCB#0 has iMX6QP and a VDDCore of 1.38V (LDO enabled) > >> PCB#1 has iMX6DL and a VDDCore of 1.32V (LDO enabled) > >> > >> I was wondering how other boards (like Nitrogen6x) does for booting. > >> > >> As soon as my boards have the same DDR Memory routing and types, the oly > >> thing I can think is the different memory address space for DDR controller. > > > > Even if the external memory is the same, you need 2 different DRAM > > setups. Quad and DualLite differ in IOMUX setup and maximum DRAM > > frequency, the QuadPlus needs additional setup for the NoC. > > > > So you need two DRAM setup only? And no problem for NoC. Our boards will > have only QuadPlus and DualLite. Do you mean the regular Quad model? The QuadPlus has the NoC. > > >> In fact, the Nitrogen6x boards, differs from the #include of the ddr > >> controller (one is for dual-lite, the other for quad). > > > > For the Nitrogen boards we just build multiple images for different > > SoC/DRAM configurations. This is the easiest and most reliable way of > > dealing with this issue. > > > > So you will have different device-tree .dts file? One for each SoC even > if the pinout are the same? > > In this way, having two DRAM Setups, two IOMUX setup, different DRAM > Frequencies and two device-tree blobs, this leads me to a conclusion: > > -- They are TWO DIFFERENT BOARDS (even the PCB and the pinouts are the same) Well, welcome to the i.MX6 world. :) _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Information regarding iMX6 QuadPlus and iMX6 DualLite 2017-03-23 16:59 ` Lucas Stach @ 2017-03-23 17:03 ` gianluca 0 siblings, 0 replies; 6+ messages in thread From: gianluca @ 2017-03-23 17:03 UTC (permalink / raw) To: Lucas Stach; +Cc: barebox On 03/23/2017 05:59 PM, Lucas Stach wrote: > Am Donnerstag, den 23.03.2017, 17:56 +0100 schrieb gianluca: >> On 03/23/2017 04:15 PM, Lucas Stach wrote: >>> Hi, >>> >>> Am Donnerstag, den 23.03.2017, 16:04 +0100 schrieb gianluca: >>>> Hello, >>>> I was looking around to have a common Barebox binary to bootup two >>>> boards based on iMX6 SoC. >>>> >>>> The PCB are at 99.8% the same. >>>> PCB#0 has iMX6QP and a VDDCore of 1.38V (LDO enabled) >>>> PCB#1 has iMX6DL and a VDDCore of 1.32V (LDO enabled) >>>> >>>> I was wondering how other boards (like Nitrogen6x) does for booting. >>>> >>>> As soon as my boards have the same DDR Memory routing and types, the oly >>>> thing I can think is the different memory address space for DDR controller. >>> >>> Even if the external memory is the same, you need 2 different DRAM >>> setups. Quad and DualLite differ in IOMUX setup and maximum DRAM >>> frequency, the QuadPlus needs additional setup for the NoC. >>> >> >> So you need two DRAM setup only? And no problem for NoC. Our boards will >> have only QuadPlus and DualLite. > > Do you mean the regular Quad model? The QuadPlus has the NoC. > Nope. We will have only the QuadPlus model, so hence the NoC. >> >>>> In fact, the Nitrogen6x boards, differs from the #include of the ddr >>>> controller (one is for dual-lite, the other for quad). >>> >>> For the Nitrogen boards we just build multiple images for different >>> SoC/DRAM configurations. This is the easiest and most reliable way of >>> dealing with this issue. >>> >> >> So you will have different device-tree .dts file? One for each SoC even >> if the pinout are the same? >> >> In this way, having two DRAM Setups, two IOMUX setup, different DRAM >> Frequencies and two device-tree blobs, this leads me to a conclusion: >> >> -- They are TWO DIFFERENT BOARDS (even the PCB and the pinouts are the same) > > Well, welcome to the i.MX6 world. :) > > Thank you for this hint. WTF > > -- Eurek s.r.l. | Electronic Engineering | http://www.eurek.it via Celletta 8/B, 40026 Imola, Italy | Phone: +39-(0)542-609120 p.iva 00690621206 - c.f. 04020030377 | Fax: +39-(0)542-609212 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Information regarding iMX6 QuadPlus and iMX6 DualLite 2017-03-23 15:15 ` Lucas Stach 2017-03-23 16:56 ` gianluca @ 2017-03-23 18:47 ` Sascha Hauer 1 sibling, 0 replies; 6+ messages in thread From: Sascha Hauer @ 2017-03-23 18:47 UTC (permalink / raw) To: Lucas Stach; +Cc: barebox, gianluca Hi, On Thu, Mar 23, 2017 at 04:15:53PM +0100, Lucas Stach wrote: > Hi, > > Am Donnerstag, den 23.03.2017, 16:04 +0100 schrieb gianluca: > > But I do not found any switch between choosing one Soc or another. > > Where is done the startup entry? > > If you want a single binary, you need build a 2 stage barebox. First > stage needs to be loaded into SRAM, then you can look at which board you > are running and do the specific DRAM setup. Then you can load the bigger > 2nd stage into DRAM, where you again need to look at the board you are > running at and select the correct devicetree for barebox to use. For an example how this can be done look at the wandboard support: arch/arm/boards/technexion-wandboard/lowlevel.c The wandboard doesn't have QuadPLus support, but the principle is the same. It comes with different device trees and DRAMs. Both are selected depending on the SoC type. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
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