[PATCH 1/3] ARM: i.MX: Add i.MX6 ULL support

[PATCH 1/3] ARM: i.MX: Add i.MX6 ULL support

[Stefan Riedmueller]

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
 arch/arm/mach-imx/imx.c               | 2 ++
 arch/arm/mach-imx/imx6.c              | 3 +++
 arch/arm/mach-imx/include/mach/imx6.h | 2 ++
 3 files changed, 7 insertions(+)

diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c
index 1990739..9400105 100644
--- a/arch/arm/mach-imx/imx.c
+++ b/arch/arm/mach-imx/imx.c
@@ -67,6 +67,8 @@ static int imx_soc_from_dt(void)
 		return IMX_CPU_IMX6;
 	if (of_machine_is_compatible("fsl,imx6ul"))
 		return IMX_CPU_IMX6;
+	if (of_machine_is_compatible("fsl,imx6ull"))
+		return IMX_CPU_IMX6;
 	if (of_machine_is_compatible("fsl,imx7s"))
 		return IMX_CPU_IMX7;
 	if (of_machine_is_compatible("fsl,imx7d"))
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 44a8dbe..7b3fc1d 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -160,6 +160,9 @@ int imx6_init(void)
 	case IMX6_CPUTYPE_IMX6UL:
 		cputypestr = "i.MX6 UltraLite";
 		break;
+	case IMX6_CPUTYPE_IMX6ULL:
+		cputypestr = "i.MX6 ULL";
+		break;
 	default:
 		cputypestr = "unknown i.MX6";
 		break;
diff --git a/arch/arm/mach-imx/include/mach/imx6.h b/arch/arm/mach-imx/include/mach/imx6.h
index 327676b..6ad5343 100644
--- a/arch/arm/mach-imx/include/mach/imx6.h
+++ b/arch/arm/mach-imx/include/mach/imx6.h
@@ -18,6 +18,7 @@ void imx6_init_lowlevel(void);
 #define IMX6_CPUTYPE_IMX6D	0x263
 #define IMX6_CPUTYPE_IMX6Q	0x463
 #define IMX6_CPUTYPE_IMX6UL	0x164
+#define IMX6_CPUTYPE_IMX6ULL	0x165
 
 #define SCU_CONFIG              0x04
 
@@ -82,6 +83,7 @@ DEFINE_MX6_CPU_TYPE(mx6d, IMX6_CPUTYPE_IMX6D);
 DEFINE_MX6_CPU_TYPE(mx6sx, IMX6_CPUTYPE_IMX6SX);
 DEFINE_MX6_CPU_TYPE(mx6sl, IMX6_CPUTYPE_IMX6SL);
 DEFINE_MX6_CPU_TYPE(mx6ul, IMX6_CPUTYPE_IMX6UL);
+DEFINE_MX6_CPU_TYPE(mx6ull, IMX6_CPUTYPE_IMX6ULL);
 
 static inline int __imx6_cpu_revision(void)
 {
-- 
1.9.1


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[PATCH 2/3] ARM: i.MX6ul: Add Clock support for i.MX6ull

[Stefan Riedmueller]

From linux-4.10 clock support, only skipped some unnecessary clocks

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
 drivers/clk/imx/clk-imx6ul.c | 73 +++++++++++++++++++++++++++++++++++++-------
 1 file changed, 62 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index f28660d..b0a6bb0 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -66,10 +66,24 @@ static const char *perclk_sels[] = { "ipg", "osc", };
 static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
 static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
 static const char *sim_sels[] = { "sim_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
+/* epdc_pre_sels, epdc_sels, esai_sels only exists on i.MX6ULL */
+static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
+static const char *esai_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
+static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
 
 static struct clk *clks[IMX6UL_CLK_END];
 static struct clk_onecell_data clk_data;
 
+static inline int clk_on_imx6ul(void)
+{
+	return of_machine_is_compatible("fsl,imx6ul");
+}
+
+static inline int clk_on_imx6ull(void)
+{
+	return of_machine_is_compatible("fsl,imx6ull");
+}
+
 static int const clks_init_on[] __initconst = {
 	IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2, IMX6UL_CLK_AIPSTZ3,
 	IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM,
@@ -206,12 +220,19 @@ static int imx6_ccm_probe(struct device_d *dev)
 	clks[IMX6UL_CLK_QSPI1_SEL]	  = imx_clk_mux("qspi1_sel",    base + 0x1c, 7,  3, qspi1_sels, ARRAY_SIZE(qspi1_sels));
 	clks[IMX6UL_CLK_PERCLK_SEL]	  = imx_clk_mux("perclk_sel",	base + 0x1c, 6,  1, perclk_sels, ARRAY_SIZE(perclk_sels));
 	clks[IMX6UL_CLK_CAN_SEL]	  = imx_clk_mux("can_sel",	base + 0x20, 8,  2, can_sels, ARRAY_SIZE(can_sels));
+	if (clk_on_imx6ull())
+		clks[IMX6ULL_CLK_ESAI_SEL]        = imx_clk_mux("esai_sel",     base + 0x20, 19, 2, esai_sels, ARRAY_SIZE(esai_sels));
 	clks[IMX6UL_CLK_UART_SEL]	  = imx_clk_mux("uart_sel",	base + 0x24, 6,  1, uart_sels, ARRAY_SIZE(uart_sels));
 	clks[IMX6UL_CLK_ENFC_SEL]	  = imx_clk_mux("enfc_sel",	base + 0x2c, 15, 3, enfc_sels, ARRAY_SIZE(enfc_sels));
 	clks[IMX6UL_CLK_LDB_DI0_SEL]	  = imx_clk_mux("ldb_di0_sel",	base + 0x2c, 9,  3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels));
 	clks[IMX6UL_CLK_SPDIF_SEL]	  = imx_clk_mux("spdif_sel",	base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels));
-	clks[IMX6UL_CLK_SIM_PRE_SEL]	  = imx_clk_mux("sim_pre_sel",	base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels));
-	clks[IMX6UL_CLK_SIM_SEL]	  = imx_clk_mux("sim_sel",	base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels));
+	if (clk_on_imx6ul()) {
+		clks[IMX6UL_CLK_SIM_PRE_SEL]      = imx_clk_mux("sim_pre_sel",  base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels));
+		clks[IMX6UL_CLK_SIM_SEL]          = imx_clk_mux("sim_sel",      base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels));
+	} else if (clk_on_imx6ull()) {
+		clks[IMX6ULL_CLK_EPDC_PRE_SEL]    = imx_clk_mux("epdc_pre_sel", base + 0x34, 15, 3, epdc_pre_sels, ARRAY_SIZE(epdc_pre_sels));
+		clks[IMX6ULL_CLK_EPDC_SEL]        = imx_clk_mux("epdc_sel",     base + 0x34, 9, 3, epdc_sels, ARRAY_SIZE(epdc_sels));
+	}
 	clks[IMX6UL_CLK_ECSPI_SEL]	  = imx_clk_mux("ecspi_sel",	base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
 	clks[IMX6UL_CLK_LCDIF_PRE_SEL]	  = imx_clk_mux("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels));
 	clks[IMX6UL_CLK_LCDIF_SEL]	  = imx_clk_mux("lcdif_sel",	base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels));
@@ -244,6 +265,10 @@ static int imx6_ccm_probe(struct device_d *dev)
 	clks[IMX6UL_CLK_SAI3_PODF]	= imx_clk_divider("sai3_podf",	   "sai3_pred",		base + 0x28, 16, 6);
 	clks[IMX6UL_CLK_SAI1_PRED]	= imx_clk_divider("sai1_pred",	   "sai1_sel",		base + 0x28, 6,	 3);
 	clks[IMX6UL_CLK_SAI1_PODF]	= imx_clk_divider("sai1_podf",	   "sai1_pred",		base + 0x28, 0,	 6);
+	if (clk_on_imx6ull()) {
+		clks[IMX6ULL_CLK_ESAI_PRED]     = imx_clk_divider("esai_pred",     "esai_sel",          base + 0x28, 9,  3);
+		clks[IMX6ULL_CLK_ESAI_PODF]     = imx_clk_divider("esai_podf",     "esai_pred",         base + 0x28, 25, 3);
+	}
 	clks[IMX6UL_CLK_ENFC_PRED]	= imx_clk_divider("enfc_pred",	   "enfc_sel",		base + 0x2c, 18, 3);
 	clks[IMX6UL_CLK_ENFC_PODF]	= imx_clk_divider("enfc_podf",	   "enfc_pred",		base + 0x2c, 21, 6);
 	clks[IMX6UL_CLK_SAI2_PRED]	= imx_clk_divider("sai2_pred",	   "sai2_sel",		base + 0x2c, 6,	 3);
@@ -264,9 +289,15 @@ static int imx6_ccm_probe(struct device_d *dev)
 	clks[IMX6UL_CLK_AIPSTZ1]	= imx_clk_gate2("aips_tz1",	"ahb",		base + 0x68,	0);
 	clks[IMX6UL_CLK_AIPSTZ2]	= imx_clk_gate2("aips_tz2",	"ahb",		base + 0x68,	2);
 	clks[IMX6UL_CLK_APBHDMA]	= imx_clk_gate2("apbh_dma",	"bch_podf",	base + 0x68,	4);
-	clks[IMX6UL_CLK_CAAM_MEM]	= imx_clk_gate2("caam_mem",	"ahb",		base + 0x68,	8);
-	clks[IMX6UL_CLK_CAAM_ACLK]	= imx_clk_gate2("caam_aclk",	"ahb",		base + 0x68,	10);
-	clks[IMX6UL_CLK_CAAM_IPG]	= imx_clk_gate2("caam_ipg",	"ipg",		base + 0x68,	12);
+	if (clk_on_imx6ul()) {
+		clks[IMX6UL_CLK_CAAM_MEM]       = imx_clk_gate2("caam_mem",     "ahb",          base + 0x68,    8);
+		clks[IMX6UL_CLK_CAAM_ACLK]      = imx_clk_gate2("caam_aclk",    "ahb",          base + 0x68,    10);
+		clks[IMX6UL_CLK_CAAM_IPG]       = imx_clk_gate2("caam_ipg",     "ipg",          base + 0x68,    12);
+	} else if (clk_on_imx6ull()) {
+		clks[IMX6ULL_CLK_DCP_CLK]       = imx_clk_gate2("dcp",          "ahb",          base + 0x68,    10);
+		clks[IMX6UL_CLK_ENET]           = imx_clk_gate2("enet",         "ipg",          base + 0x68,    12);
+		clks[IMX6UL_CLK_ENET_AHB]       = imx_clk_gate2("enet_ahb",     "ahb",          base + 0x68,    12);
+	}
 	clks[IMX6UL_CLK_CAN1_IPG]	= imx_clk_gate2("can1_ipg",	"ipg",		base + 0x68,	14);
 	clks[IMX6UL_CLK_CAN1_SERIAL]	= imx_clk_gate2("can1_serial",	"can_podf",	base + 0x68,	16);
 	clks[IMX6UL_CLK_CAN2_IPG]	= imx_clk_gate2("can2_ipg",	"ipg",		base + 0x68,	18);
@@ -275,7 +306,10 @@ static int imx6_ccm_probe(struct device_d *dev)
 	clks[IMX6UL_CLK_GPT2_SERIAL]	= imx_clk_gate2("gpt2_serial",	"perclk",	base + 0x68,	26);
 	clks[IMX6UL_CLK_UART2_IPG]	= imx_clk_gate2("uart2_ipg",	"ipg",		base + 0x68,	28);
 	clks[IMX6UL_CLK_UART2_SERIAL]	= imx_clk_gate2("uart2_serial",	"uart_podf",	base + 0x68,	28);
-	clks[IMX6UL_CLK_AIPSTZ3]	= imx_clk_gate2("aips_tz3",	"ahb",		base + 0x68,	30);
+	if (clk_on_imx6ul())
+		clks[IMX6UL_CLK_AIPSTZ3]        = imx_clk_gate2("aips_tz3",     "ahb",          base + 0x68,    30);
+	else if (clk_on_imx6ull())
+		clks[IMX6UL_CLK_AIPSTZ3]        = imx_clk_gate2("aips_tz3",     "ahb",           base + 0x80,   18);
 
 	/* CCGR1 */
 	clks[IMX6UL_CLK_ECSPI1]		= imx_clk_gate2("ecspi1",	"ecspi_podf",	base + 0x6c,	0);
@@ -294,6 +328,11 @@ static int imx6_ccm_probe(struct device_d *dev)
 	clks[IMX6UL_CLK_UART4_SERIAL]	= imx_clk_gate2("uart4_serail",	"uart_podf",	base + 0x6c,	24);
 
 	/* CCGR2 */
+	if (clk_on_imx6ull()) {
+		clks[IMX6ULL_CLK_ESAI_EXTAL]	= imx_clk_gate2("esai_extal",	"esai_podf",	base + 0x70,	0);
+		clks[IMX6ULL_CLK_ESAI_IPG]	= imx_clk_gate2("esai_ipg",	"ahb",		base + 0x70,	0);
+		clks[IMX6ULL_CLK_ESAI_MEM]	= imx_clk_gate2("esai_mem",	"ahb",		base + 0x70,	0);
+	}
 	clks[IMX6UL_CLK_CSI]		= imx_clk_gate2("csi",		"csi_podf",		base + 0x70,	2);
 	clks[IMX6UL_CLK_I2C1]		= imx_clk_gate2("i2c1",		"perclk",	base + 0x70,	6);
 	clks[IMX6UL_CLK_I2C2]		= imx_clk_gate2("i2c2",		"perclk",	base + 0x70,	8);
@@ -306,8 +345,13 @@ static int imx6_ccm_probe(struct device_d *dev)
 	/* CCGR3 */
 	clks[IMX6UL_CLK_UART5_IPG]	= imx_clk_gate2("uart5_ipg",	"ipg",		base + 0x74,	2);
 	clks[IMX6UL_CLK_UART5_SERIAL]	= imx_clk_gate2("uart5_serial",	"uart_podf",	base + 0x74,	2);
-	clks[IMX6UL_CLK_ENET]		= imx_clk_gate2("enet",		"ipg",		base + 0x74,	4);
-	clks[IMX6UL_CLK_ENET_AHB]	= imx_clk_gate2("enet_ahb",	"ahb",		base + 0x74,	4);
+	if (clk_on_imx6ul()) {
+		clks[IMX6UL_CLK_ENET]           = imx_clk_gate2("enet",         "ipg",          base + 0x74,    4);
+		clks[IMX6UL_CLK_ENET_AHB]       = imx_clk_gate2("enet_ahb",     "ahb",          base + 0x74,    4);
+	} else if (clk_on_imx6ull()) {
+		clks[IMX6ULL_CLK_EPDC_ACLK]     = imx_clk_gate2("epdc_aclk",    "axi",          base + 0x74,    4);
+		clks[IMX6ULL_CLK_EPDC_PIX]      = imx_clk_gate2("epdc_pix",     "epdc_podf",    base + 0x74,    4);
+	}
 	clks[IMX6UL_CLK_UART6_IPG]	= imx_clk_gate2("uart6_ipg",	"ipg",		base + 0x74,	6);
 	clks[IMX6UL_CLK_UART6_SERIAL]	= imx_clk_gate2("uart6_serial",	"uart_podf",	base + 0x74,	6);
 	clks[IMX6UL_CLK_LCDIF_PIX]	= imx_clk_gate2("lcdif_pix",	"lcdif_podf",	base + 0x74,	10);
@@ -343,8 +387,10 @@ static int imx6_ccm_probe(struct device_d *dev)
 	clks[IMX6UL_CLK_USBOH3]		= imx_clk_gate2("usboh3",	"ipg",		 base + 0x80,	0);
 	clks[IMX6UL_CLK_USDHC1]		= imx_clk_gate2("usdhc1",	"usdhc1_podf",	 base + 0x80,	2);
 	clks[IMX6UL_CLK_USDHC2]		= imx_clk_gate2("usdhc2",	"usdhc2_podf",	 base + 0x80,	4);
-	clks[IMX6UL_CLK_SIM1]		= imx_clk_gate2("sim1",		"sim_sel",	 base + 0x80,	6);
-	clks[IMX6UL_CLK_SIM2]		= imx_clk_gate2("sim2",		"sim_sel",	 base + 0x80,	8);
+	if (clk_on_imx6ul()) {
+		clks[IMX6UL_CLK_SIM1]           = imx_clk_gate2("sim1",         "sim_sel",       base + 0x80,   6);
+		clks[IMX6UL_CLK_SIM2]           = imx_clk_gate2("sim2",         "sim_sel",       base + 0x80,   8);
+	}
 	clks[IMX6UL_CLK_EIM]		= imx_clk_gate2("eim",		"eim_slow_podf", base + 0x80,	10);
 	clks[IMX6UL_CLK_PWM8]		= imx_clk_gate2("pwm8",		"perclk",	 base + 0x80,	16);
 	clks[IMX6UL_CLK_UART8_IPG]	= imx_clk_gate2("uart8_ipg",	"ipg",		 base + 0x80,	14);
@@ -397,7 +443,12 @@ static int imx6_ccm_probe(struct device_d *dev)
 	}
 
 	clk_set_parent(clks[IMX6UL_CLK_CAN_SEL], clks[IMX6UL_CLK_PLL3_60M]);
-	clk_set_parent(clks[IMX6UL_CLK_SIM_PRE_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]);
+	if (clk_on_imx6ul())
+		clk_set_parent(clks[IMX6UL_CLK_SIM_PRE_SEL],
+				clks[IMX6UL_CLK_PLL3_USB_OTG]);
+	else if (clk_on_imx6ull())
+		clk_set_parent(clks[IMX6ULL_CLK_EPDC_PRE_SEL],
+				clks[IMX6UL_CLK_PLL3_PFD2]);
 
 	clk_set_parent(clks[IMX6UL_CLK_ENFC_SEL], clks[IMX6UL_CLK_PLL2_PFD2]);
 
-- 
1.9.1


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Re: [PATCH 2/3] ARM: i.MX6ul: Add Clock support for i.MX6ull

[Sascha Hauer]

On Thu, May 11, 2017 at 11:09:27AM +0200, Stefan Riedmueller wrote:
> From linux-4.10 clock support, only skipped some unnecessary clocks
> 
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
> ---
>  drivers/clk/imx/clk-imx6ul.c | 73 +++++++++++++++++++++++++++++++++++++-------
>  1 file changed, 62 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
> index f28660d..b0a6bb0 100644
> --- a/drivers/clk/imx/clk-imx6ul.c
> +++ b/drivers/clk/imx/clk-imx6ul.c
> @@ -66,10 +66,24 @@ static const char *perclk_sels[] = { "ipg", "osc", };
>  static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
>  static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
>  static const char *sim_sels[] = { "sim_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
> +/* epdc_pre_sels, epdc_sels, esai_sels only exists on i.MX6ULL */
> +static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
> +static const char *esai_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
> +static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
>  
>  static struct clk *clks[IMX6UL_CLK_END];
>  static struct clk_onecell_data clk_data;
>  
> +static inline int clk_on_imx6ul(void)
> +{
> +	return of_machine_is_compatible("fsl,imx6ul");
> +}
> +
> +static inline int clk_on_imx6ull(void)
> +{
> +	return of_machine_is_compatible("fsl,imx6ull");
> +}

Can we use cpu_is_imx6ul(l) instead here? This would allow
us to compile away the code if we one of the two SoCs is
disabled in the config.

Sascha

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Antwort: Re: [PATCH 2/3] ARM: i.MX6ul: Add Clock support for i.MX6ull

[Stefan Riedmüller]

Sascha Hauer <s.hauer@pengutronix.de> wrote on 16/05/2017 07:47:39:

> Von: Sascha Hauer <s.hauer@pengutronix.de>
> An: Stefan Riedmueller <s.riedmueller@phytec.de>
> Kopie: barebox@lists.infradead.org
> Datum: 16/05/2017 07:47
> Betreff: Re: [PATCH 2/3] ARM: i.MX6ul: Add Clock support for i.MX6ull
> 
> On Thu, May 11, 2017 at 11:09:27AM +0200, Stefan Riedmueller wrote:
> > From linux-4.10 clock support, only skipped some unnecessary clocks
> > 
> > Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
> > ---
> >  drivers/clk/imx/clk-imx6ul.c | 73 +++++++++++++++++++++++++++++++
> ++++++-------
> >  1 file changed, 62 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/clk/imx/clk-imx6ul.c 
b/drivers/clk/imx/clk-imx6ul.c
> > index f28660d..b0a6bb0 100644
> > --- a/drivers/clk/imx/clk-imx6ul.c
> > +++ b/drivers/clk/imx/clk-imx6ul.c
> > @@ -66,10 +66,24 @@ static const char *perclk_sels[] = { "ipg", "osc", 
};
> >  static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", 
> "ipp_di1", "ldb_di0", "ldb_di1", };
> >  static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", 
> "pll3_120m", "pll3_pfd1_540m", };
> >  static const char *sim_sels[] = { "sim_podf", "ipp_di0", 
> "ipp_di1", "ldb_di0", "ldb_di1", };
> > +/* epdc_pre_sels, epdc_sels, esai_sels only exists on i.MX6ULL */
> > +static const char *epdc_pre_sels[] = { "pll2_bus", 
> "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", 
> "pll2_pfd2_396m", "pll3_pfd2_508m", };
> > +static const char *esai_sels[] = { "pll4_audio_div", 
> "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
> > +static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", 
> "ipp_di1", "ldb_di0", "ldb_di1", };
> > 
> >  static struct clk *clks[IMX6UL_CLK_END];
> >  static struct clk_onecell_data clk_data;
> > 
> > +static inline int clk_on_imx6ul(void)
> > +{
> > +   return of_machine_is_compatible("fsl,imx6ul");
> > +}
> > +
> > +static inline int clk_on_imx6ull(void)
> > +{
> > +   return of_machine_is_compatible("fsl,imx6ull");
> > +}
> 
> Can we use cpu_is_imx6ul(l) instead here? This would allow
> us to compile away the code if we one of the two SoCs is
> disabled in the config.
> 
> Sascha
> 

Hi Sascha, 

I tried to use cpu_is_mx6ul, but it seems it is not valid yet in the clk 
initcall. I found that __imx_cpu_type is set in a postcore initcall but 
would be already evaluated in cpu_is_mx6ul in the clk initcall which is a 
core initcall. So cpu_is_mx6ul would not evaluate correctly at this point. 


I also checked this with an i.MX6 DualLight where the cpu_is_mx6dl is 
implemented in the ccm init and there it evaluates wrong. In the ccm 
initcall it evaluates to 0 but later after the postcore initcalls it 
evaluates correctly to 1. So it seems the cpu_is_mx6ul/dl is not working 
correctly in the clk initcall. Did I get this correct or did I miss 
anything? 

Thanks for your help.
Stefan 

> -- 
> Pengutronix e.K.                           | |
> Industrial Linux Solutions                 | http://www.pengutronix.de/ 
|
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 
|


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Re: Antwort: Re: [PATCH 2/3] ARM: i.MX6ul: Add Clock support for i.MX6ull

[Sascha Hauer]

On Tue, May 16, 2017 at 04:46:00PM +0200, Stefan Riedmüller wrote:
> Sascha Hauer <s.hauer@pengutronix.de> wrote on 16/05/2017 07:47:39:
> 
> > Von: Sascha Hauer <s.hauer@pengutronix.de>
> > An: Stefan Riedmueller <s.riedmueller@phytec.de>
> > Kopie: barebox@lists.infradead.org
> > Datum: 16/05/2017 07:47
> > Betreff: Re: [PATCH 2/3] ARM: i.MX6ul: Add Clock support for i.MX6ull
> > 
> > On Thu, May 11, 2017 at 11:09:27AM +0200, Stefan Riedmueller wrote:
> > > From linux-4.10 clock support, only skipped some unnecessary clocks
> > > 
> > > Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
> > > ---
> > >  drivers/clk/imx/clk-imx6ul.c | 73 +++++++++++++++++++++++++++++++
> > ++++++-------
> > >  1 file changed, 62 insertions(+), 11 deletions(-)
> > > 
> > > diff --git a/drivers/clk/imx/clk-imx6ul.c 
> b/drivers/clk/imx/clk-imx6ul.c
> > > index f28660d..b0a6bb0 100644
> > > --- a/drivers/clk/imx/clk-imx6ul.c
> > > +++ b/drivers/clk/imx/clk-imx6ul.c
> > > @@ -66,10 +66,24 @@ static const char *perclk_sels[] = { "ipg", "osc", 
> };
> > >  static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", 
> > "ipp_di1", "ldb_di0", "ldb_di1", };
> > >  static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", 
> > "pll3_120m", "pll3_pfd1_540m", };
> > >  static const char *sim_sels[] = { "sim_podf", "ipp_di0", 
> > "ipp_di1", "ldb_di0", "ldb_di1", };
> > > +/* epdc_pre_sels, epdc_sels, esai_sels only exists on i.MX6ULL */
> > > +static const char *epdc_pre_sels[] = { "pll2_bus", 
> > "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", 
> > "pll2_pfd2_396m", "pll3_pfd2_508m", };
> > > +static const char *esai_sels[] = { "pll4_audio_div", 
> > "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
> > > +static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", 
> > "ipp_di1", "ldb_di0", "ldb_di1", };
> > > 
> > >  static struct clk *clks[IMX6UL_CLK_END];
> > >  static struct clk_onecell_data clk_data;
> > > 
> > > +static inline int clk_on_imx6ul(void)
> > > +{
> > > +   return of_machine_is_compatible("fsl,imx6ul");
> > > +}
> > > +
> > > +static inline int clk_on_imx6ull(void)
> > > +{
> > > +   return of_machine_is_compatible("fsl,imx6ull");
> > > +}
> > 
> > Can we use cpu_is_imx6ul(l) instead here? This would allow
> > us to compile away the code if we one of the two SoCs is
> > disabled in the config.
> > 
> > Sascha
> > 
> 
> Hi Sascha, 
> 
> I tried to use cpu_is_mx6ul, but it seems it is not valid yet in the clk 
> initcall. I found that __imx_cpu_type is set in a postcore initcall but 
> would be already evaluated in cpu_is_mx6ul in the clk initcall which is a 
> core initcall. So cpu_is_mx6ul would not evaluate correctly at this point. 
> 
> 
> I also checked this with an i.MX6 DualLight where the cpu_is_mx6dl is 
> implemented in the ccm init and there it evaluates wrong. In the ccm 
> initcall it evaluates to 0 but later after the postcore initcalls it 
> evaluates correctly to 1. So it seems the cpu_is_mx6ul/dl is not working 
> correctly in the clk initcall. Did I get this correct or did I miss 
> anything?

I looked at arch/arm/mach-imx/include/mach/imx6.h and saw that
__imx6_cpu_type() only reads from SoC registers, so assumed this would
work. What I didn't see is that the functions depend on cpu_is_mx6()
which goes down to __imx_cpu_type which you found out already.

Just like you I also found the cpu_is_mx6dl() in the i.MX6 clock driver,
but unlike you I just assumed that it works ;)

For now I think we can apply your original patch. I'll keep the issue on
my mental todo list.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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[PATCH 3/3] ARCH: ARM: Add support for phytec-phycore-imx6ull

[Stefan Riedmueller]

Created imx6ull devicetree to support Phytec phyCORE-i.MX6ULL.
 - 256 MB RAM
 - 128 MB NAND
 - 10/100 Mbit Ethernet

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
 .../flash-header-phytec-pcl063-256mb.imxcfg        |   9 ++
 arch/arm/boards/phytec-som-imx6/lowlevel.c         |   7 +-
 arch/arm/dts/Makefile                              |   3 +-
 arch/arm/dts/imx6ul-phytec-phycore-som.dts         | 146 +----------------
 arch/arm/dts/imx6ul-phytec-phycore-som.dtsi        | 178 +++++++++++++++++++++
 arch/arm/dts/imx6ull-phytec-phycore-som.dts        |  41 +++++
 images/Makefile.imx                                |   5 +
 7 files changed, 241 insertions(+), 148 deletions(-)
 create mode 100644 arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg
 create mode 100644 arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
 create mode 100644 arch/arm/dts/imx6ull-phytec-phycore-som.dts

diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg
new file mode 100644
index 0000000..4a827e4
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg
@@ -0,0 +1,9 @@
+
+#define SETUP_MDCFG0			\
+	wm 32 0x021B000C 0x676B52F3
+
+#define SETUP_MDASP_MDCTL		\
+	wm 32 0x021B0040 0x00000047;	\
+	wm 32 0x021B0000 0x83180000
+
+#include "flash-header-phytec-pcl063.h"
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 3ab88f4..07ac443 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -54,7 +54,8 @@ static void __noreturn start_imx6_phytec_common(uint32_t size,
 	int cpu_type = __imx6_cpu_type();
 	void *fdt;
 
-	if (cpu_type == IMX6_CPUTYPE_IMX6UL) {
+	if (cpu_type == IMX6_CPUTYPE_IMX6UL
+	    || cpu_type == IMX6_CPUTYPE_IMX6ULL) {
 		arm_cpu_lowlevel_init();
 		/* OCRAM Free Area is 0x00907000 to 0x00918000 (68KB) */
 		arm_setup_stack(0x00910000 - 8);
@@ -69,7 +70,8 @@ static void __noreturn start_imx6_phytec_common(uint32_t size,
 
 	fdt = fdt_blob_fixed_offset - get_runtime_offset();
 
-	if (cpu_type == IMX6_CPUTYPE_IMX6UL)
+	if (cpu_type == IMX6_CPUTYPE_IMX6UL
+	    || cpu_type == IMX6_CPUTYPE_IMX6ULL)
 		barebox_arm_entry(0x80000000, size, fdt);
 	else
 		barebox_arm_entry(0x10000000, size, fdt);
@@ -111,3 +113,4 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_
 PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true);
 
 PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_512mb, imx6ul_phytec_phycore_som, SZ_512M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_256mb, imx6ull_phytec_phycore_som, SZ_256M, false);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2342d35..ec291ce 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -53,7 +53,8 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \
 				imx6q-phytec-phycore-som-emmc.dtb.o \
 				imx6dl-phytec-phycore-som-nand.dtb.o \
 				imx6dl-phytec-phycore-som-emmc.dtb.o \
-				imx6ul-phytec-phycore-som.dtb.o
+				imx6ul-phytec-phycore-som.dtb.o \
+				imx6ull-phytec-phycore-som.dtb.o
 pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o
 pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o
 pbl-dtb-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
index 65a9365..73f7dbe 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
@@ -13,173 +13,29 @@
 /dts-v1/;
 
 #include <arm/imx6ul.dtsi>
+#include "imx6ul-phytec-phycore-som.dtsi"
 
 / {
 	model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
 	compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
-
-	chosen {
-		linux,stdout-path = &uart1;
-
-		environment-nand {
-			compatible = "barebox,environment";
-			device-path = &gpmi, "partname:barebox-environment";
-			status = "disabled";
-		};
-
-		environment-sd1 {
-			compatible = "barebox,environment";
-			device-path = &usdhc1, "partname:barebox-environment";
-			status = "disabled";
-		};
-	};
 };
 
 &fec1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_enet1>;
-	phy-mode = "rmii";
-	phy-handle = <&ethphy0>;
 	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy0: ethernet-phy@1 {
-			reg = <1>;
-		};
-	};
 };
 
 &gpmi {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	nand-on-flash-bbt;
-	fsl,no-blockmark-swap;
 	status = "okay";
-
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	partition@0 {
-		label = "barebox";
-		reg = <0x0 0x400000>;
-	};
-
-	partition@400000 {
-		label = "barebox-environment";
-		reg = <0x400000 0x100000>;
-	};
-
-	partition@500000 {
-		label = "root";
-		reg = <0x500000 0x0>;
-	};
 };
 
 &i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 =<&pinctrl_i2c1>;
-	clock-frequency = <100000>;
 	status = "okay";
-
-	eeprom@52 {
-		compatible = "cat,24c32";
-		reg = <0x52>;
-	};
 };
 
 &uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart1>;
 	status = "okay";
 };
 
 &usdhc1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc1>;
-	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
 	status = "okay";
-
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	partition@0 {
-		label = "barebox";
-		reg = <0x0 0xe0000>;
-	};
-
-	partition@e0000 {
-		label = "barebox-environment";
-		reg = <0xe0000 0x20000>;
-	};
-};
-
-&iomuxc {
-        pinctrl-names = "default";
-
-	imx6ul-phytec-phycore-som {
-
-		pinctrl_enet1: enet1grp {
-			fsl,pins = <
-				MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
-				MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
-				MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
-				MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
-				MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
-				MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
-				MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
-				MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
-				MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
-				MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
-			>;
-		};
-
-		pinctrl_gpmi_nand: gpminandgrp {
-			fsl,pins = <
-				MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0x0b0b1
-				MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0x0b0b1
-				MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B	0x0b0b1
-				MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0x0b000
-				MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0x0b0b1
-				MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0x0b0b1
-				MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0x0b0b1
-				MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0x0b0b1
-				MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0x0b0b1
-				MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0x0b0b1
-				MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0x0b0b1
-				MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0x0b0b1
-				MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0x0b0b1
-				MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06	0x0b0b1
-				MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0x0b0b1
-			>;
-		};
-
-		pinctrl_i2c1: i2cgrp {
-			fsl,pins = <
-				MX6UL_PAD_UART4_TX_DATA__I2C1_SCL	0x4001b8b0
-				MX6UL_PAD_UART4_RX_DATA__I2C1_SDA	0x4001b8b0
-			>;
-		};
-
-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
-				MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
-			>;
-		};
-
-		pinctrl_usdhc1: usdhc1grp {
-			fsl,pins = <
-				MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x17059
-				MX6UL_PAD_SD1_CLK__USDHC1_CLK     	0x10059
-				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 	0x17059
-				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 	0x17059
-				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 	0x17059
-				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 	0x17059
-				MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
-			>;
-		};
-	};
 };
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
new file mode 100644
index 0000000..96beef4
--- /dev/null
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -0,0 +1,178 @@
+/*
+ * Copyright (C) 2016 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/ {
+	chosen {
+		linux,stdout-path = &uart1;
+
+		environment-nand {
+			compatible = "barebox,environment";
+			device-path = &gpmi, "partname:barebox-environment";
+			status = "disabled";
+		};
+
+		environment-sd1 {
+			compatible = "barebox,environment";
+			device-path = &usdhc1, "partname:barebox-environment";
+			status = "disabled";
+		};
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy0>;
+	status = "disabled";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@1 {
+			reg = <1>;
+		};
+	};
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand>;
+	nand-on-flash-bbt;
+	fsl,no-blockmark-swap;
+	status = "disabled";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0x400000>;
+	};
+
+	partition@400000 {
+		label = "barebox-environment";
+		reg = <0x400000 0x100000>;
+	};
+
+	partition@500000 {
+		label = "root";
+		reg = <0x500000 0x0>;
+	};
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 =<&pinctrl_i2c1>;
+	clock-frequency = <100000>;
+	status = "disabled";
+
+	eeprom@52 {
+		compatible = "cat,24c32";
+		reg = <0x52>;
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "disabled";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+	status = "disabled";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0xe0000>;
+	};
+
+	partition@e0000 {
+		label = "barebox-environment";
+		reg = <0xe0000 0x20000>;
+	};
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+
+	imx6ul-phytec-phycore-som {
+
+		pinctrl_enet1: enet1grp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
+				MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
+				MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
+				MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
+				MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
+				MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
+				MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
+				MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
+				MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
+				MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
+			>;
+		};
+
+		pinctrl_gpmi_nand: gpminandgrp {
+			fsl,pins = <
+				MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0x0b0b1
+				MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0x0b0b1
+				MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B	0x0b0b1
+				MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0x0b000
+				MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0x0b0b1
+				MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0x0b0b1
+				MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0x0b0b1
+				MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0x0b0b1
+				MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0x0b0b1
+				MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0x0b0b1
+				MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0x0b0b1
+				MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0x0b0b1
+				MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0x0b0b1
+				MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06	0x0b0b1
+				MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0x0b0b1
+			>;
+		};
+
+		pinctrl_i2c1: i2cgrp {
+			fsl,pins = <
+				MX6UL_PAD_UART4_TX_DATA__I2C1_SCL	0x4001b8b0
+				MX6UL_PAD_UART4_RX_DATA__I2C1_SDA	0x4001b8b0
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
+				MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x17059
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     	0x10059
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 	0x17059
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 	0x17059
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 	0x17059
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 	0x17059
+				MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
+			>;
+		};
+	};
+};
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som.dts b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
new file mode 100644
index 0000000..de04132
--- /dev/null
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2017 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include <arm/imx6ull.dtsi>
+#include "imx6ul-phytec-phycore-som.dtsi"
+
+/ {
+	model = "Phytec phyCORE-i.MX6 ULL SOM";
+	compatible = "phytec,imx6ul-pcl063", "fsl,imx6ull";
+};
+
+&fec1 {
+	status = "okay";
+};
+
+&gpmi {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&usdhc1 {
+	status = "okay";
+};
diff --git a/images/Makefile.imx b/images/Makefile.imx
index cdad2e0..6ee44f2 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -435,6 +435,11 @@ CFG_start_phytec_phycore_imx6ul_som_512mb.pblx.imximg = $(board)/phytec-som-imx6
 FILE_barebox-phytec-phycore-imx6ul-512mb.img = start_phytec_phycore_imx6ul_som_512mb.pblx.imximg
 image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ul-512mb.img
 
+pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6ull_som_256mb
+CFG_start_phytec_phycore_imx6ull_som_256mb.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg
+FILE_barebox-phytec-phycore-imx6ull-256mb.img = start_phytec_phycore_imx6ull_som_256mb.pblx.imximg
+image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ull-256mb.img
+
 pblx-$(CONFIG_MACH_GW_VENTANA) += start_imx6q_gw54xx_1gx64
 CFG_start_imx6q_gw54xx_1gx64.pblx.imximg = $(board)/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg
 FILE_barebox-gateworks-imx6q-ventana-1gx64.img = start_imx6q_gw54xx_1gx64.pblx.imximg
-- 
1.9.1


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Re: [PATCH 1/3] ARM: i.MX: Add i.MX6 ULL support

[Sascha Hauer]

On Thu, May 11, 2017 at 11:09:26AM +0200, Stefan Riedmueller wrote:
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
> ---
>  arch/arm/mach-imx/imx.c               | 2 ++
>  arch/arm/mach-imx/imx6.c              | 3 +++
>  arch/arm/mach-imx/include/mach/imx6.h | 2 ++
>  3 files changed, 7 insertions(+)

Applied, thanks

Sascha

> 
> diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c
> index 1990739..9400105 100644
> --- a/arch/arm/mach-imx/imx.c
> +++ b/arch/arm/mach-imx/imx.c
> @@ -67,6 +67,8 @@ static int imx_soc_from_dt(void)
>  		return IMX_CPU_IMX6;
>  	if (of_machine_is_compatible("fsl,imx6ul"))
>  		return IMX_CPU_IMX6;
> +	if (of_machine_is_compatible("fsl,imx6ull"))
> +		return IMX_CPU_IMX6;
>  	if (of_machine_is_compatible("fsl,imx7s"))
>  		return IMX_CPU_IMX7;
>  	if (of_machine_is_compatible("fsl,imx7d"))
> diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
> index 44a8dbe..7b3fc1d 100644
> --- a/arch/arm/mach-imx/imx6.c
> +++ b/arch/arm/mach-imx/imx6.c
> @@ -160,6 +160,9 @@ int imx6_init(void)
>  	case IMX6_CPUTYPE_IMX6UL:
>  		cputypestr = "i.MX6 UltraLite";
>  		break;
> +	case IMX6_CPUTYPE_IMX6ULL:
> +		cputypestr = "i.MX6 ULL";
> +		break;
>  	default:
>  		cputypestr = "unknown i.MX6";
>  		break;
> diff --git a/arch/arm/mach-imx/include/mach/imx6.h b/arch/arm/mach-imx/include/mach/imx6.h
> index 327676b..6ad5343 100644
> --- a/arch/arm/mach-imx/include/mach/imx6.h
> +++ b/arch/arm/mach-imx/include/mach/imx6.h
> @@ -18,6 +18,7 @@ void imx6_init_lowlevel(void);
>  #define IMX6_CPUTYPE_IMX6D	0x263
>  #define IMX6_CPUTYPE_IMX6Q	0x463
>  #define IMX6_CPUTYPE_IMX6UL	0x164
> +#define IMX6_CPUTYPE_IMX6ULL	0x165
>  
>  #define SCU_CONFIG              0x04
>  
> @@ -82,6 +83,7 @@ DEFINE_MX6_CPU_TYPE(mx6d, IMX6_CPUTYPE_IMX6D);
>  DEFINE_MX6_CPU_TYPE(mx6sx, IMX6_CPUTYPE_IMX6SX);
>  DEFINE_MX6_CPU_TYPE(mx6sl, IMX6_CPUTYPE_IMX6SL);
>  DEFINE_MX6_CPU_TYPE(mx6ul, IMX6_CPUTYPE_IMX6UL);
> +DEFINE_MX6_CPU_TYPE(mx6ull, IMX6_CPUTYPE_IMX6ULL);
>  
>  static inline int __imx6_cpu_revision(void)
>  {
> -- 
> 1.9.1
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

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