[PATCH] mx5: Implement Spectre v2 workaround for Cortex-A8

[PATCH] mx5: Implement Spectre v2 workaround for Cortex-A8

[Fabio Estevam]

Since 4.18-rc1 kernel the following warning is seen on i.MX51 and
i.MX53:
    
CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable
    
Implement the suggested workaround by setting the IBE bit in the
auxiliary control register.

Based on commit 7b37a9c732bf ("ARM: Introduce ability to enable ACR::IBE
on Cortex-A8 for CVE-2017-5715") from U-Boot.
    
With this patch applied the kernel now reports:
    
CPU0: Spectre v2: using BPIALL workaround

Tested on a imx51 babbage.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
 arch/arm/include/asm/errata.h | 9 +++++++++
 arch/arm/mach-imx/cpu_init.c  | 3 ++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/errata.h b/arch/arm/include/asm/errata.h
index 98137b5..c0e0f5a 100644
--- a/arch/arm/include/asm/errata.h
+++ b/arch/arm/include/asm/errata.h
@@ -86,3 +86,12 @@ static inline void enable_arm_errata_845369_war(void)
 		"mcr	p15, 0, r0, c15, c0, 1\n"
 	);
 }
+
+static inline void enable_arm_errata_cortexa8_cve_2017_5715(void)
+{
+	__asm__ __volatile__ (
+		"mrc	p15, 0, r0, c1, c0, 1\n"
+		"orr	r0, r0, #1 << 6\n"
+		"mcr	p15, 0, r0, c1, c0, 1\n"
+	);
+}
diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
index 5b93d12..e1d88c7 100644
--- a/arch/arm/mach-imx/cpu_init.c
+++ b/arch/arm/mach-imx/cpu_init.c
@@ -22,6 +22,7 @@ void imx5_cpu_lowlevel_init(void)
 	arm_cpu_lowlevel_init();
 
 	enable_arm_errata_709718_war();
+	enable_arm_errata_cortexa8_cve_2017_5715();
 }
 
 void imx6_cpu_lowlevel_init(void)
@@ -51,4 +52,4 @@ void vf610_cpu_lowlevel_init(void)
 {
 	arm_cpu_lowlevel_init();
 }
-#endif
\ No newline at end of file
+#endif
-- 
2.7.4


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Re: [PATCH] mx5: Implement Spectre v2 workaround for Cortex-A8

[Lucas Stach]

Hi Fabio

Am Mittwoch, den 11.07.2018, 19:29 -0300 schrieb Fabio Estevam:
> Since 4.18-rc1 kernel the following warning is seen on i.MX51 and
> i.MX53:
>     
> CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable
>     
> Implement the suggested workaround by setting the IBE bit in the
> auxiliary control register.
> 
> Based on commit 7b37a9c732bf ("ARM: Introduce ability to enable ACR::IBE
> on Cortex-A8 for CVE-2017-5715") from U-Boot.
>     
> With this patch applied the kernel now reports:
>     
> CPU0: Spectre v2: using BPIALL workaround
> 
> Tested on a imx51 babbage.
> 
> > Signed-off-by: Fabio Estevam <festevam@gmail.com>
> ---
>  arch/arm/include/asm/errata.h | 9 +++++++++
>  arch/arm/mach-imx/cpu_init.c  | 3 ++-
>  2 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/include/asm/errata.h b/arch/arm/include/asm/errata.h
> index 98137b5..c0e0f5a 100644
> --- a/arch/arm/include/asm/errata.h
> +++ b/arch/arm/include/asm/errata.h
> @@ -86,3 +86,12 @@ static inline void enable_arm_errata_845369_war(void)
> > >  		"mcr	p15, 0, r0, c15, c0, 1\n"
> >  	);
>  }
> +
> +static inline void enable_arm_errata_cortexa8_cve_2017_5715(void)

Patch looks mostly good, but I don't like the naming here. CVE 2017-
5715 doesn't have a direct correlation with the Cortex A8. Maybe just
name this _cortexa8_enable_ibe? A comment that this allows the kernel
to flush the BTB properly might also help.

Regards,
Lucas


> +{
> > +	__asm__ __volatile__ (
> > > +		"mrc	p15, 0, r0, c1, c0, 1\n"
> > > +		"orr	r0, r0, #1 << 6\n"
> > > +		"mcr	p15, 0, r0, c1, c0, 1\n"
> > +	);
> +}
> diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
> index 5b93d12..e1d88c7 100644
> --- a/arch/arm/mach-imx/cpu_init.c
> +++ b/arch/arm/mach-imx/cpu_init.c
> @@ -22,6 +22,7 @@ void imx5_cpu_lowlevel_init(void)
> >  	arm_cpu_lowlevel_init();
>  
> >  	enable_arm_errata_709718_war();
> > +	enable_arm_errata_cortexa8_cve_2017_5715();
>  }
>  
>  void imx6_cpu_lowlevel_init(void)
> @@ -51,4 +52,4 @@ void vf610_cpu_lowlevel_init(void)
>  {
> >  	arm_cpu_lowlevel_init();
>  }
> -#endif
> \ No newline at end of file
> +#endif

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