* [PATCH v2] mx5: Implement Spectre v2 workaround for Cortex-A8
@ 2018-07-12 17:45 Fabio Estevam
2018-07-13 10:28 ` Lucas Stach
2018-08-08 13:42 ` Sascha Hauer
0 siblings, 2 replies; 3+ messages in thread
From: Fabio Estevam @ 2018-07-12 17:45 UTC (permalink / raw)
To: s.hauer; +Cc: barebox
Since 4.18-rc1 kernel the following warning is seen on i.MX51 and
i.MX53:
CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable
Implement the suggested workaround by setting the IBE bit in the
auxiliary control register, which allows the kernel to flush the
BTB properly.
Based on commit 7b37a9c732bf ("ARM: Introduce ability to enable ACR::IBE
on Cortex-A8 for CVE-2017-5715") from U-Boot.
With this patch applied the kernel now reports:
CPU0: Spectre v2: using BPIALL workaround
Tested on a imx51 babbage.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Changes since v1:
- Rename the function name (Lucas)
- Improve the commit log (Lucas)
arch/arm/include/asm/errata.h | 9 +++++++++
arch/arm/mach-imx/cpu_init.c | 3 ++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/errata.h b/arch/arm/include/asm/errata.h
index 98137b5..c0e0f5a 100644
--- a/arch/arm/include/asm/errata.h
+++ b/arch/arm/include/asm/errata.h
@@ -86,3 +86,12 @@ static inline void enable_arm_errata_845369_war(void)
"mcr p15, 0, r0, c15, c0, 1\n"
);
}
+
+static inline void enable_arm_errata_cortexa8_enable_ibe(void)
+{
+ __asm__ __volatile__ (
+ "mrc p15, 0, r0, c1, c0, 1\n"
+ "orr r0, r0, #1 << 6\n"
+ "mcr p15, 0, r0, c1, c0, 1\n"
+ );
+}
diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
index 5b93d12..e1d88c7 100644
--- a/arch/arm/mach-imx/cpu_init.c
+++ b/arch/arm/mach-imx/cpu_init.c
@@ -22,6 +22,7 @@ void imx5_cpu_lowlevel_init(void)
arm_cpu_lowlevel_init();
enable_arm_errata_709718_war();
+ enable_arm_errata_cortexa8_enable_ibe();
}
void imx6_cpu_lowlevel_init(void)
@@ -51,4 +52,4 @@ void vf610_cpu_lowlevel_init(void)
{
arm_cpu_lowlevel_init();
}
-#endif
\ No newline at end of file
+#endif
--
2.7.4
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] mx5: Implement Spectre v2 workaround for Cortex-A8
2018-07-12 17:45 [PATCH v2] mx5: Implement Spectre v2 workaround for Cortex-A8 Fabio Estevam
@ 2018-07-13 10:28 ` Lucas Stach
2018-08-08 13:42 ` Sascha Hauer
1 sibling, 0 replies; 3+ messages in thread
From: Lucas Stach @ 2018-07-13 10:28 UTC (permalink / raw)
To: Fabio Estevam, s.hauer; +Cc: barebox
Am Donnerstag, den 12.07.2018, 14:45 -0300 schrieb Fabio Estevam:
> Since 4.18-rc1 kernel the following warning is seen on i.MX51 and
> i.MX53:
>
> CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable
>
> Implement the suggested workaround by setting the IBE bit in the
> auxiliary control register, which allows the kernel to flush the
> BTB properly.
>
> Based on commit 7b37a9c732bf ("ARM: Introduce ability to enable ACR::IBE
> on Cortex-A8 for CVE-2017-5715") from U-Boot.
>
> With this patch applied the kernel now reports:
>
> CPU0: Spectre v2: using BPIALL workaround
>
> Tested on a imx51 babbage.
>
> Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> Changes since v1:
> - Rename the function name (Lucas)
> - Improve the commit log (Lucas)
>
> arch/arm/include/asm/errata.h | 9 +++++++++
> arch/arm/mach-imx/cpu_init.c | 3 ++-
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/errata.h b/arch/arm/include/asm/errata.h
> index 98137b5..c0e0f5a 100644
> --- a/arch/arm/include/asm/errata.h
> +++ b/arch/arm/include/asm/errata.h
> @@ -86,3 +86,12 @@ static inline void enable_arm_errata_845369_war(void)
> > > "mcr p15, 0, r0, c15, c0, 1\n"
> > );
> }
> +
> +static inline void enable_arm_errata_cortexa8_enable_ibe(void)
> +{
> > + __asm__ __volatile__ (
> > > + "mrc p15, 0, r0, c1, c0, 1\n"
> > > + "orr r0, r0, #1 << 6\n"
> > > + "mcr p15, 0, r0, c1, c0, 1\n"
> > + );
> +}
> diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
> index 5b93d12..e1d88c7 100644
> --- a/arch/arm/mach-imx/cpu_init.c
> +++ b/arch/arm/mach-imx/cpu_init.c
> @@ -22,6 +22,7 @@ void imx5_cpu_lowlevel_init(void)
> > arm_cpu_lowlevel_init();
>
> > enable_arm_errata_709718_war();
> > + enable_arm_errata_cortexa8_enable_ibe();
> }
>
> void imx6_cpu_lowlevel_init(void)
> @@ -51,4 +52,4 @@ void vf610_cpu_lowlevel_init(void)
> {
> > arm_cpu_lowlevel_init();
> }
> -#endif
> \ No newline at end of file
> +#endif
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] mx5: Implement Spectre v2 workaround for Cortex-A8
2018-07-12 17:45 [PATCH v2] mx5: Implement Spectre v2 workaround for Cortex-A8 Fabio Estevam
2018-07-13 10:28 ` Lucas Stach
@ 2018-08-08 13:42 ` Sascha Hauer
1 sibling, 0 replies; 3+ messages in thread
From: Sascha Hauer @ 2018-08-08 13:42 UTC (permalink / raw)
To: Fabio Estevam; +Cc: barebox
On Thu, Jul 12, 2018 at 02:45:03PM -0300, Fabio Estevam wrote:
> Since 4.18-rc1 kernel the following warning is seen on i.MX51 and
> i.MX53:
>
> CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable
>
> Implement the suggested workaround by setting the IBE bit in the
> auxiliary control register, which allows the kernel to flush the
> BTB properly.
>
> Based on commit 7b37a9c732bf ("ARM: Introduce ability to enable ACR::IBE
> on Cortex-A8 for CVE-2017-5715") from U-Boot.
>
> With this patch applied the kernel now reports:
>
> CPU0: Spectre v2: using BPIALL workaround
>
> Tested on a imx51 babbage.
>
> Signed-off-by: Fabio Estevam <festevam@gmail.com>
> ---
Applied, thanks
Sascha
> Changes since v1:
> - Rename the function name (Lucas)
> - Improve the commit log (Lucas)
>
> arch/arm/include/asm/errata.h | 9 +++++++++
> arch/arm/mach-imx/cpu_init.c | 3 ++-
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/errata.h b/arch/arm/include/asm/errata.h
> index 98137b5..c0e0f5a 100644
> --- a/arch/arm/include/asm/errata.h
> +++ b/arch/arm/include/asm/errata.h
> @@ -86,3 +86,12 @@ static inline void enable_arm_errata_845369_war(void)
> "mcr p15, 0, r0, c15, c0, 1\n"
> );
> }
> +
> +static inline void enable_arm_errata_cortexa8_enable_ibe(void)
> +{
> + __asm__ __volatile__ (
> + "mrc p15, 0, r0, c1, c0, 1\n"
> + "orr r0, r0, #1 << 6\n"
> + "mcr p15, 0, r0, c1, c0, 1\n"
> + );
> +}
> diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
> index 5b93d12..e1d88c7 100644
> --- a/arch/arm/mach-imx/cpu_init.c
> +++ b/arch/arm/mach-imx/cpu_init.c
> @@ -22,6 +22,7 @@ void imx5_cpu_lowlevel_init(void)
> arm_cpu_lowlevel_init();
>
> enable_arm_errata_709718_war();
> + enable_arm_errata_cortexa8_enable_ibe();
> }
>
> void imx6_cpu_lowlevel_init(void)
> @@ -51,4 +52,4 @@ void vf610_cpu_lowlevel_init(void)
> {
> arm_cpu_lowlevel_init();
> }
> -#endif
> \ No newline at end of file
> +#endif
> --
> 2.7.4
>
>
--
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2018-07-12 17:45 [PATCH v2] mx5: Implement Spectre v2 workaround for Cortex-A8 Fabio Estevam
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