* [PATCH 2/8] ARM: dts: imx6qdl: phycore: Add state framework
2019-07-02 12:37 [PATCH 1/8] ARM: phytec-som-imx6: Add low cost variant for imx6dl phycore Stefan Riedmueller
@ 2019-07-02 12:37 ` Stefan Riedmueller
2019-07-02 12:37 ` [PATCH 3/8] ARM: dts: imx6ul: phycore: Add eeprom label Stefan Riedmueller
` (5 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Stefan Riedmueller @ 2019-07-02 12:37 UTC (permalink / raw)
To: barebox
From: Daniel Schultz <d.schultz@phytec.de>
Add the state framework with EEPROM backend.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts | 1 +
arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts | 1 +
arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts | 1 +
arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts | 1 +
arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts | 1 +
arch/arm/dts/imx6q-phytec-phycore-som-nand.dts | 1 +
arch/arm/dts/imx6qdl-phytec-state.dtsi | 81 ++++++++++++++++++++++
7 files changed, 87 insertions(+)
create mode 100644 arch/arm/dts/imx6qdl-phytec-state.dtsi
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
index a04e37f80363..21cbb5f944c9 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
@@ -15,6 +15,7 @@
#include <arm/imx6dl.dtsi>
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-state.dtsi"
/ {
model = "Phytec phyCORE-i.MX6 DualLite/SOLO with eMMC";
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
index 5d9727ec5b80..b8efb95ee08a 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
@@ -9,6 +9,7 @@
#include <arm/imx6dl.dtsi>
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-state.dtsi"
/ {
model = "PHYTEC phyCORE-i.MX6 DualLite/SOLO with eMMC low-cost";
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
index e119e4c0d4fc..4d38d1698a48 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
@@ -9,6 +9,7 @@
#include <arm/imx6dl.dtsi>
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-state.dtsi"
/ {
model = "PHYTEC phyCORE-i.MX6 Duallite/SOLO with NAND low-cost";
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
index 287d876e41ed..3ad3723d2893 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
@@ -14,6 +14,7 @@
#include <arm/imx6dl.dtsi>
#include "imx6dl.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-state.dtsi"
/ {
model = "Phytec phyCORE-i.MX6 Duallite/SOLO with NAND";
diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
index 94a70389f084..7a86d5b94daf 100644
--- a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
@@ -14,6 +14,7 @@
#include <arm/imx6q.dtsi>
#include "imx6q.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-state.dtsi"
/ {
model = "Phytec phyCORE-i.MX6 Quad with eMMC";
diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
index 6d82ec34d6e5..96d1de224c9e 100644
--- a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
+++ b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
@@ -14,6 +14,7 @@
#include <arm/imx6q.dtsi>
#include "imx6q.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-state.dtsi"
/ {
model = "Phytec phyCORE-i.MX6 Quad with NAND";
diff --git a/arch/arm/dts/imx6qdl-phytec-state.dtsi b/arch/arm/dts/imx6qdl-phytec-state.dtsi
new file mode 100644
index 000000000000..76aa15f3e2f7
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-phytec-state.dtsi
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH,
+ * Author: Daniel Schultz <d.schultz@phytec.de>
+ */
+
+/ {
+ aliases {
+ state = &state;
+ };
+
+ state: imx6qdl_phytec_boot_state {
+ magic = <0x883b86a6>;
+ compatible = "barebox,state";
+ backend-type = "raw";
+ backend = <&backend_update_eeprom>;
+ backend-stridesize = <54>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootstate {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ last_chosen {
+ reg = <0x0 0x4>;
+ type = "uint32";
+ };
+ system0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ remaining_attempts {
+ reg = <0x4 0x4>;
+ type = "uint32";
+ default = <3>;
+ };
+ priority {
+ reg = <0x8 0x4>;
+ type = "uint32";
+ default = <21>;
+ };
+ ok {
+ reg = <0xc 0x4>;
+ type = "uint32";
+ default = <0>;
+ };
+ };
+ system1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ remaining_attempts {
+ reg = <0x10 0x4>;
+ type = "uint32";
+ default = <3>;
+ };
+ priority {
+ reg = <0x14 0x4>;
+ type = "uint32";
+ default = <20>;
+ };
+ ok {
+ reg = <0x18 0x4>;
+ type = "uint32";
+ default = <0>;
+ };
+ };
+ };
+ };
+};
+
+&eeprom {
+ status = "okay";
+ partitions {
+ compatible = "fixed-partitions";
+ #size-cells = <1>;
+ #address-cells = <1>;
+ backend_update_eeprom: state@0 {
+ reg = <0x0 0x100>;
+ label = "update-eeprom";
+ };
+ };
+};
--
2.7.4
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^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 3/8] ARM: dts: imx6ul: phycore: Add eeprom label
2019-07-02 12:37 [PATCH 1/8] ARM: phytec-som-imx6: Add low cost variant for imx6dl phycore Stefan Riedmueller
2019-07-02 12:37 ` [PATCH 2/8] ARM: dts: imx6qdl: phycore: Add state framework Stefan Riedmueller
@ 2019-07-02 12:37 ` Stefan Riedmueller
2019-07-02 12:37 ` [PATCH 4/8] ARM: dts: imx6ul: phycore: Add state framework Stefan Riedmueller
` (4 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Stefan Riedmueller @ 2019-07-02 12:37 UTC (permalink / raw)
To: barebox
Add a label for the EEPROM to be able to address it for the state
framework.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/dts/imx6ul-phytec-phycore-som.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
index 964f91950d93..1ef9d547822e 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -79,7 +79,7 @@
clock-frequency = <100000>;
status = "disabled";
- eeprom@52 {
+ eeprom: eeprom@52 {
compatible = "cat,24c32";
reg = <0x52>;
};
--
2.7.4
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^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 4/8] ARM: dts: imx6ul: phycore: Add state framework
2019-07-02 12:37 [PATCH 1/8] ARM: phytec-som-imx6: Add low cost variant for imx6dl phycore Stefan Riedmueller
2019-07-02 12:37 ` [PATCH 2/8] ARM: dts: imx6qdl: phycore: Add state framework Stefan Riedmueller
2019-07-02 12:37 ` [PATCH 3/8] ARM: dts: imx6ul: phycore: Add eeprom label Stefan Riedmueller
@ 2019-07-02 12:37 ` Stefan Riedmueller
2019-07-09 8:57 ` Roland Hieber
2019-07-02 12:37 ` [PATCH 5/8] ARM: imx6ul: phycore: Prepare for eMMC module Stefan Riedmueller
` (3 subsequent siblings)
6 siblings, 1 reply; 12+ messages in thread
From: Stefan Riedmueller @ 2019-07-02 12:37 UTC (permalink / raw)
To: barebox
From: Daniel Schultz <d.schultz@phytec.de>
Add the state framework with EEPROM backend.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/dts/imx6ul-phytec-phycore-som.dts | 5 ++
arch/arm/dts/imx6ul-phytec-state.dtsi | 81 +++++++++++++++++++++++++++++
arch/arm/dts/imx6ull-phytec-phycore-som.dts | 5 ++
3 files changed, 91 insertions(+)
create mode 100644 arch/arm/dts/imx6ul-phytec-state.dtsi
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
index 6d1876702d1b..11418ea7f038 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
@@ -14,6 +14,7 @@
#include <arm/imx6ul.dtsi>
#include "imx6ul-phytec-phycore-som.dtsi"
+#include "imx6ul-phytec-state.dtsi"
/ {
model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
@@ -32,6 +33,10 @@
status = "okay";
};
+&state {
+ status = "okay";
+};
+
&uart1 {
status = "okay";
};
diff --git a/arch/arm/dts/imx6ul-phytec-state.dtsi b/arch/arm/dts/imx6ul-phytec-state.dtsi
new file mode 100644
index 000000000000..a21cb49f00ce
--- /dev/null
+++ b/arch/arm/dts/imx6ul-phytec-state.dtsi
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH,
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+/ {
+ aliases {
+ state = &state;
+ };
+
+ state: imx6ul_phytec_boot_state {
+ magic = <0x883b86a6>;
+ compatible = "barebox,state";
+ backend-type = "raw";
+ backend = <&backend_update_eeprom>;
+ backend-stridesize = <54>;
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootstate {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ last_chosen {
+ reg = <0x0 0x4>;
+ type = "uint32";
+ };
+ system0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ remaining_attempts {
+ reg = <0x4 0x4>;
+ type = "uint32";
+ default = <3>;
+ };
+ priority {
+ reg = <0x8 0x4>;
+ type = "uint32";
+ default = <21>;
+ };
+ ok {
+ reg = <0xc 0x4>;
+ type = "uint32";
+ default = <0>;
+ };
+ };
+ system1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ remaining_attempts {
+ reg = <0x10 0x4>;
+ type = "uint32";
+ default = <3>;
+ };
+ priority {
+ reg = <0x14 0x4>;
+ type = "uint32";
+ default = <20>;
+ };
+ ok {
+ reg = <0x18 0x4>;
+ type = "uint32";
+ default = <0>;
+ };
+ };
+ };
+ };
+};
+
+&eeprom {
+ partitions {
+ compatible = "fixed-partitions";
+ #size-cells = <1>;
+ #address-cells = <1>;
+ backend_update_eeprom: state@0 {
+ reg = <0x0 0x100>;
+ label = "update-eeprom";
+ };
+ };
+};
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som.dts b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
index 4d73010131ee..86f43a4632a7 100644
--- a/arch/arm/dts/imx6ull-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
@@ -14,6 +14,7 @@
#include <arm/imx6ull.dtsi>
#include "imx6ul-phytec-phycore-som.dtsi"
+#include "imx6ul-phytec-state.dtsi"
/ {
model = "Phytec phyCORE-i.MX6 ULL SOM";
@@ -32,6 +33,10 @@
status = "okay";
};
+&state {
+ status = "okay";
+};
+
&uart1 {
status = "okay";
};
--
2.7.4
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^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 4/8] ARM: dts: imx6ul: phycore: Add state framework
2019-07-02 12:37 ` [PATCH 4/8] ARM: dts: imx6ul: phycore: Add state framework Stefan Riedmueller
@ 2019-07-09 8:57 ` Roland Hieber
0 siblings, 0 replies; 12+ messages in thread
From: Roland Hieber @ 2019-07-09 8:57 UTC (permalink / raw)
To: Stefan Riedmueller, Daniel Schultz; +Cc: barebox
On Tue, Jul 02, 2019 at 02:37:41PM +0200, Stefan Riedmueller wrote:
> From: Daniel Schultz <d.schultz@phytec.de>
>
> Add the state framework with EEPROM backend.
>
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Missing S-o-b from Daniel
> ---
> arch/arm/dts/imx6ul-phytec-phycore-som.dts | 5 ++
> arch/arm/dts/imx6ul-phytec-state.dtsi | 81 +++++++++++++++++++++++++++++
> arch/arm/dts/imx6ull-phytec-phycore-som.dts | 5 ++
> 3 files changed, 91 insertions(+)
> create mode 100644 arch/arm/dts/imx6ul-phytec-state.dtsi
>
> diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
> index 6d1876702d1b..11418ea7f038 100644
> --- a/arch/arm/dts/imx6ul-phytec-phycore-som.dts
> +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
> @@ -14,6 +14,7 @@
>
> #include <arm/imx6ul.dtsi>
> #include "imx6ul-phytec-phycore-som.dtsi"
> +#include "imx6ul-phytec-state.dtsi"
>
> / {
> model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
> @@ -32,6 +33,10 @@
> status = "okay";
> };
>
> +&state {
> + status = "okay";
> +};
> +
> &uart1 {
> status = "okay";
> };
> diff --git a/arch/arm/dts/imx6ul-phytec-state.dtsi b/arch/arm/dts/imx6ul-phytec-state.dtsi
> new file mode 100644
> index 000000000000..a21cb49f00ce
> --- /dev/null
> +++ b/arch/arm/dts/imx6ul-phytec-state.dtsi
> @@ -0,0 +1,81 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 PHYTEC Messtechnik GmbH,
> + * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
> + */
> +
> +/ {
> + aliases {
> + state = &state;
> + };
> +
> + state: imx6ul_phytec_boot_state {
> + magic = <0x883b86a6>;
> + compatible = "barebox,state";
> + backend-type = "raw";
> + backend = <&backend_update_eeprom>;
> + backend-stridesize = <54>;
> + status = "disabled";
Same here too for missing backend-storage-type.
- Roland
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + bootstate {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + last_chosen {
> + reg = <0x0 0x4>;
> + type = "uint32";
> + };
> + system0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + remaining_attempts {
> + reg = <0x4 0x4>;
> + type = "uint32";
> + default = <3>;
> + };
> + priority {
> + reg = <0x8 0x4>;
> + type = "uint32";
> + default = <21>;
> + };
> + ok {
> + reg = <0xc 0x4>;
> + type = "uint32";
> + default = <0>;
> + };
> + };
> + system1 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + remaining_attempts {
> + reg = <0x10 0x4>;
> + type = "uint32";
> + default = <3>;
> + };
> + priority {
> + reg = <0x14 0x4>;
> + type = "uint32";
> + default = <20>;
> + };
> + ok {
> + reg = <0x18 0x4>;
> + type = "uint32";
> + default = <0>;
> + };
> + };
> + };
> + };
> +};
> +
> +&eeprom {
> + partitions {
> + compatible = "fixed-partitions";
> + #size-cells = <1>;
> + #address-cells = <1>;
> + backend_update_eeprom: state@0 {
> + reg = <0x0 0x100>;
> + label = "update-eeprom";
> + };
> + };
> +};
> diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som.dts b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
> index 4d73010131ee..86f43a4632a7 100644
> --- a/arch/arm/dts/imx6ull-phytec-phycore-som.dts
> +++ b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
> @@ -14,6 +14,7 @@
>
> #include <arm/imx6ull.dtsi>
> #include "imx6ul-phytec-phycore-som.dtsi"
> +#include "imx6ul-phytec-state.dtsi"
>
> / {
> model = "Phytec phyCORE-i.MX6 ULL SOM";
> @@ -32,6 +33,10 @@
> status = "okay";
> };
>
> +&state {
> + status = "okay";
> +};
> +
> &uart1 {
> status = "okay";
> };
> --
> 2.7.4
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
--
Roland Hieber | r.hieber@pengutronix.de |
Pengutronix e.K. | https://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim | Phone: +49-5121-206917-5086 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 5/8] ARM: imx6ul: phycore: Prepare for eMMC module
2019-07-02 12:37 [PATCH 1/8] ARM: phytec-som-imx6: Add low cost variant for imx6dl phycore Stefan Riedmueller
` (2 preceding siblings ...)
2019-07-02 12:37 ` [PATCH 4/8] ARM: dts: imx6ul: phycore: Add state framework Stefan Riedmueller
@ 2019-07-02 12:37 ` Stefan Riedmueller
2019-07-02 12:37 ` [PATCH 6/8] ARM: phytec-som-imx: imx6ul: Add eMMC support Stefan Riedmueller
` (2 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Stefan Riedmueller @ 2019-07-02 12:37 UTC (permalink / raw)
To: barebox
Prepare for the new phyCORE-i.MX 6UL/ULL eMMC module by extending the
dts filenames by their boot medium. Also add the boot medium to the
compatible to be able to perform boot medium dependent setup code.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boards/phytec-som-imx6/board.c | 4 +-
arch/arm/boards/phytec-som-imx6/lowlevel.c | 6 +--
arch/arm/dts/Makefile | 6 +--
arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts | 48 +++++++++++++++++++
arch/arm/dts/imx6ul-phytec-phycore-som.dts | 54 ----------------------
....dts => imx6ull-phytec-phycore-som-lc-nand.dts} | 6 +--
...som.dts => imx6ull-phytec-phycore-som-nand.dts} | 14 ++----
images/Makefile.imx | 28 +++++------
8 files changed, 77 insertions(+), 89 deletions(-)
create mode 100644 arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts
delete mode 100644 arch/arm/dts/imx6ul-phytec-phycore-som.dts
rename arch/arm/dts/{imx6ull-phytec-phycore-som-lc.dts => imx6ull-phytec-phycore-som-lc-nand.dts} (70%)
rename arch/arm/dts/{imx6ull-phytec-phycore-som.dts => imx6ull-phytec-phycore-som-nand.dts} (50%)
diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c
index d80851797597..cf50ad99b2fc 100644
--- a/arch/arm/boards/phytec-som-imx6/board.c
+++ b/arch/arm/boards/phytec-som-imx6/board.c
@@ -190,7 +190,7 @@ static int physom_imx6_devices_init(void)
default_environment_path = "/chosen/environment-spinor";
default_envdev = "SPI NOR flash";
- } else if (of_machine_is_compatible("phytec,imx6ul-pcl063")) {
+ } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")) {
barebox_set_hostname("phyCORE-i.MX6UL");
default_environment_path = "/chosen/environment-nand";
default_envdev = "NAND flash";
@@ -249,7 +249,7 @@ static int physom_imx6_devices_init(void)
|| of_machine_is_compatible("phytec,imx6dl-pcm058-nand")
|| of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) {
defaultenv_append_directory(defaultenv_physom_imx6_phycore);
- } else if (of_machine_is_compatible("phytec,imx6ul-pcl063")) {
+ } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")) {
defaultenv_append_directory(defaultenv_physom_imx6ul_phycore);
}
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 0f8d591b3a71..494087ab1479 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -118,6 +118,6 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6qp_som_nand_1gib, imx6qp_phytec_phycore_so
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_emmc, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true);
-PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_512mb, imx6ul_phytec_phycore_som, SZ_512M, false);
-PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_lc_256mb, imx6ull_phytec_phycore_som_lc, SZ_256M, false);
-PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_512mb, imx6ull_phytec_phycore_som, SZ_512M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_nand_512mb, imx6ul_phytec_phycore_som_nand, SZ_512M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_lc_nand_256mb, imx6ull_phytec_phycore_som_lc_nand, SZ_256M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_nand_512mb, imx6ull_phytec_phycore_som_nand, SZ_512M, false);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2a2d7a55b820..c96f040ae311 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -66,9 +66,9 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \
imx6dl-phytec-phycore-som-lc-nand.dtb.o \
imx6dl-phytec-phycore-som-emmc.dtb.o \
imx6dl-phytec-phycore-som-lc-emmc.dtb.o \
- imx6ul-phytec-phycore-som.dtb.o \
- imx6ull-phytec-phycore-som-lc.dtb.o \
- imx6ull-phytec-phycore-som.dtb.o
+ imx6ul-phytec-phycore-som-nand.dtb.o \
+ imx6ull-phytec-phycore-som-lc-nand.dtb.o \
+ imx6ull-phytec-phycore-som-nand.dtb.o
pbl-dtb-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o
pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += imx8mq-phytec-phycore-som.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts
new file mode 100644
index 000000000000..67478e26dc63
--- /dev/null
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+/dts-v1/;
+
+#include <arm/imx6ul.dtsi>
+#include "imx6ul-phytec-phycore-som.dtsi"
+#include "imx6ul-phytec-state.dtsi"
+
+/ {
+ model = "PHYTEC phyCORE-i.MX6 Ultra Lite SOM with NAND";
+ compatible = "phytec,imx6ul-pcl063-nand", "fsl,imx6ul";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&gpmi {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&state {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+};
+
+&usbotg1 {
+ status = "okay";
+};
+
+&usbotg2 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
deleted file mode 100644
index 11418ea7f038..000000000000
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dts
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (C) 2016 PHYTEC Messtechnik GmbH
- * Author: Christian Hemp <c.hemp@phytec.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-
-#include <arm/imx6ul.dtsi>
-#include "imx6ul-phytec-phycore-som.dtsi"
-#include "imx6ul-phytec-state.dtsi"
-
-/ {
- model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
- compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
-};
-
-&fec1 {
- status = "okay";
-};
-
-&gpmi {
- status = "okay";
-};
-
-&i2c1 {
- status = "okay";
-};
-
-&state {
- status = "okay";
-};
-
-&uart1 {
- status = "okay";
-};
-
-&usdhc1 {
- status = "okay";
-};
-
-&usbotg1 {
- status = "okay";
-};
-
-&usbotg2 {
- status = "okay";
-};
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts b/arch/arm/dts/imx6ull-phytec-phycore-som-lc-nand.dts
similarity index 70%
rename from arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts
rename to arch/arm/dts/imx6ull-phytec-phycore-som-lc-nand.dts
index 94a783075651..e6c588b44966 100644
--- a/arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som-lc-nand.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
- * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
* Author: Stefan Riedmueller <s.riedmueller@phytec.de>
*/
@@ -10,8 +10,8 @@
#include "imx6ul-phytec-phycore-som.dtsi"
/ {
- model = "Phytec phyCORE-i.MX6 ULL SOM low-cost";
- compatible = "phytec,imx6ul-pcl063", "fsl,imx6ull";
+ model = "PHYTEC phyCORE-i.MX6 ULL SOM low-cost with NAND";
+ compatible = "phytec,imx6ul-pcl063-nand", "fsl,imx6ull";
};
&fec1 {
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som.dts b/arch/arm/dts/imx6ull-phytec-phycore-som-nand.dts
similarity index 50%
rename from arch/arm/dts/imx6ull-phytec-phycore-som.dts
rename to arch/arm/dts/imx6ull-phytec-phycore-som-nand.dts
index 86f43a4632a7..a5fa3e051c66 100644
--- a/arch/arm/dts/imx6ull-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som-nand.dts
@@ -1,13 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
- * Copyright (C) 2017 PHYTEC Messtechnik GmbH
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
* Author: Stefan Riedmueller <s.riedmueller@phytec.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
@@ -17,8 +11,8 @@
#include "imx6ul-phytec-state.dtsi"
/ {
- model = "Phytec phyCORE-i.MX6 ULL SOM";
- compatible = "phytec,imx6ul-pcl063", "fsl,imx6ull";
+ model = "PHYTEC phyCORE-i.MX6 ULL SOM with NAND";
+ compatible = "phytec,imx6ul-pcl063-nand", "fsl,imx6ull";
};
&fec1 {
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 95ed6392e3c6..8aedc906dc84 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -504,20 +504,20 @@ CFG_start_nxp_imx6ull_evk.pblb.imximg = $(board)/nxp-imx6ull-evk/flash-header-nx
FILE_barebox-nxp-imx6ull-evk.img = start_nxp_imx6ull_evk.pblb.imximg
image-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += barebox-nxp-imx6ull-evk.img
-pblb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6ul_som_512mb
-CFG_start_phytec_phycore_imx6ul_som_512mb.pblb.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcl063-512mb.imxcfg
-FILE_barebox-phytec-phycore-imx6ul-512mb.img = start_phytec_phycore_imx6ul_som_512mb.pblb.imximg
-image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ul-512mb.img
-
-pblb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6ull_som_lc_256mb
-CFG_start_phytec_phycore_imx6ull_som_lc_256mb.pblb.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg
-FILE_barebox-phytec-phycore-imx6ull-lc-256mb.img = start_phytec_phycore_imx6ull_som_lc_256mb.pblb.imximg
-image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ull-lc-256mb.img
-
-pblb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6ull_som_512mb
-CFG_start_phytec_phycore_imx6ull_som_512mb.pblb.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcl063-512mb.imxcfg
-FILE_barebox-phytec-phycore-imx6ull-512mb.img = start_phytec_phycore_imx6ull_som_512mb.pblb.imximg
-image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ull-512mb.img
+pblb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6ul_som_nand_512mb
+CFG_start_phytec_phycore_imx6ul_som_nand_512mb.pblb.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcl063-512mb.imxcfg
+FILE_barebox-phytec-phycore-imx6ul-nand-512mb.img = start_phytec_phycore_imx6ul_som_nand_512mb.pblb.imximg
+image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ul-nand-512mb.img
+
+pblb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6ull_som_lc_nand_256mb
+CFG_start_phytec_phycore_imx6ull_som_lc_nand_256mb.pblb.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg
+FILE_barebox-phytec-phycore-imx6ull-lc-nand-256mb.img = start_phytec_phycore_imx6ull_som_lc_nand_256mb.pblb.imximg
+image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ull-lc-nand-256mb.img
+
+pblb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6ull_som_nand_512mb
+CFG_start_phytec_phycore_imx6ull_som_nand_512mb.pblb.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcl063-512mb.imxcfg
+FILE_barebox-phytec-phycore-imx6ull-nand-512mb.img = start_phytec_phycore_imx6ull_som_nand_512mb.pblb.imximg
+image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ull-nand-512mb.img
pblb-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += start_imx6ul_pico_hobbit_256mb
CFG_start_imx6ul_pico_hobbit_256mb.pblb.imximg = $(board)/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg
--
2.7.4
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^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 6/8] ARM: phytec-som-imx: imx6ul: Add eMMC support
2019-07-02 12:37 [PATCH 1/8] ARM: phytec-som-imx6: Add low cost variant for imx6dl phycore Stefan Riedmueller
` (3 preceding siblings ...)
2019-07-02 12:37 ` [PATCH 5/8] ARM: imx6ul: phycore: Prepare for eMMC module Stefan Riedmueller
@ 2019-07-02 12:37 ` Stefan Riedmueller
2019-07-02 12:37 ` [PATCH 7/8] ARM: dts: imx6ul: phycore: Add support for eMMC Stefan Riedmueller
2019-07-02 12:37 ` [PATCH 8/8] ARM: dts: imx6ul: phycore: Add phyCORE-i.MX 6ULL with eMMC Stefan Riedmueller
6 siblings, 0 replies; 12+ messages in thread
From: Stefan Riedmueller @ 2019-07-02 12:37 UTC (permalink / raw)
To: barebox
Add initial support for phyCORE-i.MX 6UL/ULL with eMMC. Including board
code and default environment.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boards/phytec-som-imx6/board.c | 18 +++++++++++++++---
.../defaultenv-physom-imx6ul-phycore/boot/emmc | 5 +++++
.../defaultenv-physom-imx6ul-phycore/boot/mmc | 5 +++++
.../defaultenv-physom-imx6ul-phycore/init/automount | 5 +++++
.../defaultenv-physom-imx6ul-phycore/init/bootsource | 17 +++++++++++++++++
5 files changed, 47 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/emmc
create mode 100644 arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/mmc
create mode 100644 arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/init/bootsource
diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c
index cf50ad99b2fc..730115702bb0 100644
--- a/arch/arm/boards/phytec-som-imx6/board.c
+++ b/arch/arm/boards/phytec-som-imx6/board.c
@@ -190,7 +190,8 @@ static int physom_imx6_devices_init(void)
default_environment_path = "/chosen/environment-spinor";
default_envdev = "SPI NOR flash";
- } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")) {
+ } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")
+ || of_machine_is_compatible("phytec,imx6ul-pcl063-emmc")) {
barebox_set_hostname("phyCORE-i.MX6UL");
default_environment_path = "/chosen/environment-nand";
default_envdev = "NAND flash";
@@ -236,6 +237,10 @@ static int physom_imx6_devices_init(void)
imx6_bbu_internal_mmc_register_handler("mmc3",
"/dev/mmc3",
BBU_HANDLER_FLAG_DEFAULT);
+ } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-emmc")) {
+ imx6_bbu_internal_mmc_register_handler("mmc1",
+ "/dev/mmc1",
+ BBU_HANDLER_FLAG_DEFAULT);
} else {
imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT);
}
@@ -243,13 +248,20 @@ static int physom_imx6_devices_init(void)
defaultenv_append_directory(defaultenv_physom_imx6);
/* Overwrite file /env/init/automount */
- if (of_machine_is_compatible("phytec,imx6qp-pcm058-nand")
+ if (of_machine_is_compatible("phytec,imx6q-pfla02")
+ || of_machine_is_compatible("phytec,imx6dl-pfla02")
+ || of_machine_is_compatible("phytec,imx6s-pfla02")
+ || of_machine_is_compatible("phytec,imx6q-pcaaxl3")) {
+ defaultenv_append_directory(defaultenv_physom_imx6);
+ } else if (of_machine_is_compatible("phytec,imx6qp-pcm058-nand")
|| of_machine_is_compatible("phytec,imx6q-pcm058-nand")
|| of_machine_is_compatible("phytec,imx6q-pcm058-emmc")
|| of_machine_is_compatible("phytec,imx6dl-pcm058-nand")
|| of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) {
+ defaultenv_append_directory(defaultenv_physom_imx6);
defaultenv_append_directory(defaultenv_physom_imx6_phycore);
- } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")) {
+ } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand")
+ || of_machine_is_compatible("phytec,imx6ul-pcl063-emmc")) {
defaultenv_append_directory(defaultenv_physom_imx6ul_phycore);
}
diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/emmc b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/emmc
new file mode 100644
index 000000000000..15cba6f5ac1b
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/emmc
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+global.bootm.image="/mnt/emmc/zImage"
+global.bootm.oftree="/mnt/emmc/oftree"
+global.linux.bootargs.dyn.root="root=/dev/mmcblk1p2 rootflags='discard,data=journal'"
diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/mmc b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/mmc
new file mode 100644
index 000000000000..8de2efa997d9
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/mmc
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+global.bootm.image="/mnt/mmc/zImage"
+global.bootm.oftree="/mnt/mmc/oftree"
+global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootflags='data=journal'"
diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/init/automount b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/init/automount
index 71d9086582d0..36759de7c679 100644
--- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/init/automount
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/init/automount
@@ -7,3 +7,8 @@ automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp'
mkdir -p /mnt/mmc
automount -d /mnt/mmc 'mmc0.probe=1 && [ -e /dev/mmc0.0 ] && mount /dev/mmc0.0 /mnt/mmc'
+
+if [ -e /dev/mmc1 ]; then
+ mkdir -p /mnt/emmc
+ automount -d /mnt/emmc 'mmc1.probe=1 && [ -e /dev/mmc1.0 ] && mount /dev/mmc1.0 /mnt/emmc'
+fi
diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/init/bootsource b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/init/bootsource
new file mode 100644
index 000000000000..beb7afe9c28e
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/init/bootsource
@@ -0,0 +1,17 @@
+#!/bin/sh
+
+if [ -n "$nv.boot.default" ]; then
+ exit
+fi
+
+if [ $bootsource = mmc ]; then
+ if [ $bootsource_instance = 0 ]; then
+ global.boot.default="mmc emmc nand spi net"
+ elif [ $bootsource_instance = 1 ]; then
+ global.boot.default="emmc mmc nand spi net"
+ fi
+elif [ $bootsource = nand ]; then
+ global.boot.default="nand spi mmc net"
+elif [ $bootsource = net ]; then
+ global.boot.default="net nand spi mmc"
+fi
--
2.7.4
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^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 7/8] ARM: dts: imx6ul: phycore: Add support for eMMC
2019-07-02 12:37 [PATCH 1/8] ARM: phytec-som-imx6: Add low cost variant for imx6dl phycore Stefan Riedmueller
` (4 preceding siblings ...)
2019-07-02 12:37 ` [PATCH 6/8] ARM: phytec-som-imx: imx6ul: Add eMMC support Stefan Riedmueller
@ 2019-07-02 12:37 ` Stefan Riedmueller
2019-07-02 12:37 ` [PATCH 8/8] ARM: dts: imx6ul: phycore: Add phyCORE-i.MX 6ULL with eMMC Stefan Riedmueller
6 siblings, 0 replies; 12+ messages in thread
From: Stefan Riedmueller @ 2019-07-02 12:37 UTC (permalink / raw)
To: barebox
Add support for phyCORE-i.MX 6UL/ULL modules with eMMC instead of NAND
flash.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/dts/imx6ul-phytec-phycore-som.dtsi | 42 +++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
index 1ef9d547822e..0ec7eae1eff0 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -25,6 +25,12 @@
device-path = &usdhc1, "partname:barebox-environment";
status = "disabled";
};
+
+ environment-sd2 {
+ compatible = "barebox,environment";
+ device-path = &usdhc2, "partname:barebox-environment";
+ status = "disabled";
+ };
};
};
@@ -125,6 +131,27 @@
};
};
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <8>;
+ non-removable;
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xe0000>;
+ };
+
+ partition@e0000 {
+ label = "barebox-environment";
+ reg = <0xe0000 0x20000>;
+ };
+};
+
&iomuxc {
pinctrl-names = "default";
@@ -196,6 +223,21 @@
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
>;
};
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
+ >;
+ };
};
};
--
2.7.4
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^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 8/8] ARM: dts: imx6ul: phycore: Add phyCORE-i.MX 6ULL with eMMC
2019-07-02 12:37 [PATCH 1/8] ARM: phytec-som-imx6: Add low cost variant for imx6dl phycore Stefan Riedmueller
` (5 preceding siblings ...)
2019-07-02 12:37 ` [PATCH 7/8] ARM: dts: imx6ul: phycore: Add support for eMMC Stefan Riedmueller
@ 2019-07-02 12:37 ` Stefan Riedmueller
6 siblings, 0 replies; 12+ messages in thread
From: Stefan Riedmueller @ 2019-07-02 12:37 UTC (permalink / raw)
To: barebox
Add a phyCORE-i.MX 6ULL with eMMC. It has following features:
- i.MX 6ULL Y2 792 MHz
- 512 MB RAM
- 4 GB eMMC
- 10/100 MBits Ethernet
- USB OTG
- USB Host
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boards/phytec-som-imx6/lowlevel.c | 1 +
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts | 43 ++++++++++++++++++++++++
images/Makefile.imx | 5 +++
4 files changed, 51 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 494087ab1479..07bb0ed1b569 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -121,3 +121,4 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_
PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_nand_512mb, imx6ul_phytec_phycore_som_nand, SZ_512M, false);
PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_lc_nand_256mb, imx6ull_phytec_phycore_som_lc_nand, SZ_256M, false);
PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_nand_512mb, imx6ull_phytec_phycore_som_nand, SZ_512M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_emmc_512mb, imx6ull_phytec_phycore_som_emmc, SZ_512M, false);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c96f040ae311..87ddc57b899c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -68,7 +68,8 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \
imx6dl-phytec-phycore-som-lc-emmc.dtb.o \
imx6ul-phytec-phycore-som-nand.dtb.o \
imx6ull-phytec-phycore-som-lc-nand.dtb.o \
- imx6ull-phytec-phycore-som-nand.dtb.o
+ imx6ull-phytec-phycore-som-nand.dtb.o \
+ imx6ull-phytec-phycore-som-emmc.dtb.o
pbl-dtb-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o
pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += imx8mq-phytec-phycore-som.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts
new file mode 100644
index 000000000000..aa162cc42d07
--- /dev/null
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2019 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+/dts-v1/;
+
+#include <arm/imx6ull.dtsi>
+#include "imx6ul-phytec-phycore-som.dtsi"
+
+/ {
+ model = "PHYTEC phyCORE-i.MX6 ULL SOM with eMMC";
+ compatible = "phytec,imx6ul-pcl063-emmc", "fsl,imx6ull";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+};
+
+&usdhc2 {
+ status = "okay";
+};
+
+&usbotg1 {
+ status = "okay";
+};
+
+&usbotg2 {
+ status = "okay";
+};
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 8aedc906dc84..a287c11c4042 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -519,6 +519,11 @@ CFG_start_phytec_phycore_imx6ull_som_nand_512mb.pblb.imximg = $(board)/phytec-so
FILE_barebox-phytec-phycore-imx6ull-nand-512mb.img = start_phytec_phycore_imx6ull_som_nand_512mb.pblb.imximg
image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ull-nand-512mb.img
+pblb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6ull_som_emmc_512mb
+CFG_start_phytec_phycore_imx6ull_som_emmc_512mb.pblb.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcl063-512mb.imxcfg
+FILE_barebox-phytec-phycore-imx6ull-emmc-512mb.img = start_phytec_phycore_imx6ull_som_emmc_512mb.pblb.imximg
+image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ull-emmc-512mb.img
+
pblb-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += start_imx6ul_pico_hobbit_256mb
CFG_start_imx6ul_pico_hobbit_256mb.pblb.imximg = $(board)/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg
FILE_barebox-imx6ul-pico-hobbit-256mb.img = start_imx6ul_pico_hobbit_256mb.pblb.imximg
--
2.7.4
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/8] ARM: dts: imx6qdl: phycore: Add state framework
2019-07-09 8:53 [PATCH 2/8] ARM: dts: imx6qdl: phycore: Add state framework Roland Hieber
@ 2019-07-09 8:56 ` Roland Hieber
2019-07-09 9:20 ` Stefan Riedmüller
1 sibling, 0 replies; 12+ messages in thread
From: Roland Hieber @ 2019-07-09 8:56 UTC (permalink / raw)
To: Stefan Riedmueller, Daniel Schultz; +Cc: Barebox Mailing List
On Tue, Jul 09, 2019 at 10:53:39AM +0200, Roland Hieber wrote:
> <d.schultz@phytec.de>
> Cc: barebox@lists.infradead.org
> Bcc:
> Subject: Re: [PATCH 2/8] ARM: dts: imx6qdl: phycore: Add state framework
> Reply-To:
> In-Reply-To: <1562071065-367410-2-git-send-email-s.riedmueller@phytec.de>
> X-Sent-From: Pengutronix Hildesheim
> X-URL: http://www.pengutronix.de/
> X-IRC: #ptxdist @freenode
> X-Accept-Language: de,en
> X-Accept-Content-Type: text/plain
> X-Uptime: 10:41:58 up 1 day, 14:52, 50 users, load average: 0.08, 0.13, 0.10
Oops? Okay, apparently that happens when you don't indent the
receipients correctly in mutt... Please ignore :)
--
Roland Hieber | r.hieber@pengutronix.de |
Pengutronix e.K. | https://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim | Phone: +49-5121-206917-5086 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/8] ARM: dts: imx6qdl: phycore: Add state framework
2019-07-09 8:53 [PATCH 2/8] ARM: dts: imx6qdl: phycore: Add state framework Roland Hieber
2019-07-09 8:56 ` Roland Hieber
@ 2019-07-09 9:20 ` Stefan Riedmüller
1 sibling, 0 replies; 12+ messages in thread
From: Stefan Riedmüller @ 2019-07-09 9:20 UTC (permalink / raw)
To: Roland Hieber; +Cc: Barebox Mailing List, Daniel Schultz
Hi Roland,
On 09.07.19 10:53, Roland Hieber wrote:
> <d.schultz@phytec.de>
> Cc: barebox@lists.infradead.org
> Bcc:
> Subject: Re: [PATCH 2/8] ARM: dts: imx6qdl: phycore: Add state framework
> Reply-To:
> In-Reply-To: <1562071065-367410-2-git-send-email-s.riedmueller@phytec.de>
> X-Sent-From: Pengutronix Hildesheim
> X-URL: http://www.pengutronix.de/
> X-IRC: #ptxdist @freenode
> X-Accept-Language: de,en
> X-Accept-Content-Type: text/plain
> X-Uptime: 10:41:58 up 1 day, 14:52, 50 users, load average: 0.08, 0.13, 0.10
>
> Hi Stefan, Daniel,
>
> On Tue, Jul 02, 2019 at 02:37:39PM +0200, Stefan Riedmueller wrote:
>> From: Daniel Schultz <d.schultz@phytec.de>
>>
>> Add the state framework with EEPROM backend.
>>
>> Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
>> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
>> ---
>> arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts | 1 +
>> arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts | 1 +
>> arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts | 1 +
>> arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts | 1 +
>> arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts | 1 +
>> arch/arm/dts/imx6q-phytec-phycore-som-nand.dts | 1 +
>> arch/arm/dts/imx6qdl-phytec-state.dtsi | 81 ++++++++++++++++++++++
>> 7 files changed, 87 insertions(+)
>> create mode 100644 arch/arm/dts/imx6qdl-phytec-state.dtsi
>>
>> diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
>> index a04e37f80363..21cbb5f944c9 100644
>> --- a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
>> +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
>> @@ -15,6 +15,7 @@
>> #include <arm/imx6dl.dtsi>
>> #include "imx6dl.dtsi"
>> #include "imx6qdl-phytec-phycore-som.dtsi"
>> +#include "imx6qdl-phytec-state.dtsi"
>>
>> / {
>> model = "Phytec phyCORE-i.MX6 DualLite/SOLO with eMMC";
>> diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
>> index 5d9727ec5b80..b8efb95ee08a 100644
>> --- a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
>> +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts
>> @@ -9,6 +9,7 @@
>> #include <arm/imx6dl.dtsi>
>> #include "imx6dl.dtsi"
>> #include "imx6qdl-phytec-phycore-som.dtsi"
>> +#include "imx6qdl-phytec-state.dtsi"
>>
>> / {
>> model = "PHYTEC phyCORE-i.MX6 DualLite/SOLO with eMMC low-cost";
>> diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
>> index e119e4c0d4fc..4d38d1698a48 100644
>> --- a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
>> +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts
>> @@ -9,6 +9,7 @@
>> #include <arm/imx6dl.dtsi>
>> #include "imx6dl.dtsi"
>> #include "imx6qdl-phytec-phycore-som.dtsi"
>> +#include "imx6qdl-phytec-state.dtsi"
>>
>> / {
>> model = "PHYTEC phyCORE-i.MX6 Duallite/SOLO with NAND low-cost";
>> diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
>> index 287d876e41ed..3ad3723d2893 100644
>> --- a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
>> +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
>> @@ -14,6 +14,7 @@
>> #include <arm/imx6dl.dtsi>
>> #include "imx6dl.dtsi"
>> #include "imx6qdl-phytec-phycore-som.dtsi"
>> +#include "imx6qdl-phytec-state.dtsi"
>>
>> / {
>> model = "Phytec phyCORE-i.MX6 Duallite/SOLO with NAND";
>> diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
>> index 94a70389f084..7a86d5b94daf 100644
>> --- a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
>> +++ b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
>> @@ -14,6 +14,7 @@
>> #include <arm/imx6q.dtsi>
>> #include "imx6q.dtsi"
>> #include "imx6qdl-phytec-phycore-som.dtsi"
>> +#include "imx6qdl-phytec-state.dtsi"
>>
>> / {
>> model = "Phytec phyCORE-i.MX6 Quad with eMMC";
>> diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
>> index 6d82ec34d6e5..96d1de224c9e 100644
>> --- a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
>> +++ b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
>> @@ -14,6 +14,7 @@
>> #include <arm/imx6q.dtsi>
>> #include "imx6q.dtsi"
>> #include "imx6qdl-phytec-phycore-som.dtsi"
>> +#include "imx6qdl-phytec-state.dtsi"
>>
>> / {
>> model = "Phytec phyCORE-i.MX6 Quad with NAND";
>> diff --git a/arch/arm/dts/imx6qdl-phytec-state.dtsi b/arch/arm/dts/imx6qdl-phytec-state.dtsi
>> new file mode 100644
>> index 000000000000..76aa15f3e2f7
>> --- /dev/null
>> +++ b/arch/arm/dts/imx6qdl-phytec-state.dtsi
>> @@ -0,0 +1,81 @@
>> +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
>> +/*
>> + * Copyright (C) 2019 PHYTEC Messtechnik GmbH,
>> + * Author: Daniel Schultz <d.schultz@phytec.de>
>> + */
>> +
>> +/ {
>> + aliases {
>> + state = &state;
>> + };
>> +
>> + state: imx6qdl_phytec_boot_state {
>> + magic = <0x883b86a6>;
>> + compatible = "barebox,state";
>> + backend-type = "raw";
>> + backend = <&backend_update_eeprom>;
>> + backend-stridesize = <54>;
>
> In order to be compatible with previous (and possibly future?) userspace
> implementations, you should also set the backend-storage-type property.
> We had cases in the past where userspace and barebox defaulted to
> different storage types and could not understand each other.
>
> (For reference: https://www.barebox.org/doc/2019.06.0/user/state.html )
Thank you for the hint. I'll send a v2.
Stefan
>
> - Roland
>
>> +
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + bootstate {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + last_chosen {
>> + reg = <0x0 0x4>;
>> + type = "uint32";
>> + };
>> + system0 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + remaining_attempts {
>> + reg = <0x4 0x4>;
>> + type = "uint32";
>> + default = <3>;
>> + };
>> + priority {
>> + reg = <0x8 0x4>;
>> + type = "uint32";
>> + default = <21>;
>> + };
>> + ok {
>> + reg = <0xc 0x4>;
>> + type = "uint32";
>> + default = <0>;
>> + };
>> + };
>> + system1 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + remaining_attempts {
>> + reg = <0x10 0x4>;
>> + type = "uint32";
>> + default = <3>;
>> + };
>> + priority {
>> + reg = <0x14 0x4>;
>> + type = "uint32";
>> + default = <20>;
>> + };
>> + ok {
>> + reg = <0x18 0x4>;
>> + type = "uint32";
>> + default = <0>;
>> + };
>> + };
>> + };
>> + };
>> +};
>> +
>> +&eeprom {
>> + status = "okay";
>> + partitions {
>> + compatible = "fixed-partitions";
>> + #size-cells = <1>;
>> + #address-cells = <1>;
>> + backend_update_eeprom: state@0 {
>> + reg = <0x0 0x100>;
>> + label = "update-eeprom";
>> + };
>> + };
>> +};
>> --
>> 2.7.4
>>
>>
>> _______________________________________________
>> barebox mailing list
>> barebox@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/barebox
>>
>
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^ permalink raw reply [flat|nested] 12+ messages in thread