From: Sascha Hauer <s.hauer@pengutronix.de>
To: barebox@lists.infradead.org, Ahmad Fatoum <a.fatoum@pengutronix.de>
Cc: "Alvin Šipraga" <ALSI@bang-olufsen.dk>
Subject: Re: [PATCH] ddr: imx8m: fix broken sharing of DRAM timing with TF-A for DFS
Date: Fri, 03 May 2024 09:46:06 +0200 [thread overview]
Message-ID: <171472236610.36996.5200181315853367687.b4-ty@pengutronix.de> (raw)
In-Reply-To: <20240429141610.3556452-1-a.fatoum@pengutronix.de>
On Mon, 29 Apr 2024 16:16:10 +0200, Ahmad Fatoum wrote:
> To facilitate dynamic frequency scaling, barebox will place the DRAM
> parameters it has configured into a well-known location in DRAM
> for consumption by TF-A.
>
> This means that we need to be very picky about the struct layout for the
> data we write there to maintain ABI-compatibility. Unfortunately, NXP
> chose for the i.MX9 to add two fields into the middle, when it would
> have been possible to cleanly embed the i.MX8 DRAM timings in the
> i.MX9 DRAM timing struct. This is done now, so we need to arrange
> ourselves with it and ensure that the i.MX8M DRAM timings we share with
> TF-A don't have glimpses of the i.MX9 future.
>
> [...]
Applied, thanks!
[1/1] ddr: imx8m: fix broken sharing of DRAM timing with TF-A for DFS
https://git.pengutronix.de/cgit/barebox/commit/?id=ea580697c269 (link may not be stable)
Best regards,
--
Sascha Hauer <s.hauer@pengutronix.de>
prev parent reply other threads:[~2024-05-03 7:46 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-29 14:16 Ahmad Fatoum
2024-05-03 7:46 ` Sascha Hauer [this message]
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