From: Sascha Hauer <s.hauer@pengutronix.de>
To: BAREBOX <barebox@lists.infradead.org>,
Mathieu Anquetin via B4 Relay
<devnull+mathieu.anquetin.groupe-cahors.com@kernel.org>
Cc: Fabian Pflug <f.pflug@pengutronix.de>,
Jonas Rebmann <jre@pengutronix.de>,
Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
Subject: Re: [PATCH] ddr: imx9: fix DRAM PLL bypass
Date: Tue, 05 Aug 2025 11:14:46 +0200 [thread overview]
Message-ID: <175438528635.3506967.11568292814343312236.b4-ty@pengutronix.de> (raw)
In-Reply-To: <20250718-fix_imx9_ddr_init-v1-1-b52def9e7ee5@groupe-cahors.com>
On Fri, 18 Jul 2025 20:12:42 +0200, Mathieu Anquetin via B4 Relay wrote:
> On i.MX9, clock selection for DDR PHY is done by setting/clearing bit 0
> of GPR_SHARED2 register.
>
> This is done using the generic function ccm_shared_gpr_set() which takes
> two arguments, the GPR number and the value to set. However, this
> function did not use the GPR number to calculate the offset of the
> GPR_SHAREDn register to set in the CCM.
>
> [...]
Applied, thanks!
[1/1] ddr: imx9: fix DRAM PLL bypass
https://git.pengutronix.de/cgit/barebox/commit/?id=a10fb28638ab (link may not be stable)
Best regards,
--
Sascha Hauer <s.hauer@pengutronix.de>
prev parent reply other threads:[~2025-08-05 9:34 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-18 18:12 Mathieu Anquetin via B4 Relay
2025-07-31 8:40 ` ANQUETIN Mathieu
2025-07-31 9:02 ` Ahmad Fatoum
2025-08-05 9:14 ` Sascha Hauer [this message]
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