From mboxrd@z Thu Jan 1 00:00:00 1970 Delivery-date: Mon, 15 Dec 2025 09:44:23 +0100 Received: from metis.whiteo.stw.pengutronix.de ([2a0a:edc0:2:b01:1d::104]) by lore.white.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1vV4Br-00BgKV-1B for lore@lore.pengutronix.de; Mon, 15 Dec 2025 09:44:23 +0100 Received: from bombadil.infradead.org ([2607:7c80:54:3::133]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1vV4Bq-0002RO-RD for lore@pengutronix.de; Mon, 15 Dec 2025 09:44:23 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Date:Message-Id:Subject:References:In-Reply-To:To: From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=+a9CZT68M5mcj9eDYPxNnfjCKDgK/E153NwHnCeycR8=; b=hqUFPgU2b8KRqP8tlNymrPRPfH Ii/xU/zs5ahSq8ew5H0GnbSwDfmq12FA5/0ZzMExOLar35KQEByl813CctpcxsdGo7Q5sq0QCjqWQ SfHhrtu0fsOg9mX1w+Z2RLnQ5rbecl0Kk8i/X8gExllHv2k6lKT32yDAecDVLOCqKGBvJUi/sFADQ 47W/KlBajfyhFZidu9ria0G0DTH52ltBxmW9aFDIQ7ry7xCdeT0+cvy2YWkBCWMjO/jiyhSPzLzwE goeMwCQ3UW6NCdPoc9Bzn/eQ+2uyFboAkdbmI3cblOSoWrnBRPygGQsUjX/GsojmGh7sjPRrYPlHF 9F2NyxVQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vV4BP-00000003I4m-09MN; Mon, 15 Dec 2025 08:43:55 +0000 Received: from metis.whiteo.stw.pengutronix.de ([2a0a:edc0:2:b01:1d::104]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vV4BM-00000003I3z-47RS for barebox@lists.infradead.org; Mon, 15 Dec 2025 08:43:54 +0000 Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1vV4BL-0002JX-6A; Mon, 15 Dec 2025 09:43:51 +0100 Received: from dude02.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::28]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1vV4BL-005kbW-02; Mon, 15 Dec 2025 09:43:51 +0100 Received: from localhost ([::1] helo=dude02.red.stw.pengutronix.de) by dude02.red.stw.pengutronix.de with esmtp (Exim 4.98.2) (envelope-from ) id 1vV4BK-000000015dO-3yYQ; Mon, 15 Dec 2025 09:43:50 +0100 From: Sascha Hauer To: barebox@lists.infradead.org, Ahmad Fatoum In-Reply-To: <20251211204313.2613484-1-a.fatoum@pengutronix.de> References: <20251211204313.2613484-1-a.fatoum@pengutronix.de> Message-Id: <176578823094.259973.5136855121401220833.b4-ty@pengutronix.de> Date: Mon, 15 Dec 2025 09:43:50 +0100 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251215_004353_054263_887E070C X-CRM114-Status: UNSURE ( 8.17 ) X-CRM114-Notice: Please train this message. X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.0 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: [PATCH] ARM: cpu: disable interrupts before MMU disabling X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) On Thu, 11 Dec 2025 21:43:13 +0100, Ahmad Fatoum wrote: > The cache maintenance operations we do in mmu_disable() won't take > kindly to being interrupted by interrupt handlers if we have any. > > Thus disable them first thing and also move the #ifdef into the header > while at it. > > > [...] Applied, thanks! [1/1] ARM: cpu: disable interrupts before MMU disabling https://git.pengutronix.de/cgit/barebox/commit/?id=c811ba231875 (link may not be stable) Best regards, -- Sascha Hauer