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From: chalianis1@gmail.com
To: Sascha Hauer <s.hauer@pengutronix.de>
Cc: chalianis1@gmail.com, barebox@lists.infradead.org
Subject: Re: [PATCH] usb: dwc2: skip polling for the soft reset clear bit and add after reset delay
Date: Wed, 26 Aug 2026 13:54:50 +0200	[thread overview]
Message-ID: <178774529085.956898.8142660027039059393.b4-reply@b4> (raw)
In-Reply-To: <E1we9fW-00000005ggu-3u1v@pty.whiteo.stw.pengutronix.de>

On 2026-06-29 10:56 +0000, Sascha Hauer wrote:
> On 2026-06-23 10:23, chalianis1 wrote:
> > From: Chali Anis <chalianis1@gmail.com>
> > 
> > The RPi4 SoC do not deassert GRSTCTL_CSFTRST within the expected
> > window but continue to operate correctly, causing probe to fail
> > with ETIMEDOUT.
> 
> Does "within the expected window" imply that there is a bigger window in
> which it is de-asserted?
>
What I mean is within the expected window according to the SoC datasheet
of RK3588 which I just realized that I wrongly thought that it has a DWC2.
Rockchip RK3588 TRM V1.0-Part2 20220309 page 2221 
> > 
> > Per the datasheet, GRSTCTL_CSFTRST is self-clearing but requires at least
> > 3 PHY clocks after reset before any PHY domain access. Add a 1us delay to
> > satisfy this requirement.
> 
> Which datasheet, the SoC datasheet or a DWC2 datasheet?
>
the SOC one.
> I'm just asking if there is a chance to not need a SoC check here.
> 
> Sascha
> 
> > 
> > Signed-off-by: Chali Anis <chalianis1@gmail.com>
> > ---
> >  drivers/usb/dwc2/core.c | 13 +++++++++----
> >  1 file changed, 9 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
> > index 60cc690fdbc0..6d4b7930da9e 100644
> > --- a/drivers/usb/dwc2/core.c
> > +++ b/drivers/usb/dwc2/core.c
> > @@ -809,11 +809,16 @@ int dwc2_core_reset(struct dwc2 *dwc2)
> >  	greset |= GRSTCTL_CSFTRST;
> >  	dwc2_writel(dwc2, greset, GRSTCTL);
> >  
> > -	ret = dwc2_wait_bit_clear(dwc2, GRSTCTL, GRSTCTL_CSFTRST, 10000);
> > -	if (ret) {
> > -		dwc2_warn(dwc2, "%s: Timeout! Waiting for Core Soft Reset\n",
> > +	/* Wait for at least 3 PHY Clocks */
> > +	udelay(1);
> > +
> > +	if (!of_machine_is_compatible("brcm,bcm2711")) {
> > +		ret = dwc2_wait_bit_clear(dwc2, GRSTCTL, GRSTCTL_CSFTRST, 10000);
> > +		if (ret) {
> > +			dwc2_warn(dwc2, "%s: Timeout! Waiting for Core Soft Reset\n",
> >  				__func__);
> > -		return ret;
> > +			return ret;
> > +		}
> >  	}
> >  
> >  	if (wait_for_host_mode)
> > 
> 
> -- 
> Pengutronix e.K.                           |                             |
> Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
> 
> 
> 

Best regards.
Anis




  reply	other threads:[~2026-08-26 11:55 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-23 14:23 chalianis1
2026-06-29 10:56 ` Sascha Hauer
2026-08-26 11:54   ` chalianis1 [this message]
2026-08-26 12:12     ` chalianis1

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