* [PATCH v1] nvmem: bsec.c: add optional permanent write support
@ 2021-11-29 10:52 Oleksij Rempel
2021-11-29 11:07 ` Ahmad Fatoum
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Oleksij Rempel @ 2021-11-29 10:52 UTC (permalink / raw)
To: barebox; +Cc: Oleksij Rempel
To be able to fuze MAC address we need to be able to use BSEC_SMC_PROG_OTP
instead of BSEC_SMC_WRITE_SHADOW.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
---
drivers/nvmem/Kconfig | 11 +++++++++++
drivers/nvmem/bsec.c | 22 +++++++++++++++++++---
2 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index d809fb6eab..1bb477a997 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -66,6 +66,17 @@ config STM32_BSEC
This adds support for the STM32 OTP controller. Reads and writes
to will go to the shadow RAM, not the OTP fuses themselvers.
+config STM32_BSEC_WRITE
+ bool
+ prompt "Enable write support of STM32 CPUs OTP fuses"
+ depends on STM32_BSEC
+ help
+ This adds write support to STM32 On-Chip OTP registers. Example of set
+ MAC to 12:34:56:78:9A:BC:
+ bsec0.permanent_write_enable=1
+ mw -l -d /dev/stm32-bsec 0x000000e4+4 0x78563412
+ mw -l -d /dev/stm32-bsec 0x000000e8+4 0x0000bc9a
+
config STARFIVE_OTP
tristate "Starfive OTP Supprot"
depends on SOC_STARFIVE
diff --git a/drivers/nvmem/bsec.c b/drivers/nvmem/bsec.c
index 2d35d12df3..86b943a45d 100644
--- a/drivers/nvmem/bsec.c
+++ b/drivers/nvmem/bsec.c
@@ -21,8 +21,10 @@
#define BSEC_OTP_SERIAL 13
struct bsec_priv {
+ struct device_d dev;
u32 svc_id;
struct regmap_config map_config;
+ int permanent_write_enable;
};
struct stm32_bsec_data {
@@ -59,13 +61,18 @@ static int stm32_bsec_read_shadow(void *ctx, unsigned reg, unsigned *val)
return bsec_smc(ctx, BSEC_SMC_READ_SHADOW, reg, 0, val);
}
-static int stm32_bsec_reg_write_shadow(void *ctx, unsigned reg, unsigned val)
+static int stm32_bsec_reg_write(void *ctx, unsigned reg, unsigned val)
{
- return bsec_smc(ctx, BSEC_SMC_WRITE_SHADOW, reg, val, NULL);
+ struct bsec_priv *priv = ctx;
+
+ if (priv->permanent_write_enable)
+ return bsec_smc(ctx, BSEC_SMC_PROG_OTP, reg, val, NULL);
+ else
+ return bsec_smc(ctx, BSEC_SMC_WRITE_SHADOW, reg, val, NULL);
}
static struct regmap_bus stm32_bsec_regmap_bus = {
- .reg_write = stm32_bsec_reg_write_shadow,
+ .reg_write = stm32_bsec_reg_write,
.reg_read = stm32_bsec_read_shadow,
};
@@ -150,6 +157,10 @@ static int stm32_bsec_probe(struct device_d *dev)
priv->svc_id = data->svc_id;
+ dev_set_name(&priv->dev, "bsec");
+ priv->dev.parent = dev;
+ register_device(&priv->dev);
+
priv->map_config.reg_bits = 32;
priv->map_config.val_bits = 32;
priv->map_config.reg_stride = 4;
@@ -159,6 +170,11 @@ static int stm32_bsec_probe(struct device_d *dev)
if (IS_ERR(map))
return PTR_ERR(map);
+ if (IS_ENABLED(CONFIG_STM32_BSEC_WRITE)) {
+ dev_add_param_bool(&priv->dev, "permanent_write_enable",
+ NULL, NULL, &priv->permanent_write_enable, NULL);
+ }
+
nvmem = nvmem_regmap_register(map, "stm32-bsec");
if (IS_ERR(nvmem))
return PTR_ERR(nvmem);
--
2.30.2
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^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v1] nvmem: bsec.c: add optional permanent write support
2021-11-29 10:52 [PATCH v1] nvmem: bsec.c: add optional permanent write support Oleksij Rempel
@ 2021-11-29 11:07 ` Ahmad Fatoum
2021-11-29 11:10 ` [PATCH] fixup! " Ahmad Fatoum
2021-11-30 10:16 ` [PATCH v1] " Sascha Hauer
2 siblings, 0 replies; 4+ messages in thread
From: Ahmad Fatoum @ 2021-11-29 11:07 UTC (permalink / raw)
To: Oleksij Rempel, barebox
On 29.11.21 11:52, Oleksij Rempel wrote:
> To be able to fuze MAC address we need to be able to use BSEC_SMC_PROG_OTP
> instead of BSEC_SMC_WRITE_SHADOW.
>
> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
> ---
> drivers/nvmem/Kconfig | 11 +++++++++++
> drivers/nvmem/bsec.c | 22 +++++++++++++++++++---
> 2 files changed, 30 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
> index d809fb6eab..1bb477a997 100644
> --- a/drivers/nvmem/Kconfig
> +++ b/drivers/nvmem/Kconfig
> @@ -66,6 +66,17 @@ config STM32_BSEC
> This adds support for the STM32 OTP controller. Reads and writes
> to will go to the shadow RAM, not the OTP fuses themselvers.
>
> +config STM32_BSEC_WRITE
> + bool
> + prompt "Enable write support of STM32 CPUs OTP fuses"
> + depends on STM32_BSEC
> + help
> + This adds write support to STM32 On-Chip OTP registers. Example of set
> + MAC to 12:34:56:78:9A:BC:
> + bsec0.permanent_write_enable=1
> + mw -l -d /dev/stm32-bsec 0x000000e4+4 0x78563412
> + mw -l -d /dev/stm32-bsec 0x000000e8+4 0x0000bc9a
I'd have preferred the device parameter be associated with the
device instantiated from the device tree instead of allocating
a new device just to hold the param. Unfortunately, the existing device
has a '-' in the name, so the parameter can only be set with setenv..
I should've thought about that when I submitted the driver, but
as imx-ocotp/ocotp0 follows the same scheme:
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> +
> config STARFIVE_OTP
> tristate "Starfive OTP Supprot"
> depends on SOC_STARFIVE
> diff --git a/drivers/nvmem/bsec.c b/drivers/nvmem/bsec.c
> index 2d35d12df3..86b943a45d 100644
> --- a/drivers/nvmem/bsec.c
> +++ b/drivers/nvmem/bsec.c
> @@ -21,8 +21,10 @@
> #define BSEC_OTP_SERIAL 13
>
> struct bsec_priv {
> + struct device_d dev;
> u32 svc_id;
> struct regmap_config map_config;
> + int permanent_write_enable;
> };
>
> struct stm32_bsec_data {
> @@ -59,13 +61,18 @@ static int stm32_bsec_read_shadow(void *ctx, unsigned reg, unsigned *val)
> return bsec_smc(ctx, BSEC_SMC_READ_SHADOW, reg, 0, val);
> }
>
> -static int stm32_bsec_reg_write_shadow(void *ctx, unsigned reg, unsigned val)
> +static int stm32_bsec_reg_write(void *ctx, unsigned reg, unsigned val)
> {
> - return bsec_smc(ctx, BSEC_SMC_WRITE_SHADOW, reg, val, NULL);
> + struct bsec_priv *priv = ctx;
> +
> + if (priv->permanent_write_enable)
> + return bsec_smc(ctx, BSEC_SMC_PROG_OTP, reg, val, NULL);
> + else
> + return bsec_smc(ctx, BSEC_SMC_WRITE_SHADOW, reg, val, NULL);
> }
>
> static struct regmap_bus stm32_bsec_regmap_bus = {
> - .reg_write = stm32_bsec_reg_write_shadow,
> + .reg_write = stm32_bsec_reg_write,
> .reg_read = stm32_bsec_read_shadow,
> };
>
> @@ -150,6 +157,10 @@ static int stm32_bsec_probe(struct device_d *dev)
>
> priv->svc_id = data->svc_id;
>
> + dev_set_name(&priv->dev, "bsec");
> + priv->dev.parent = dev;
> + register_device(&priv->dev);
> +
> priv->map_config.reg_bits = 32;
> priv->map_config.val_bits = 32;
> priv->map_config.reg_stride = 4;
> @@ -159,6 +170,11 @@ static int stm32_bsec_probe(struct device_d *dev)
> if (IS_ERR(map))
> return PTR_ERR(map);
>
> + if (IS_ENABLED(CONFIG_STM32_BSEC_WRITE)) {
> + dev_add_param_bool(&priv->dev, "permanent_write_enable",
> + NULL, NULL, &priv->permanent_write_enable, NULL);
> + }
> +
> nvmem = nvmem_regmap_register(map, "stm32-bsec");
> if (IS_ERR(nvmem))
> return PTR_ERR(nvmem);
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH] fixup! nvmem: bsec.c: add optional permanent write support
2021-11-29 10:52 [PATCH v1] nvmem: bsec.c: add optional permanent write support Oleksij Rempel
2021-11-29 11:07 ` Ahmad Fatoum
@ 2021-11-29 11:10 ` Ahmad Fatoum
2021-11-30 10:16 ` [PATCH v1] " Sascha Hauer
2 siblings, 0 replies; 4+ messages in thread
From: Ahmad Fatoum @ 2021-11-29 11:10 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum
With Oleksij's patches, this no longer holds true. MAC is read from OTP
and a device parameter now controls whether write goes to OTP or shadow
RAM.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/nvmem/Kconfig | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 1bb477a9972f..7b1ebe1d689d 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -63,8 +63,7 @@ config STM32_BSEC
depends on ARCH_STM32MP
depends on OFDEVICE
help
- This adds support for the STM32 OTP controller. Reads and writes
- to will go to the shadow RAM, not the OTP fuses themselvers.
+ This adds support for the STM32 OTP controller.
config STM32_BSEC_WRITE
bool
--
2.30.2
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v1] nvmem: bsec.c: add optional permanent write support
2021-11-29 10:52 [PATCH v1] nvmem: bsec.c: add optional permanent write support Oleksij Rempel
2021-11-29 11:07 ` Ahmad Fatoum
2021-11-29 11:10 ` [PATCH] fixup! " Ahmad Fatoum
@ 2021-11-30 10:16 ` Sascha Hauer
2 siblings, 0 replies; 4+ messages in thread
From: Sascha Hauer @ 2021-11-30 10:16 UTC (permalink / raw)
To: Oleksij Rempel; +Cc: barebox
On Mon, Nov 29, 2021 at 11:52:44AM +0100, Oleksij Rempel wrote:
> To be able to fuze MAC address we need to be able to use BSEC_SMC_PROG_OTP
> instead of BSEC_SMC_WRITE_SHADOW.
>
> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
> ---
> drivers/nvmem/Kconfig | 11 +++++++++++
> drivers/nvmem/bsec.c | 22 +++++++++++++++++++---
> 2 files changed, 30 insertions(+), 3 deletions(-)
Applied, thanks
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 4+ messages in thread
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2021-11-29 10:52 [PATCH v1] nvmem: bsec.c: add optional permanent write support Oleksij Rempel
2021-11-29 11:07 ` Ahmad Fatoum
2021-11-29 11:10 ` [PATCH] fixup! " Ahmad Fatoum
2021-11-30 10:16 ` [PATCH v1] " Sascha Hauer
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