From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: Rouven Czerwinski <rcz@pengutronix.de>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH] ARM: aarch64: save clobbered registers in __barebox_arm_entry
Date: Wed, 2 Oct 2019 12:45:59 +0200 [thread overview]
Message-ID: <1d85b1ca-bc84-f64c-03ff-68710a998109@pengutronix.de> (raw)
In-Reply-To: <6673f557f1dc626e64c2514bf9bb93cd2c790a5e.camel@pengutronix.de>
On 10/2/19 11:30 AM, Rouven Czerwinski wrote:
> On Wed, 2019-10-02 at 09:57 +0200, Ahmad Fatoum wrote:
>> arm_early_mmu_cache_invalidate now clobbers x0, x1, x2, which might
>> be
>> passed by a previous stage bootloader. Have the caller save them.
>> ---
>> Rouven, does this work for you?
>
> No, this does not fix the issue. I'll take some time to look into this
> at a later point.
Hmm, could you tell me a bit about how the i.MX8 boots?
At what stage does it break? barebox PBL? barebox proper?
Is there something running prior to the barebox PBL?
Is the MMU off when barebox is run?
>
> - rcz
>
>
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prev parent reply other threads:[~2019-10-02 10:46 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-01 9:09 [PATCH 1/2] ARM: cache_64: invalidate icache in arm_early_mmu_cache_flush Ahmad Fatoum
2019-10-01 9:09 ` [PATCH 2/2] ARM: cache_64: invalidate dcache in arm_early_mmu_cache_invalidate Ahmad Fatoum
2019-10-01 9:15 ` Ahmad Fatoum
2019-10-02 7:38 ` [PATCH 1/2] ARM: cache_64: invalidate icache in arm_early_mmu_cache_flush Rouven Czerwinski
2019-10-02 7:43 ` Ahmad Fatoum
2019-10-02 7:46 ` Rouven Czerwinski
2019-10-02 7:57 ` [PATCH] ARM: aarch64: save clobbered registers in __barebox_arm_entry Ahmad Fatoum
2019-10-02 9:30 ` Rouven Czerwinski
2019-10-02 10:45 ` Ahmad Fatoum [this message]
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