* [PATCH] ddr: imx9: fix DRAM PLL bypass
@ 2025-07-18 18:12 Mathieu Anquetin via B4 Relay
2025-07-31 8:40 ` ANQUETIN Mathieu
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Mathieu Anquetin via B4 Relay @ 2025-07-18 18:12 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: Fabian Pflug, Jonas Rebmann, Mathieu Anquetin
From: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
On i.MX9, clock selection for DDR PHY is done by setting/clearing bit 0
of GPR_SHARED2 register.
This is done using the generic function ccm_shared_gpr_set() which takes
two arguments, the GPR number and the value to set. However, this
function did not use the GPR number to calculate the offset of the
GPR_SHAREDn register to set in the CCM.
Therefore, it was not possible to enable/disable DRAM PLL bypass
correctly and this led to hangs when training the DDR PHY with some
frequencies (like 625MT/s).
Fixes: e6234f907416 ("ddr: Initial i.MX9 support")
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
---
Some DRAM timing configurations require to change the input clock signal
and to bypass the DRAM PLL. This is done by setting bit 0 of the
GPR_SHARED2 register of the CLock Controller Module. However, the
register offset to set was not calculated correctly, leading to hangs
during PHY training when PLL bypass was required.
In particular, this was the case for the configuration setting the FSP
to 625MT/s.
---
drivers/ddr/imx/imx9_ddr_init.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/imx/imx9_ddr_init.c b/drivers/ddr/imx/imx9_ddr_init.c
index cdee18e4ad0e4cee1b13bd2aab4b53ffcb537e49..086827d9b34c49a76426289b707aad6fa474d065 100644
--- a/drivers/ddr/imx/imx9_ddr_init.c
+++ b/drivers/ddr/imx/imx9_ddr_init.c
@@ -352,6 +352,8 @@ static void save_trained_mr12_14(struct dram_cfg_param *cfg, u32 cfg_num, u32 mr
#define MHZ(x) ((x) * 1000000UL)
+#define SHARED_GPR(n) (0x4800 + ((n) * 0x20))
+
#define SHARED_GPR_DRAM_CLK 2
#define SHARED_GPR_DRAM_CLK_SEL_PLL 0
#define SHARED_GPR_DRAM_CLK_SEL_CCM BIT(0)
@@ -376,7 +378,7 @@ static int dram_pll_init(u32 freq)
static void ccm_shared_gpr_set(u32 gpr, u32 val)
{
- writel(val, IOMEM(MX9_CCM_BASE_ADDR + 0x4800));
+ writel(val, IOMEM(MX9_CCM_BASE_ADDR + SHARED_GPR(gpr)));
}
#define DRAM_ALT_CLK_ROOT 76
---
base-commit: f49c873d7ec78a2df7bd3c7a86f5372fb1666517
change-id: 20250718-fix_imx9_ddr_init-6ccf9db195be
Best regards,
--
*Mathieu ANQUETIN*
/Software Developer/
CRDE -- Groupe Cahors | http://www.groupe-cahors.com
ZI des Grands Camps | Phone: +33 (0)5 65 30 38 77
46090 Mercuès -- France |
*GROUPE CAHORS* is a member of the UN Global Compact.
^ permalink raw reply [flat|nested] 4+ messages in thread* RE: [PATCH] ddr: imx9: fix DRAM PLL bypass
2025-07-18 18:12 [PATCH] ddr: imx9: fix DRAM PLL bypass Mathieu Anquetin via B4 Relay
@ 2025-07-31 8:40 ` ANQUETIN Mathieu
2025-07-31 9:02 ` Ahmad Fatoum
2025-08-05 9:14 ` Sascha Hauer
2 siblings, 0 replies; 4+ messages in thread
From: ANQUETIN Mathieu @ 2025-07-31 8:40 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX, ANQUETIN Mathieu; +Cc: Fabian Pflug, Jonas Rebmann
Friendly ping!
Cordialement / Best regards,
--
*Mathieu ANQUETIN*
/Software Developer/
CRDE -- Groupe Cahors | http://www.groupe-cahors.com
ZI des Grands Camps | Phone: +33 (0)5 65 30 38 77
46090 Mercuès -- France |
*GROUPE CAHORS* is a member of the UN Global Compact.
________________________________________
De : Mathieu Anquetin via B4 Relay <devnull+mathieu.anquetin.groupe-cahors.com@kernel.org>
Envoyé : vendredi 18 juillet 2025 20:12
À : Sascha Hauer; BAREBOX
Cc : Fabian Pflug; Jonas Rebmann; ANQUETIN Mathieu
Objet : [PATCH] ddr: imx9: fix DRAM PLL bypass
From: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
On i.MX9, clock selection for DDR PHY is done by setting/clearing bit 0
of GPR_SHARED2 register.
This is done using the generic function ccm_shared_gpr_set() which takes
two arguments, the GPR number and the value to set. However, this
function did not use the GPR number to calculate the offset of the
GPR_SHAREDn register to set in the CCM.
Therefore, it was not possible to enable/disable DRAM PLL bypass
correctly and this led to hangs when training the DDR PHY with some
frequencies (like 625MT/s).
Fixes: e6234f907416 ("ddr: Initial i.MX9 support")
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
---
Some DRAM timing configurations require to change the input clock signal
and to bypass the DRAM PLL. This is done by setting bit 0 of the
GPR_SHARED2 register of the CLock Controller Module. However, the
register offset to set was not calculated correctly, leading to hangs
during PHY training when PLL bypass was required.
In particular, this was the case for the configuration setting the FSP
to 625MT/s.
---
drivers/ddr/imx/imx9_ddr_init.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/imx/imx9_ddr_init.c b/drivers/ddr/imx/imx9_ddr_init.c
index cdee18e4ad0e4cee1b13bd2aab4b53ffcb537e49..086827d9b34c49a76426289b707aad6fa474d065 100644
--- a/drivers/ddr/imx/imx9_ddr_init.c
+++ b/drivers/ddr/imx/imx9_ddr_init.c
@@ -352,6 +352,8 @@ static void save_trained_mr12_14(struct dram_cfg_param *cfg, u32 cfg_num, u32 mr
#define MHZ(x) ((x) * 1000000UL)
+#define SHARED_GPR(n) (0x4800 + ((n) * 0x20))
+
#define SHARED_GPR_DRAM_CLK 2
#define SHARED_GPR_DRAM_CLK_SEL_PLL 0
#define SHARED_GPR_DRAM_CLK_SEL_CCM BIT(0)
@@ -376,7 +378,7 @@ static int dram_pll_init(u32 freq)
static void ccm_shared_gpr_set(u32 gpr, u32 val)
{
- writel(val, IOMEM(MX9_CCM_BASE_ADDR + 0x4800));
+ writel(val, IOMEM(MX9_CCM_BASE_ADDR + SHARED_GPR(gpr)));
}
#define DRAM_ALT_CLK_ROOT 76
---
base-commit: f49c873d7ec78a2df7bd3c7a86f5372fb1666517
change-id: 20250718-fix_imx9_ddr_init-6ccf9db195be
Best regards,
--
*Mathieu ANQUETIN*
/Software Developer/
CRDE -- Groupe Cahors | http://www.groupe-cahors.com
ZI des Grands Camps | Phone: +33 (0)5 65 30 38 77
46090 Mercuès -- France |
*GROUPE CAHORS* is a member of the UN Global Compact.
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] ddr: imx9: fix DRAM PLL bypass
2025-07-18 18:12 [PATCH] ddr: imx9: fix DRAM PLL bypass Mathieu Anquetin via B4 Relay
2025-07-31 8:40 ` ANQUETIN Mathieu
@ 2025-07-31 9:02 ` Ahmad Fatoum
2025-08-05 9:14 ` Sascha Hauer
2 siblings, 0 replies; 4+ messages in thread
From: Ahmad Fatoum @ 2025-07-31 9:02 UTC (permalink / raw)
To: mathieu.anquetin, Sascha Hauer, BAREBOX; +Cc: Fabian Pflug, Jonas Rebmann
Hi Mathieu,
Thanks for your patch
On 7/18/25 20:12, Mathieu Anquetin via B4 Relay wrote:
> From: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
>
> On i.MX9, clock selection for DDR PHY is done by setting/clearing bit 0
> of GPR_SHARED2 register.
>
> This is done using the generic function ccm_shared_gpr_set() which takes
> two arguments, the GPR number and the value to set. However, this
> function did not use the GPR number to calculate the offset of the
> GPR_SHAREDn register to set in the CCM.
>
> Therefore, it was not possible to enable/disable DRAM PLL bypass
> correctly and this led to hangs when training the DDR PHY with some
> frequencies (like 625MT/s).
>
> Fixes: e6234f907416 ("ddr: Initial i.MX9 support")
> Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Sascha is on vacation this month, but I assume he can pick this for the
next release.
Cheers,
Ahmad
> ---
> Some DRAM timing configurations require to change the input clock signal
> and to bypass the DRAM PLL. This is done by setting bit 0 of the
> GPR_SHARED2 register of the CLock Controller Module. However, the
> register offset to set was not calculated correctly, leading to hangs
> during PHY training when PLL bypass was required.
>
> In particular, this was the case for the configuration setting the FSP
> to 625MT/s.
> ---
> drivers/ddr/imx/imx9_ddr_init.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/ddr/imx/imx9_ddr_init.c b/drivers/ddr/imx/imx9_ddr_init.c
> index cdee18e4ad0e4cee1b13bd2aab4b53ffcb537e49..086827d9b34c49a76426289b707aad6fa474d065 100644
> --- a/drivers/ddr/imx/imx9_ddr_init.c
> +++ b/drivers/ddr/imx/imx9_ddr_init.c
> @@ -352,6 +352,8 @@ static void save_trained_mr12_14(struct dram_cfg_param *cfg, u32 cfg_num, u32 mr
>
> #define MHZ(x) ((x) * 1000000UL)
>
> +#define SHARED_GPR(n) (0x4800 + ((n) * 0x20))
> +
> #define SHARED_GPR_DRAM_CLK 2
> #define SHARED_GPR_DRAM_CLK_SEL_PLL 0
> #define SHARED_GPR_DRAM_CLK_SEL_CCM BIT(0)
> @@ -376,7 +378,7 @@ static int dram_pll_init(u32 freq)
>
> static void ccm_shared_gpr_set(u32 gpr, u32 val)
> {
> - writel(val, IOMEM(MX9_CCM_BASE_ADDR + 0x4800));
> + writel(val, IOMEM(MX9_CCM_BASE_ADDR + SHARED_GPR(gpr)));
> }
>
> #define DRAM_ALT_CLK_ROOT 76
>
> ---
> base-commit: f49c873d7ec78a2df7bd3c7a86f5372fb1666517
> change-id: 20250718-fix_imx9_ddr_init-6ccf9db195be
>
> Best regards,
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] ddr: imx9: fix DRAM PLL bypass
2025-07-18 18:12 [PATCH] ddr: imx9: fix DRAM PLL bypass Mathieu Anquetin via B4 Relay
2025-07-31 8:40 ` ANQUETIN Mathieu
2025-07-31 9:02 ` Ahmad Fatoum
@ 2025-08-05 9:14 ` Sascha Hauer
2 siblings, 0 replies; 4+ messages in thread
From: Sascha Hauer @ 2025-08-05 9:14 UTC (permalink / raw)
To: BAREBOX, Mathieu Anquetin via B4 Relay
Cc: Fabian Pflug, Jonas Rebmann, Mathieu Anquetin
On Fri, 18 Jul 2025 20:12:42 +0200, Mathieu Anquetin via B4 Relay wrote:
> On i.MX9, clock selection for DDR PHY is done by setting/clearing bit 0
> of GPR_SHARED2 register.
>
> This is done using the generic function ccm_shared_gpr_set() which takes
> two arguments, the GPR number and the value to set. However, this
> function did not use the GPR number to calculate the offset of the
> GPR_SHAREDn register to set in the CCM.
>
> [...]
Applied, thanks!
[1/1] ddr: imx9: fix DRAM PLL bypass
https://git.pengutronix.de/cgit/barebox/commit/?id=a10fb28638ab (link may not be stable)
Best regards,
--
Sascha Hauer <s.hauer@pengutronix.de>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2025-07-18 18:12 [PATCH] ddr: imx9: fix DRAM PLL bypass Mathieu Anquetin via B4 Relay
2025-07-31 8:40 ` ANQUETIN Mathieu
2025-07-31 9:02 ` Ahmad Fatoum
2025-08-05 9:14 ` Sascha Hauer
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