* [PATCH 1/2] imx_spi: rework transfer according to the API, fix compatibility with spi_write_then_read() @ 2011-08-30 6:20 Paul Fertser 2011-08-30 6:30 ` [PATCH 2/2] imx25: imx_spi: support CSPI v0.7 as found on i.MX25 Paul Fertser 2011-09-12 10:20 ` [PATCH 1/2] imx_spi: rework transfer according to the API, fix compatibility with spi_write_then_read() Sascha Hauer 0 siblings, 2 replies; 5+ messages in thread From: Paul Fertser @ 2011-08-30 6:20 UTC (permalink / raw) To: barebox This code was tested barely with m25p80 driver, reading jedec id and some data from the chip worked fine. Signed-off-by: Paul Fertser <fercerpav@gmail.com> --- drivers/spi/imx_spi.c | 55 +++++++++++++++++++++++++++++++++++++++--------- 1 files changed, 44 insertions(+), 11 deletions(-) diff --git a/drivers/spi/imx_spi.c b/drivers/spi/imx_spi.c index 6dc41b9..0d21fb3 100644 --- a/drivers/spi/imx_spi.c +++ b/drivers/spi/imx_spi.c @@ -310,23 +310,56 @@ static void cspi_2_3_init(struct imx_spi *imx) } #endif +static void imx_spi_do_transfer(struct spi_device *spi, struct spi_transfer *t) +{ + struct imx_spi *imx = container_of(spi->master, struct imx_spi, master); + unsigned i; + + if (spi->bits_per_word <= 8) { + const u8 *tx_buf = t->tx_buf; + u8 *rx_buf = t->rx_buf; + u8 rx_val; + + for (i = 0; i < t->len; i++) { + rx_val = imx->xchg_single(imx, tx_buf ? tx_buf[i] : 0); + if (rx_buf) + rx_buf[i] = rx_val; + } + } else if (spi->bits_per_word <= 16) { + const u16 *tx_buf = t->tx_buf; + u16 *rx_buf = t->rx_buf; + u16 rx_val; + + for (i = 0; i < t->len >> 1; i++) { + rx_val = imx->xchg_single(imx, tx_buf ? tx_buf[i] : 0); + if (rx_buf) + rx_buf[i] = rx_val; + } + } else if (spi->bits_per_word <= 32) { + const u32 *tx_buf = t->tx_buf; + u32 *rx_buf = t->rx_buf; + u32 rx_val; + + for (i = 0; i < t->len >> 2; i++) { + rx_val = imx->xchg_single(imx, tx_buf ? tx_buf[i] : 0); + if (rx_buf) + rx_buf[i] = rx_val; + } + } +} + static int imx_spi_transfer(struct spi_device *spi, struct spi_message *mesg) { - struct spi_master *master = spi->master; - struct imx_spi *imx = container_of(master, struct imx_spi, master); - struct spi_transfer *t = NULL; + struct imx_spi *imx = container_of(spi->master, struct imx_spi, master); + struct spi_transfer *t = NULL; imx->chipselect(spi, 1); - list_for_each_entry (t, &mesg->transfers, transfer_list) { - const u32 *txbuf = t->tx_buf; - u32 *rxbuf = t->rx_buf; - int i = 0; + mesg->actual_length = 0; - while(i < t->len >> 2) { - rxbuf[i] = imx->xchg_single(imx, txbuf[i]); - i++; - } + list_for_each_entry(t, &mesg->transfers, transfer_list) { + imx_spi_do_transfer(spi, t); + mesg->actual_length += t->len; } imx->chipselect(spi, 0); -- 1.5.2.2 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] imx25: imx_spi: support CSPI v0.7 as found on i.MX25 2011-08-30 6:20 [PATCH 1/2] imx_spi: rework transfer according to the API, fix compatibility with spi_write_then_read() Paul Fertser @ 2011-08-30 6:30 ` Paul Fertser 2011-09-12 10:21 ` Sascha Hauer 2011-09-12 10:20 ` [PATCH 1/2] imx_spi: rework transfer according to the API, fix compatibility with spi_write_then_read() Sascha Hauer 1 sibling, 1 reply; 5+ messages in thread From: Paul Fertser @ 2011-08-30 6:30 UTC (permalink / raw) To: barebox Based on the Linux driver. Barely tested with m25p80 with CS in GPIO mode. Currently always using the slowest speed. Signed-off-by: Paul Fertser <fercerpav@gmail.com> --- arch/arm/mach-imx/include/mach/devices-imx25.h | 5 + arch/arm/mach-imx/include/mach/imx25-regs.h | 1 + drivers/spi/Kconfig | 5 + drivers/spi/imx_spi.c | 115 ++++++++++++++++++++++++ 4 files changed, 126 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-imx/include/mach/devices-imx25.h b/arch/arm/mach-imx/include/mach/devices-imx25.h index 87f5ba0..eff5977 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx25.h +++ b/arch/arm/mach-imx/include/mach/devices-imx25.h @@ -6,6 +6,11 @@ static inline struct device_d *imx25_add_i2c0(struct i2c_platform_data *pdata) return imx_add_i2c((void *)IMX_I2C1_BASE, 0, pdata); } +static inline struct device_d *imx25_add_spi0(struct spi_imx_master *pdata) +{ + return imx_add_spi((void *)IMX_CSPI1_BASE, 0, pdata); +} + static inline struct device_d *imx25_add_uart0(void) { return imx_add_uart((void *)IMX_UART1_BASE, 0); diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h index 78ec0cd..73307c4 100644 --- a/arch/arm/mach-imx/include/mach/imx25-regs.h +++ b/arch/arm/mach-imx/include/mach/imx25-regs.h @@ -47,6 +47,7 @@ #define IMX_NFC_BASE 0xBB000000 #define IMX_FEC_BASE 0x50038000 #define IMX_I2C1_BASE 0x43F80000 +#define IMX_CSPI1_BASE 0x43FA4000 /* * Clock Controller Module (CCM) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index c72493c..94470fe 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -14,6 +14,11 @@ config DRIVER_SPI_IMX_0_0 depends on ARCH_IMX27 default y +config DRIVER_SPI_IMX_0_7 + bool + depends on ARCH_IMX25 + default y + config DRIVER_SPI_IMX_2_3 bool depends on ARCH_IMX51 || ARCH_IMX53 diff --git a/drivers/spi/imx_spi.c b/drivers/spi/imx_spi.c index 0d21fb3..3050efc 100644 --- a/drivers/spi/imx_spi.c +++ b/drivers/spi/imx_spi.c @@ -65,6 +65,22 @@ #define CSPI_0_0_TEST_LBC (1 << 14) +#define CSPI_0_7_RXDATA 0x00 +#define CSPI_0_7_TXDATA 0x04 +#define CSPI_0_7_CTRL 0x08 +#define CSPI_0_7_CTRL_ENABLE (1 << 0) +#define CSPI_0_7_CTRL_MASTER (1 << 1) +#define CSPI_0_7_CTRL_XCH (1 << 2) +#define CSPI_0_7_CTRL_POL (1 << 4) +#define CSPI_0_7_CTRL_PHA (1 << 5) +#define CSPI_0_7_CTRL_SSCTL (1 << 6) +#define CSPI_0_7_CTRL_SSPOL (1 << 7) +#define CSPI_0_7_CTRL_CS_SHIFT 12 +#define CSPI_0_7_CTRL_DR_SHIFT 16 +#define CSPI_0_7_CTRL_BL_SHIFT 20 +#define CSPI_0_7_STAT 0x14 +#define CSPI_0_7_STAT_RR (1 << 3) + #define CSPI_2_3_RXDATA 0x00 #define CSPI_2_3_TXDATA 0x04 #define CSPI_2_3_CTRL 0x08 @@ -206,6 +222,94 @@ static void cspi_0_0_init(struct imx_spi *imx) } #endif +#ifdef CONFIG_DRIVER_SPI_IMX_0_7 +static unsigned int cspi_0_7_xchg_single(struct imx_spi *imx, unsigned int data) +{ + void __iomem *base = imx->regs; + + unsigned int cfg_reg = readl(base + CSPI_0_7_CTRL); + + writel(data, base + CSPI_0_7_TXDATA); + + cfg_reg |= CSPI_0_7_CTRL_XCH; + + writel(cfg_reg, base + CSPI_0_7_CTRL); + + while (!(readl(base + CSPI_0_7_STAT) & CSPI_0_7_STAT_RR)) + ; + + return readl(base + CSPI_0_7_RXDATA); +} + +#if 0 +/* MX1, MX31, MX35, MX51 CSPI */ +static unsigned int spi_imx_clkdiv_2(unsigned int fin, + unsigned int fspi) +{ + int i, div = 4; + + for (i = 0; i < 7; i++) { + if (fspi * div >= fin) + return i; + div <<= 1; + } + + return 7; +} +#endif + +static void cspi_0_7_chipselect(struct spi_device *spi, int is_active) +{ + struct spi_master *master = spi->master; + struct imx_spi *imx = container_of(master, struct imx_spi, master); + void __iomem *base = imx->regs; + unsigned int cs = 0; + int gpio = imx->cs_array[spi->chip_select]; + unsigned int reg = CSPI_0_7_CTRL_ENABLE | CSPI_0_7_CTRL_MASTER; + + if (spi->mode & SPI_CS_HIGH) + cs = 1; + + if (!is_active) { + if (gpio >= 0) + gpio_set_value(gpio, !cs); + return; + } + +#if 0 + reg |= spi_imx_clkdiv_2(166000000, spi->max_speed_hz) << + CSPI_0_7_CTRL_DR_SHIFT; +#endif + reg |= 7 << CSPI_0_7_CTRL_DR_SHIFT; /* slowest speed */ + + reg |= (spi->bits_per_word - 1) << CSPI_0_7_CTRL_BL_SHIFT; + reg |= CSPI_0_7_CTRL_SSCTL; + + if (spi->mode & SPI_CPHA) + reg |= CSPI_0_7_CTRL_PHA; + if (spi->mode & SPI_CPOL) + reg |= CSPI_0_7_CTRL_POL; + if (spi->mode & SPI_CS_HIGH) + reg |= CSPI_0_7_CTRL_SSPOL; + if (gpio < 0) + reg |= (gpio + 32) << CSPI_0_7_CTRL_CS_SHIFT; + + writel(reg, base + CSPI_0_7_CTRL); + + if (gpio >= 0) + gpio_set_value(gpio, cs); +} + +static void cspi_0_7_init(struct imx_spi *imx) +{ + void __iomem *base = imx->regs; + + /* drain receive buffer */ + while (readl(base + CSPI_0_7_STAT) & CSPI_0_7_STAT_RR) + readl(base + CSPI_0_7_RXDATA); +} +#endif + #ifdef CONFIG_DRIVER_SPI_IMX_2_3 static unsigned int cspi_2_3_xchg_single(struct imx_spi *imx, unsigned int data) { @@ -375,6 +479,13 @@ static struct spi_imx_devtype_data spi_imx_devtype_data[] = { .init = cspi_0_0_init, }, #endif +#ifdef CONFIG_DRIVER_SPI_IMX_0_7 + [SPI_IMX_VER_0_7] = { + .chipselect = cspi_0_7_chipselect, + .xchg_single = cspi_0_7_xchg_single, + .init = cspi_0_7_init, + }, +#endif #ifdef CONFIG_DRIVER_SPI_IMX_2_3 [SPI_IMX_VER_2_3] = { .chipselect = cspi_2_3_chipselect, @@ -405,6 +516,10 @@ static int imx_spi_probe(struct device_d *dev) if (cpu_is_mx27()) version = SPI_IMX_VER_0_0; #endif +#ifdef CONFIG_DRIVER_SPI_IMX_0_7 + if (cpu_is_mx25()) + version = SPI_IMX_VER_0_7; +#endif #ifdef CONFIG_DRIVER_SPI_IMX_2_3 if (cpu_is_mx51() || cpu_is_mx53()) version = SPI_IMX_VER_2_3; -- 1.5.2.2 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] imx25: imx_spi: support CSPI v0.7 as found on i.MX25 2011-08-30 6:30 ` [PATCH 2/2] imx25: imx_spi: support CSPI v0.7 as found on i.MX25 Paul Fertser @ 2011-09-12 10:21 ` Sascha Hauer 2011-08-30 6:30 ` [PATCH] " Paul Fertser 0 siblings, 1 reply; 5+ messages in thread From: Sascha Hauer @ 2011-09-12 10:21 UTC (permalink / raw) To: Paul Fertser; +Cc: barebox On Tue, Aug 30, 2011 at 10:30:51AM +0400, Paul Fertser wrote: > + > +#if 0 > +/* MX1, MX31, MX35, MX51 CSPI */ > +static unsigned int spi_imx_clkdiv_2(unsigned int fin, > + unsigned int fspi) > +{ > + int i, div = 4; > + > + for (i = 0; i < 7; i++) { > + if (fspi * div >= fin) > + return i; > + div <<= 1; > + } > + > + return 7; > +} > +#endif > + > +static void cspi_0_7_chipselect(struct spi_device *spi, int is_active) > +{ > + struct spi_master *master = spi->master; > + struct imx_spi *imx = container_of(master, struct imx_spi, master); > + void __iomem *base = imx->regs; > + unsigned int cs = 0; > + int gpio = imx->cs_array[spi->chip_select]; > + unsigned int reg = CSPI_0_7_CTRL_ENABLE | CSPI_0_7_CTRL_MASTER; > + > + if (spi->mode & SPI_CS_HIGH) > + cs = 1; > + > + if (!is_active) { > + if (gpio >= 0) > + gpio_set_value(gpio, !cs); > + return; > + } > + > +#if 0 > + reg |= spi_imx_clkdiv_2(166000000, spi->max_speed_hz) << > + CSPI_0_7_CTRL_DR_SHIFT; > +#endif > + reg |= 7 << CSPI_0_7_CTRL_DR_SHIFT; /* slowest speed */ Can we fix this before merging it? Are there any problems with faster speeds? Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] imx25: imx_spi: support CSPI v0.7 as found on i.MX25 2011-09-12 10:21 ` Sascha Hauer @ 2011-08-30 6:30 ` Paul Fertser 0 siblings, 0 replies; 5+ messages in thread From: Paul Fertser @ 2011-08-30 6:30 UTC (permalink / raw) To: barebox Based on the Linux driver. Tested with m25p80 with CS in GPIO mode. Clock setting support is ad-hoc as the corresponding mach is not using the generic clock infrastructure. Signed-off-by: Paul Fertser <fercerpav@gmail.com> --- arch/arm/mach-imx/include/mach/clock.h | 1 + arch/arm/mach-imx/include/mach/devices-imx25.h | 5 + arch/arm/mach-imx/include/mach/imx25-regs.h | 1 + arch/arm/mach-imx/speed-imx25.c | 5 + drivers/spi/Kconfig | 5 + drivers/spi/imx_spi.c | 111 ++++++++++++++++++++++++ 6 files changed, 128 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-imx/include/mach/clock.h b/arch/arm/mach-imx/include/mach/clock.h index 5b590a2..1082178 100644 --- a/arch/arm/mach-imx/include/mach/clock.h +++ b/arch/arm/mach-imx/include/mach/clock.h @@ -29,6 +29,7 @@ ulong imx_get_uartclk(void); ulong imx_get_lcdclk(void); ulong imx_get_i2cclk(void); ulong imx_get_mmcclk(void); +ulong imx_get_cspiclk(void); int imx_clko_set_div(int div); void imx_clko_set_src(int src); diff --git a/arch/arm/mach-imx/include/mach/devices-imx25.h b/arch/arm/mach-imx/include/mach/devices-imx25.h index 87f5ba0..eff5977 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx25.h +++ b/arch/arm/mach-imx/include/mach/devices-imx25.h @@ -6,6 +6,11 @@ static inline struct device_d *imx25_add_i2c0(struct i2c_platform_data *pdata) return imx_add_i2c((void *)IMX_I2C1_BASE, 0, pdata); } +static inline struct device_d *imx25_add_spi0(struct spi_imx_master *pdata) +{ + return imx_add_spi((void *)IMX_CSPI1_BASE, 0, pdata); +} + static inline struct device_d *imx25_add_uart0(void) { return imx_add_uart((void *)IMX_UART1_BASE, 0); diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h index 78ec0cd..73307c4 100644 --- a/arch/arm/mach-imx/include/mach/imx25-regs.h +++ b/arch/arm/mach-imx/include/mach/imx25-regs.h @@ -47,6 +47,7 @@ #define IMX_NFC_BASE 0xBB000000 #define IMX_FEC_BASE 0x50038000 #define IMX_I2C1_BASE 0x43F80000 +#define IMX_CSPI1_BASE 0x43FA4000 /* * Clock Controller Module (CCM) diff --git a/arch/arm/mach-imx/speed-imx25.c b/arch/arm/mach-imx/speed-imx25.c index 68b50e9..150adb2 100644 --- a/arch/arm/mach-imx/speed-imx25.c +++ b/arch/arm/mach-imx/speed-imx25.c @@ -87,6 +87,11 @@ unsigned long imx_get_mmcclk(void) return imx_get_perclk(3); } +unsigned long imx_get_cspiclk(void) +{ + return imx_get_ipgclk(); +} + void imx_dump_clocks(void) { printf("mpll: %10ld Hz\n", imx_get_mpllclk()); diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index c72493c..94470fe 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -14,6 +14,11 @@ config DRIVER_SPI_IMX_0_0 depends on ARCH_IMX27 default y +config DRIVER_SPI_IMX_0_7 + bool + depends on ARCH_IMX25 + default y + config DRIVER_SPI_IMX_2_3 bool depends on ARCH_IMX51 || ARCH_IMX53 diff --git a/drivers/spi/imx_spi.c b/drivers/spi/imx_spi.c index 6dc41b9..f0d2a36 100644 --- a/drivers/spi/imx_spi.c +++ b/drivers/spi/imx_spi.c @@ -27,6 +27,7 @@ #include <gpio.h> #include <mach/spi.h> #include <mach/generic.h> +#include <mach/clock.h> #define CSPI_0_0_RXDATA 0x00 #define CSPI_0_0_TXDATA 0x04 @@ -65,6 +66,22 @@ #define CSPI_0_0_TEST_LBC (1 << 14) +#define CSPI_0_7_RXDATA 0x00 +#define CSPI_0_7_TXDATA 0x04 +#define CSPI_0_7_CTRL 0x08 +#define CSPI_0_7_CTRL_ENABLE (1 << 0) +#define CSPI_0_7_CTRL_MASTER (1 << 1) +#define CSPI_0_7_CTRL_XCH (1 << 2) +#define CSPI_0_7_CTRL_POL (1 << 4) +#define CSPI_0_7_CTRL_PHA (1 << 5) +#define CSPI_0_7_CTRL_SSCTL (1 << 6) +#define CSPI_0_7_CTRL_SSPOL (1 << 7) +#define CSPI_0_7_CTRL_CS_SHIFT 12 +#define CSPI_0_7_CTRL_DR_SHIFT 16 +#define CSPI_0_7_CTRL_BL_SHIFT 20 +#define CSPI_0_7_STAT 0x14 +#define CSPI_0_7_STAT_RR (1 << 3) + #define CSPI_2_3_RXDATA 0x00 #define CSPI_2_3_TXDATA 0x04 #define CSPI_2_3_CTRL 0x08 @@ -206,6 +223,89 @@ static void cspi_0_0_init(struct imx_spi *imx) } #endif +#ifdef CONFIG_DRIVER_SPI_IMX_0_7 +static unsigned int cspi_0_7_xchg_single(struct imx_spi *imx, unsigned int data) +{ + void __iomem *base = imx->regs; + + unsigned int cfg_reg = readl(base + CSPI_0_7_CTRL); + + writel(data, base + CSPI_0_7_TXDATA); + + cfg_reg |= CSPI_0_7_CTRL_XCH; + + writel(cfg_reg, base + CSPI_0_7_CTRL); + + while (!(readl(base + CSPI_0_7_STAT) & CSPI_0_7_STAT_RR)) + ; + + return readl(base + CSPI_0_7_RXDATA); +} + +/* MX1, MX31, MX35, MX51 CSPI */ +static unsigned int spi_imx_clkdiv_2(unsigned int fin, + unsigned int fspi) +{ + int i, div = 4; + + for (i = 0; i < 7; i++) { + if (fspi * div >= fin) + return i; + div <<= 1; + } + + return 7; +} + +static void cspi_0_7_chipselect(struct spi_device *spi, int is_active) +{ + struct spi_master *master = spi->master; + struct imx_spi *imx = container_of(master, struct imx_spi, master); + void __iomem *base = imx->regs; + unsigned int cs = 0; + int gpio = imx->cs_array[spi->chip_select]; + unsigned int reg = CSPI_0_7_CTRL_ENABLE | CSPI_0_7_CTRL_MASTER; + + if (spi->mode & SPI_CS_HIGH) + cs = 1; + + if (!is_active) { + if (gpio >= 0) + gpio_set_value(gpio, !cs); + return; + } + + reg |= spi_imx_clkdiv_2(imx_get_cspiclk(), spi->max_speed_hz) << + CSPI_0_7_CTRL_DR_SHIFT; + + reg |= (spi->bits_per_word - 1) << CSPI_0_7_CTRL_BL_SHIFT; + reg |= CSPI_0_7_CTRL_SSCTL; + + if (spi->mode & SPI_CPHA) + reg |= CSPI_0_7_CTRL_PHA; + if (spi->mode & SPI_CPOL) + reg |= CSPI_0_7_CTRL_POL; + if (spi->mode & SPI_CS_HIGH) + reg |= CSPI_0_7_CTRL_SSPOL; + if (gpio < 0) + reg |= (gpio + 32) << CSPI_0_7_CTRL_CS_SHIFT; + + writel(reg, base + CSPI_0_7_CTRL); + + if (gpio >= 0) + gpio_set_value(gpio, cs); +} + +static void cspi_0_7_init(struct imx_spi *imx) +{ + void __iomem *base = imx->regs; + + /* drain receive buffer */ + while (readl(base + CSPI_0_7_STAT) & CSPI_0_7_STAT_RR) + readl(base + CSPI_0_7_RXDATA); +} +#endif + #ifdef CONFIG_DRIVER_SPI_IMX_2_3 static unsigned int cspi_2_3_xchg_single(struct imx_spi *imx, unsigned int data) { @@ -342,6 +442,13 @@ static struct spi_imx_devtype_data spi_imx_devtype_data[] = { .init = cspi_0_0_init, }, #endif +#ifdef CONFIG_DRIVER_SPI_IMX_0_7 + [SPI_IMX_VER_0_7] = { + .chipselect = cspi_0_7_chipselect, + .xchg_single = cspi_0_7_xchg_single, + .init = cspi_0_7_init, + }, +#endif #ifdef CONFIG_DRIVER_SPI_IMX_2_3 [SPI_IMX_VER_2_3] = { .chipselect = cspi_2_3_chipselect, @@ -372,6 +479,10 @@ static int imx_spi_probe(struct device_d *dev) if (cpu_is_mx27()) version = SPI_IMX_VER_0_0; #endif +#ifdef CONFIG_DRIVER_SPI_IMX_0_7 + if (cpu_is_mx25()) + version = SPI_IMX_VER_0_7; +#endif #ifdef CONFIG_DRIVER_SPI_IMX_2_3 if (cpu_is_mx51() || cpu_is_mx53()) version = SPI_IMX_VER_2_3; -- 1.7.2.3 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] imx_spi: rework transfer according to the API, fix compatibility with spi_write_then_read() 2011-08-30 6:20 [PATCH 1/2] imx_spi: rework transfer according to the API, fix compatibility with spi_write_then_read() Paul Fertser 2011-08-30 6:30 ` [PATCH 2/2] imx25: imx_spi: support CSPI v0.7 as found on i.MX25 Paul Fertser @ 2011-09-12 10:20 ` Sascha Hauer 1 sibling, 0 replies; 5+ messages in thread From: Sascha Hauer @ 2011-09-12 10:20 UTC (permalink / raw) To: Paul Fertser; +Cc: barebox Hi Paul, On Tue, Aug 30, 2011 at 10:20:23AM +0400, Paul Fertser wrote: > This code was tested barely with m25p80 driver, reading jedec id and some data > from the chip worked fine. > > Signed-off-by: Paul Fertser <fercerpav@gmail.com> > --- > drivers/spi/imx_spi.c | 55 +++++++++++++++++++++++++++++++++++++++--------- > 1 files changed, 44 insertions(+), 11 deletions(-) Applied to -next. Thanks Sascha > > diff --git a/drivers/spi/imx_spi.c b/drivers/spi/imx_spi.c > index 6dc41b9..0d21fb3 100644 > --- a/drivers/spi/imx_spi.c > +++ b/drivers/spi/imx_spi.c > @@ -310,23 +310,56 @@ static void cspi_2_3_init(struct imx_spi *imx) > } > #endif > > +static void imx_spi_do_transfer(struct spi_device *spi, struct spi_transfer *t) > +{ > + struct imx_spi *imx = container_of(spi->master, struct imx_spi, master); > + unsigned i; > + > + if (spi->bits_per_word <= 8) { > + const u8 *tx_buf = t->tx_buf; > + u8 *rx_buf = t->rx_buf; > + u8 rx_val; > + > + for (i = 0; i < t->len; i++) { > + rx_val = imx->xchg_single(imx, tx_buf ? tx_buf[i] : 0); > + if (rx_buf) > + rx_buf[i] = rx_val; > + } > + } else if (spi->bits_per_word <= 16) { > + const u16 *tx_buf = t->tx_buf; > + u16 *rx_buf = t->rx_buf; > + u16 rx_val; > + > + for (i = 0; i < t->len >> 1; i++) { > + rx_val = imx->xchg_single(imx, tx_buf ? tx_buf[i] : 0); > + if (rx_buf) > + rx_buf[i] = rx_val; > + } > + } else if (spi->bits_per_word <= 32) { > + const u32 *tx_buf = t->tx_buf; > + u32 *rx_buf = t->rx_buf; > + u32 rx_val; > + > + for (i = 0; i < t->len >> 2; i++) { > + rx_val = imx->xchg_single(imx, tx_buf ? tx_buf[i] : 0); > + if (rx_buf) > + rx_buf[i] = rx_val; > + } > + } > +} > + > static int imx_spi_transfer(struct spi_device *spi, struct spi_message *mesg) > { > - struct spi_master *master = spi->master; > - struct imx_spi *imx = container_of(master, struct imx_spi, master); > - struct spi_transfer *t = NULL; > + struct imx_spi *imx = container_of(spi->master, struct imx_spi, master); > + struct spi_transfer *t = NULL; > > imx->chipselect(spi, 1); > > - list_for_each_entry (t, &mesg->transfers, transfer_list) { > - const u32 *txbuf = t->tx_buf; > - u32 *rxbuf = t->rx_buf; > - int i = 0; > + mesg->actual_length = 0; > > - while(i < t->len >> 2) { > - rxbuf[i] = imx->xchg_single(imx, txbuf[i]); > - i++; > - } > + list_for_each_entry(t, &mesg->transfers, transfer_list) { > + imx_spi_do_transfer(spi, t); > + mesg->actual_length += t->len; > } > > imx->chipselect(spi, 0); > -- > 1.5.2.2 > > > _______________________________________________ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox > -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2011-09-19 13:58 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2011-08-30 6:20 [PATCH 1/2] imx_spi: rework transfer according to the API, fix compatibility with spi_write_then_read() Paul Fertser 2011-08-30 6:30 ` [PATCH 2/2] imx25: imx_spi: support CSPI v0.7 as found on i.MX25 Paul Fertser 2011-09-12 10:21 ` Sascha Hauer 2011-08-30 6:30 ` [PATCH] " Paul Fertser 2011-09-12 10:20 ` [PATCH 1/2] imx_spi: rework transfer according to the API, fix compatibility with spi_write_then_read() Sascha Hauer
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