* Add basic support for the OMAP-L138/DA850
@ 2012-06-26 9:51 Jan Luebbe
2012-06-26 9:51 ` [PATCH 01/12] mach-davinci: add platform and minimal board file for HMI10 Jan Luebbe
` (12 more replies)
0 siblings, 13 replies; 22+ messages in thread
From: Jan Luebbe @ 2012-06-26 9:51 UTC (permalink / raw)
To: barebox
Hi,
this series introduces a new ARM machine 'davinci' and adds support
for UART, pin mux, power/clock, USB 1.1, NAND and SPI. Included is
support for the HMI10 system which was used to develop and test this
series.
A second series adding ethernet (EMAC) and display (LCDC) support
will be submitted when this is accepted.
Best regards,
Jan Lübbe
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^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH 01/12] mach-davinci: add platform and minimal board file for HMI10 2012-06-26 9:51 Add basic support for the OMAP-L138/DA850 Jan Luebbe @ 2012-06-26 9:51 ` Jan Luebbe 2012-06-26 9:51 ` [PATCH 02/12] mach-davinci: add GPIO support Jan Luebbe ` (11 subsequent siblings) 12 siblings, 0 replies; 22+ messages in thread From: Jan Luebbe @ 2012-06-26 9:51 UTC (permalink / raw) To: barebox This supports the serial console. Signed-off-by: Jan Luebbe <jlu@pengutronix.de> --- arch/arm/Kconfig | 4 + arch/arm/Makefile | 2 + arch/arm/boards/hmi10/Makefile | 1 + arch/arm/boards/hmi10/board.c | 92 +++++ arch/arm/boards/hmi10/config.h | 24 ++ arch/arm/boards/hmi10/env/config | 60 +++ arch/arm/mach-davinci/Kconfig | 36 ++ arch/arm/mach-davinci/Makefile | 2 + arch/arm/mach-davinci/clock.c | 94 +++++ arch/arm/mach-davinci/clocksource.c | 164 +++++++++ arch/arm/mach-davinci/include/mach/da8xx.h | 40 ++ arch/arm/mach-davinci/include/mach/hardware.h | 492 +++++++++++++++++++++++++ 12 files changed, 1011 insertions(+) create mode 100644 arch/arm/boards/hmi10/Makefile create mode 100644 arch/arm/boards/hmi10/board.c create mode 100644 arch/arm/boards/hmi10/config.h create mode 100644 arch/arm/boards/hmi10/env/config create mode 100644 arch/arm/mach-davinci/Kconfig create mode 100644 arch/arm/mach-davinci/Makefile create mode 100644 arch/arm/mach-davinci/clock.c create mode 100644 arch/arm/mach-davinci/clocksource.c create mode 100644 arch/arm/mach-davinci/include/mach/da8xx.h create mode 100644 arch/arm/mach-davinci/include/mach/hardware.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3eada5b..336fc24 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -36,6 +36,9 @@ config ARCH_AT91 select GENERIC_GPIO select CLKDEV_LOOKUP +config ARCH_DAVINCI + bool "TI Davinci" + config ARCH_EP93XX bool "Cirrus Logic EP93xx" select CPU_ARM920T @@ -92,6 +95,7 @@ endchoice source arch/arm/cpu/Kconfig source arch/arm/mach-at91/Kconfig +source arch/arm/mach-davinci/Kconfig source arch/arm/mach-ep93xx/Kconfig source arch/arm/mach-imx/Kconfig source arch/arm/mach-mxs/Kconfig diff --git a/arch/arm/Makefile b/arch/arm/Makefile index bd684dc..e890efb 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -52,6 +52,7 @@ AFLAGS += -include asm/unified.h -msoft-float $(AFLAGS_THUMB2) # Machine directory name. This list is sorted alphanumerically # by CONFIG_* macro name. machine-$(CONFIG_ARCH_AT91) := at91 +machine-$(CONFIG_ARCH_DAVINCI) := davinci machine-$(CONFIG_ARCH_EP93XX) := ep93xx machine-$(CONFIG_ARCH_IMX) := imx machine-$(CONFIG_ARCH_MXS) := mxs @@ -90,6 +91,7 @@ board-$(CONFIG_MACH_EUKREA_CPUIMX35) := eukrea_cpuimx35 board-$(CONFIG_MACH_EUKREA_CPUIMX51SD) := eukrea_cpuimx51 board-$(CONFIG_MACH_FREESCALE_MX25_3STACK) := freescale-mx25-3-stack board-$(CONFIG_MACH_FREESCALE_MX35_3STACK) := freescale-mx35-3-stack +board-$(CONFIG_MACH_HMI10) := hmi10 board-$(CONFIG_MACH_IMX21ADS) := imx21ads board-$(CONFIG_MACH_IMX27ADS) := imx27ads board-$(CONFIG_MACH_MIOA701) := mioa701 diff --git a/arch/arm/boards/hmi10/Makefile b/arch/arm/boards/hmi10/Makefile new file mode 100644 index 0000000..dcfc293 --- /dev/null +++ b/arch/arm/boards/hmi10/Makefile @@ -0,0 +1 @@ +obj-y += board.o diff --git a/arch/arm/boards/hmi10/board.c b/arch/arm/boards/hmi10/board.c new file mode 100644 index 0000000..be4d920 --- /dev/null +++ b/arch/arm/boards/hmi10/board.c @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2012 Jan Luebbe <j.luebbe@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <common.h> +#include <console.h> +#include <init.h> +#include <driver.h> +#include <sizes.h> +#include <io.h> +#include <ns16550.h> +#include <partition.h> +#include <spi/spi.h> +#include <spi/flash.h> +#include <asm/armlinux.h> +#include <generated/mach-types.h> +#include <linux/err.h> +#include <linux/mtd/nand.h> + +#include <mach/hardware.h> +#include <mach/da8xx.h> + +#ifdef CONFIG_DRIVER_SERIAL_NS16550 +static struct NS16550_plat serial_plat = { + //.clock is calculated in hmi10_console_init + .shift = 2, +}; + +/** + * @brief UART serial port initialization - remember to enable COM clocks in + * arch + * + * @return result of device registration + */ +static int hmi10_console_init(void) +{ + /* Register the serial port */ + writel(0x44440000, &davinci_uart2_ctrl_regs->mdr); + serial_plat.clock = da8xx_clk_get(DAVINCI_UART2_CLKID); + add_ns16550_device(-1, DAVINCI_UART2_BASE, 1024, IORESOURCE_MEM_32BIT, + &serial_plat); + /* bring TX (bit 14) and TX (bit 13) out of reset */ + writel((1<<14) | (1<<13), &davinci_uart2_ctrl_regs->pwremu_mgmt); + + return 0; +} +console_initcall(hmi10_console_init); +#endif /* CONFIG_DRIVER_SERIAL_NS16550 */ + +static int hmi10_postconsole_init(void) +{ + printf("ARM Clock: %d Hz\n", da8xx_clk_get(DAVINCI_ARM_CLKID)); + //printf("DDR Clock: %d Hz\n", da8xx_clk_get(DAVINCI_DDR_CLKID)/2); + //printf("AUX Clock: %d Hz\n", da8xx_clk_get(DAVINCI_AUXCLK_CLKID)); + //printf("UART2 Clock: %d Hz\n", da8xx_clk_get(DAVINCI_UART2_CLKID)); + //printf("EMIFA Clock: %d Hz\n", da8xx_clk_get(DAVINCI_EMIFA_CLKID)); + + return 0; +} +postconsole_initcall(hmi10_postconsole_init); + +static int hmi10_mem_init(void) +{ + arm_add_mem_device("ram0", 0xc0000000, SZ_32M); + arm_add_mem_device("ram1", 0xc4000000, SZ_64M); + + return 0; +} +mem_initcall(hmi10_mem_init); + +static int hmi10_devices_init(void) +{ + armlinux_set_bootparams((void *)0xc0000100); + armlinux_set_architecture(MACH_TYPE_DAVINCI_HE_HMI10); + + return 0; +} +device_initcall(hmi10_devices_init); diff --git a/arch/arm/boards/hmi10/config.h b/arch/arm/boards/hmi10/config.h new file mode 100644 index 0000000..d430e2c --- /dev/null +++ b/arch/arm/boards/hmi10/config.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2012 Jan Luebbe <j.luebbe@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_OSCIN_FREQ 24000000 + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/hmi10/env/config b/arch/arm/boards/hmi10/env/config new file mode 100644 index 0000000..de146f3 --- /dev/null +++ b/arch/arm/boards/hmi10/env/config @@ -0,0 +1,60 @@ +#!/bin/sh + +machine=hmi10 +user= + +# Enter MAC address here if not retrieved automatically +#eth0.ethaddr=de:ad:be:ef:00:00 + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp +dhcp_vendor_id=barebox + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.serverip=a.b.c.d +#eth0.gateway=a.b.c.d + +# can be either 'tftp', 'nfs', 'nand', 'nor' or 'disk' +kernel_loc=tftp +#kernel_loc=nand +# can be either 'net', 'nand', 'nor', 'disk' or 'initrd' +rootfs_loc=net +#rootfs_loc=nand + +# for flash based rootfs: 'jffs2' or 'ubifs' +# in case of disk any regular filesystem like 'ext2', 'ext3', 'reiserfs' +rootfs_type=ubifs +# where is the rootfs in case of 'rootfs_loc=disk' (linux name) +#rootfs_part_linux_dev=mmcblk0p4 +rootfsimage=rootfs-${machine}.$rootfs_type + +# where is the kernel image in case of 'kernel_loc=disk' +#kernel_part=disk0.2 + +#kernelimage=zImage-$machine +kernelimage=uImage-$machine +#kernelimage=Image-$machine +#kernelimage=Image-$machine.lzo + +bareboximage=barebox-${machine}.bin +bareboxenvimage=barebox-${machine}.bin + +if [ -n $user ]; then + bareboximage="$user"-"$bareboximage" + bareboxenvimage="$user"-"$bareboxenvimage" + kernelimage="$user"-"$kernelimage" + rootfsimage="$user"-"$rootfsimage" + nfsroot="/home/$user/nfsroot/$machine" +else + nfsroot="/path/to/nfs/root" +fi + +autoboot_timeout=1 + +bootargs="console=ttyS2,115200 ro" + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig new file mode 100644 index 0000000..4109763 --- /dev/null +++ b/arch/arm/mach-davinci/Kconfig @@ -0,0 +1,36 @@ +menu "Davinci features" + depends on ARCH_DAVINCI + +config MACH_OMAP + bool + +config SOC_DA8XX + bool + +choice + prompt "Select Davinci variant" + +config ARCH_DAVINCI_DA850 + bool "DA850/OMAP-L138/AM18x" + select CPU_ARM926T + select SOC_DA8XX + +endchoice + +config ARCH_TEXT_BASE + hex + default 0xc1e00000 if MACH_HMI10 + +config BOARDINFO + default "Hesch HMI10" if MACH_HMI10 + +choice + prompt "Select Davinci board" + +config MACH_HMI10 + bool "Hesch HMI10" + depends on ARCH_DAVINCI_DA850 + +endchoice + +endmenu diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile new file mode 100644 index 0000000..5f1e545 --- /dev/null +++ b/arch/arm/mach-davinci/Makefile @@ -0,0 +1,2 @@ +obj-y += clock.o +obj-y += clocksource.o diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c new file mode 100644 index 0000000..cd53a98 --- /dev/null +++ b/arch/arm/mach-davinci/clock.c @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2004 Texas Instruments. + * Copyright (C) 2009 David Brownell + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <io.h> +#include <mach/hardware.h> + +/* offsets from PLL controller base */ +#define PLLC_PLLCTL 0x100 +#define PLLC_PLLM 0x110 +#define PLLC_PREDIV 0x114 +#define PLLC_PLLDIV1 0x118 +#define PLLC_PLLDIV2 0x11c +#define PLLC_PLLDIV3 0x120 +#define PLLC_POSTDIV 0x128 +#define PLLC_BPDIV 0x12c +#define PLLC_PLLDIV4 0x160 +#define PLLC_PLLDIV5 0x164 +#define PLLC_PLLDIV6 0x168 +#define PLLC_PLLDIV7 0x16c +#define PLLC_PLLDIV8 0x170 +#define PLLC_PLLDIV9 0x174 + +/* SOC-specific pll info */ +unsigned int sysdiv[9] = { + PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5, + PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9 +}; + +int da8xx_clk_get(enum davinci_clk_ids id) +{ + int pre_div; + int pllm; + int post_div; + int pll_out; + unsigned int pll_base; + + pll_out = CONFIG_SYS_OSCIN_FREQ; + + if (id == DAVINCI_AUXCLK_CLKID) + goto out; + + if ((id >> 16) == 1) + pll_base = DAVINCI_PLL_CNTRL1_BASE; + else + pll_base = DAVINCI_PLL_CNTRL0_BASE; + + id &= 0xFFFF; + + /* + * Lets keep this simple. Combining operations can result in + * unexpected approximations + */ + pre_div = (readl(pll_base + PLLC_PREDIV) & 0xff) + 1; + pllm = readl(pll_base + PLLC_PLLM) + 1; + + pll_out /= pre_div; + pll_out *= pllm; + + if (id == DAVINCI_PLLM_CLKID) + goto out; + + post_div = (readl(pll_base + PLLC_POSTDIV) & 0xff) + 1; + + pll_out /= post_div; + + if (id == DAVINCI_PLLC_CLKID) + goto out; + + pll_out /= (readl(pll_base + sysdiv[id - 1]) & 0xff) + 1; + +out: + return pll_out; +} diff --git a/arch/arm/mach-davinci/clocksource.c b/arch/arm/mach-davinci/clocksource.c new file mode 100644 index 0000000..1d0920b --- /dev/null +++ b/arch/arm/mach-davinci/clocksource.c @@ -0,0 +1,164 @@ +/* + * (C) Copyright 2012 Jan Luebbe <j.luebbe@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Based on code from the linux kernel: + * arch/arm/mach-davinci/time.c + * Copyright 2007 (c) MontaVista Software, Inc. + */ + +#include <common.h> +#include <init.h> +#include <clock.h> +#include <asm/io.h> + +#include <mach/da8xx.h> +#include <mach/hardware.h> + +/* Timer register offsets */ +#define PID12 0x0 +#define TIM12 0x10 +#define TIM34 0x14 +#define PRD12 0x18 +#define PRD34 0x1c +#define TCR 0x20 +#define TGCR 0x24 +#define WDTCR 0x28 + +/* Timer register bitfields */ +#define TCR_ENAMODE12_SHIFT 6 +#define TCR_ENAMODE34_SHIFT 22 +#define TCR_ENAMODE_DISABLE 0x0 +#define TCR_ENAMODE_ONESHOT 0x1 +#define TCR_ENAMODE_PERIODIC 0x2 +#define TCR_ENAMODE_MASK 0x3 + +#define TGCR_TIMMODE_SHIFT 2 +#define TGCR_TIMMODE_64BIT_GP 0x0 +#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1 +#define TGCR_TIMMODE_64BIT_WDOG 0x2 +#define TGCR_TIMMODE_32BIT_CHAINED 0x3 + +#define TGCR_TIM12RS_SHIFT 0 +#define TGCR_TIM34RS_SHIFT 1 +#define TGCR_RESET 0x0 +#define TGCR_UNRESET 0x1 +#define TGCR_RESET_MASK 0x3 + +#define WDTCR_WDEN_SHIFT 14 +#define WDTCR_WDEN_DISABLE 0x0 +#define WDTCR_WDEN_ENABLE 0x1 +#define WDTCR_WDKEY_SHIFT 16 +#define WDTCR_WDKEY_SEQ0 0xa5c6 +#define WDTCR_WDKEY_SEQ1 0xda7e + +uint64_t davinci_clocksource_read(void) +{ + /* When reading TIM12, TIM34 is copied into a shadow register */ + uint32_t tim12, tim34; + tim12 = readl(DA8XX_TIMER64P0_BASE + TIM12); + tim34 = readl(DA8XX_TIMER64P0_BASE + TIM34); + return tim12; // FIXME +} + +static struct clocksource cs = { + .read = davinci_clocksource_read, + .mask = 0xffffffff, + .shift = 20, +}; + +static int clocksource_init(void) +{ + uint32_t tcr, tgcr; + /* Disabled, Internal clock source */ + writel(0, DA8XX_TIMER64P0_BASE + TCR); + + /* reset both timers, no pre-scaler for timer34 */ + tgcr = 0; + writel(tgcr, DA8XX_TIMER64P0_BASE + TGCR); + + /* Set both timers to unchained 32-bit */ + tgcr = TGCR_TIMMODE_64BIT_GP << TGCR_TIMMODE_SHIFT; + writel(tgcr, DA8XX_TIMER64P0_BASE + TGCR); + + /* Unreset timers */ + tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | + (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); + writel(tgcr, DA8XX_TIMER64P0_BASE + TGCR); + + /* Init both counters to zero */ + writel(0, DA8XX_TIMER64P0_BASE + TIM12); + writel(0, DA8XX_TIMER64P0_BASE + TIM34); + writel(~0, DA8XX_TIMER64P0_BASE + PRD12); + writel(~0, DA8XX_TIMER64P0_BASE + PRD34); + + tcr = TCR_ENAMODE_PERIODIC << TCR_ENAMODE12_SHIFT; + writel(tcr, DA8XX_TIMER64P0_BASE + TCR); + + cs.mult = clocksource_hz2mult(da8xx_clk_get(DAVINCI_AUXCLK_CLKID), cs.shift); + + init_clock(&cs); + + return 0; +} + +core_initcall(clocksource_init); + +/* reset board using watchdog timer (TIMER64P1) */ +void davinci_watchdog_reset(void) +{ + uint32_t tgcr, wdtcr; + + /* disable, internal clock source */ + writel(0, DA8XX_TIMER64P1_BASE + TCR); + + /* reset timer, set mode to 64-bit watchdog, and unreset */ + tgcr = 0; + writel(tgcr, DA8XX_TIMER64P1_BASE + TGCR); + tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT; + tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | + (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); + writel(tgcr, DA8XX_TIMER64P1_BASE + TGCR); + + /* clear counter and period regs */ + writel(0, DA8XX_TIMER64P1_BASE + TIM12); + writel(0, DA8XX_TIMER64P1_BASE + TIM34); + writel(0, DA8XX_TIMER64P1_BASE + PRD12); + writel(0, DA8XX_TIMER64P1_BASE + PRD34); + + /* put watchdog in pre-active state */ + wdtcr = readl(DA8XX_TIMER64P1_BASE + WDTCR); + wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) | + (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); + writel(wdtcr, DA8XX_TIMER64P1_BASE + WDTCR); + + /* put watchdog in active state */ + wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) | + (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); + writel(wdtcr, DA8XX_TIMER64P1_BASE + WDTCR); + + /* write an invalid value to the WDKEY field to trigger + * a watchdog reset */ + wdtcr = 0x00004000; + writel(wdtcr, DA8XX_TIMER64P1_BASE + WDTCR); +} + +void __noreturn reset_cpu(unsigned long addr) +{ + davinci_watchdog_reset(); + + while (1); +} +EXPORT_SYMBOL(reset_cpu); diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h new file mode 100644 index 0000000..1efcaad --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -0,0 +1,40 @@ +/* + * Chip specific defines for DA8XX/OMAP L1XX SoC + * + * Author: Mark A. Greer <mgreer@mvista.com> + * + * 2007, 2009-2010 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_DAVINCI_DA8XX_H +#define __ASM_ARCH_DAVINCI_DA8XX_H + +#define IO_PHYS 0x01c00000UL + +#define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000) +#define DA8XX_JTAG_ID_REG 0x18 +#define DA8XX_MSTPRI0_REG 0x110 +#define DA8XX_MSTPRI1_REG 0x114 +#define DA8XX_MSTPRI2_REG 0x118 +#define DA8XX_CFGCHIP0_REG 0x17c +#define DA8XX_CFGCHIP2_REG 0x184 +#define DA8XX_CFGCHIP3_REG 0x188 + +#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000) +#define DA8XX_DEEPSLEEP_REG 0x8 +#define DA8XX_PWRDN_REG 0x18 + +#define DA8XX_PSC0_BASE 0x01c10000 +#define DA8XX_PLL0_BASE 0x01c11000 +#define DA8XX_TIMER64P0_BASE 0x01c20000 +#define DA8XX_TIMER64P1_BASE 0x01c21000 +#define DA8XX_GPIO_BASE 0x01e26000 +#define DA8XX_PSC1_BASE 0x01e27000 +#define DA8XX_AEMIF_CS2_BASE 0x60000000 +#define DA8XX_AEMIF_CS3_BASE 0x62000000 +#define DA8XX_AEMIF_CTL_BASE 0x68000000 +#define DA8XX_ARM_RAM_BASE 0xffff0000 + +#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h new file mode 100644 index 0000000..098ed22 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/hardware.h @@ -0,0 +1,492 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Based on: + * + * ------------------------------------------------------------------------- + * + * linux/include/asm-arm/arch-davinci/hardware.h + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <sizes.h> +#include <asm-generic/io.h> + +typedef volatile unsigned int dv_reg; +typedef volatile unsigned int * dv_reg_p; + +/* + * Base register addresses + * + * NOTE: some of these DM6446-specific addresses DO NOT WORK + * on other DaVinci chips. Double check them before you try + * using the addresses ... or PSC module identifiers, etc. + */ +#ifndef CONFIG_SOC_DA8XX + +#define DAVINCI_DMA_3PCC_BASE (0x01c00000) +#define DAVINCI_DMA_3PTC0_BASE (0x01c10000) +#define DAVINCI_DMA_3PTC1_BASE (0x01c10400) +#define DAVINCI_UART0_BASE (0x01c20000) +#define DAVINCI_UART1_BASE (0x01c20400) +#define DAVINCI_I2C_BASE (0x01c21000) +#define DAVINCI_TIMER0_BASE (0x01c21400) +#define DAVINCI_TIMER1_BASE (0x01c21800) +#define DAVINCI_WDOG_BASE (0x01c21c00) +#define DAVINCI_PWM0_BASE (0x01c22000) +#define DAVINCI_PWM1_BASE (0x01c22400) +#define DAVINCI_PWM2_BASE (0x01c22800) +#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000) +#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800) +#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00) +#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000) +#define DAVINCI_ARM_INTC_BASE (0x01c48000) +#define DAVINCI_USB_OTG_BASE (0x01c64000) +#define DAVINCI_CFC_ATA_BASE (0x01c66000) +#define DAVINCI_SPI_BASE (0x01c66800) +#define DAVINCI_GPIO_BASE (0x01c67000) +#define DAVINCI_VPSS_REGS_BASE (0x01c70000) +#if !defined(CONFIG_SOC_DM646X) +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) +#endif +#define DAVINCI_DDR_BASE (0x80000000) + +#ifdef CONFIG_SOC_DM644X +#define DAVINCI_UART2_BASE 0x01c20800 +#define DAVINCI_UHPI_BASE 0x01c67800 +#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000 +#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000 +#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000 +#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000 +#define DAVINCI_IMCOP_BASE 0x01cc0000 +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000 +#define DAVINCI_VLYNQ_BASE 0x01e01000 +#define DAVINCI_ASP_BASE 0x01e02000 +#define DAVINCI_MMC_SD_BASE 0x01e10000 +#define DAVINCI_MS_BASE 0x01e20000 +#define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000 + +#elif defined(CONFIG_SOC_DM355) +#define DAVINCI_MMC_SD1_BASE 0x01e00000 +#define DAVINCI_ASP0_BASE 0x01e02000 +#define DAVINCI_ASP1_BASE 0x01e04000 +#define DAVINCI_UART2_BASE 0x01e06000 +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000 +#define DAVINCI_MMC_SD0_BASE 0x01e11000 + +#elif defined(CONFIG_SOC_DM365) +#define DAVINCI_MMC_SD1_BASE 0x01d00000 +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000 +#define DAVINCI_MMC_SD0_BASE 0x01d11000 + +#elif defined(CONFIG_SOC_DM646X) +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000 +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000 + +#endif + +#else /* CONFIG_SOC_DA8XX */ + +#define DAVINCI_MMC_SD0_BASE 0x01c40000 +#define DAVINCI_UART0_BASE 0x01c42000 +#define DAVINCI_UART1_BASE 0x01d0c000 +#define DAVINCI_UART2_BASE 0x01d0d000 +#define DAVINCI_I2C0_BASE 0x01c22000 +#define DAVINCI_I2C1_BASE 0x01e28000 +#define DAVINCI_TIMER0_BASE 0x01c20000 +#define DAVINCI_TIMER1_BASE 0x01c21000 +#define DAVINCI_WDOG_BASE 0x01c21000 +#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000 +#define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000 +#define DAVINCI_PSC0_BASE 0x01c10000 +#define DAVINCI_PSC1_BASE 0x01e27000 +#define DAVINCI_SPI0_BASE 0x01c41000 +#define DAVINCI_USB_OTG_BASE 0x01e00000 +#define DAVINCI_SPI1_BASE (cpu_is_da830() ? 0x01e12000 : 0x01f0e000) +#define DAVINCI_GPIO_BASE 0x01e26000 +#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000 +#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000 +#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000 +#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000 +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000 +#define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000 +#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000 +#define DAVINCI_INTC_BASE 0xfffee000 +#define DAVINCI_BOOTCFG_BASE 0x01c14000 +#define DAVINCI_L3CBARAM_BASE 0x80000000 +#define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18) +#define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24) +#define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44) +#define CFGCHIP3 (DAVINCI_BOOTCFG_BASE + 0x188) +#define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00) +#define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10) +#define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14) +#define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18) +#define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c) +#define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38) +#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c) +#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40) +#define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44) + +#endif /* CONFIG_SOC_DA8XX */ + +/* Power and Sleep Controller (PSC) Domains */ +#define DAVINCI_GPSC_ARMDOMAIN 0 +#define DAVINCI_GPSC_DSPDOMAIN 1 + +#ifndef CONFIG_SOC_DA8XX + +#define DAVINCI_LPSC_VPSSMSTR 0 +#define DAVINCI_LPSC_VPSSSLV 1 +#define DAVINCI_LPSC_TPCC 2 +#define DAVINCI_LPSC_TPTC0 3 +#define DAVINCI_LPSC_TPTC1 4 +#define DAVINCI_LPSC_EMAC 5 +#define DAVINCI_LPSC_EMAC_WRAPPER 6 +#define DAVINCI_LPSC_MDIO 7 +#define DAVINCI_LPSC_IEEE1394 8 +#define DAVINCI_LPSC_USB 9 +#define DAVINCI_LPSC_ATA 10 +#define DAVINCI_LPSC_VLYNQ 11 +#define DAVINCI_LPSC_UHPI 12 +#define DAVINCI_LPSC_DDR_EMIF 13 +#define DAVINCI_LPSC_AEMIF 14 +#define DAVINCI_LPSC_MMC_SD 15 +#define DAVINCI_LPSC_MEMSTICK 16 +#define DAVINCI_LPSC_McBSP 17 +#define DAVINCI_LPSC_I2C 18 +#define DAVINCI_LPSC_UART0 19 +#define DAVINCI_LPSC_UART1 20 +#define DAVINCI_LPSC_UART2 21 +#define DAVINCI_LPSC_SPI 22 +#define DAVINCI_LPSC_PWM0 23 +#define DAVINCI_LPSC_PWM1 24 +#define DAVINCI_LPSC_PWM2 25 +#define DAVINCI_LPSC_GPIO 26 +#define DAVINCI_LPSC_TIMER0 27 +#define DAVINCI_LPSC_TIMER1 28 +#define DAVINCI_LPSC_TIMER2 29 +#define DAVINCI_LPSC_SYSTEM_SUBSYS 30 +#define DAVINCI_LPSC_ARM 31 +#define DAVINCI_LPSC_SCR2 32 +#define DAVINCI_LPSC_SCR3 33 +#define DAVINCI_LPSC_SCR4 34 +#define DAVINCI_LPSC_CROSSBAR 35 +#define DAVINCI_LPSC_CFG27 36 +#define DAVINCI_LPSC_CFG3 37 +#define DAVINCI_LPSC_CFG5 38 +#define DAVINCI_LPSC_GEM 39 +#define DAVINCI_LPSC_IMCOP 40 + +#define DAVINCI_DM646X_LPSC_EMAC 14 +#define DAVINCI_DM646X_LPSC_UART0 26 +#define DAVINCI_DM646X_LPSC_I2C 31 + +#else /* CONFIG_SOC_DA8XX */ + +enum davinci_lpsc_ids { + DAVINCI_LPSC_TPCC = 0, + DAVINCI_LPSC_TPTC0, + DAVINCI_LPSC_TPTC1, + DAVINCI_LPSC_AEMIF, + DAVINCI_LPSC_SPI0, + DAVINCI_LPSC_MMC_SD, + DAVINCI_LPSC_AINTC, + DAVINCI_LPSC_ARM_RAM_ROM, + DAVINCI_LPSC_SECCTL_KEYMGR, + DAVINCI_LPSC_UART0, + DAVINCI_LPSC_SCR0, + DAVINCI_LPSC_SCR1, + DAVINCI_LPSC_SCR2, + DAVINCI_LPSC_DMAX, + DAVINCI_LPSC_ARM, + DAVINCI_LPSC_GEM, + /* for LPSCs in PSC1, offset from 32 for differentiation */ + DAVINCI_LPSC_PSC1_BASE = 32, // 1- 0 + DAVINCI_LPSC_USB11, // 1- 1 + DAVINCI_LPSC_USB20, // 1- 2 + DAVINCI_LPSC_GPIO, // 1- 3 + DAVINCI_LPSC_UHPI, // 1- 4 + DAVINCI_LPSC_EMAC, // 1- 5 + DAVINCI_LPSC_DDR_EMIF, // 1- 6 + DAVINCI_LPSC_McASP0, // 1- 7 + DAVINCI_LPSC_McASP1, // 1- 8 + DAVINCI_LPSC_McASP2, // 1- 9 + DAVINCI_LPSC_SPI1, // 1-10 + DAVINCI_LPSC_I2C1, // 1-11 + DAVINCI_LPSC_UART1, // 1-12 + DAVINCI_LPSC_UART2, // 1-13 + DAVINCI_LPSC_McBSP0, // 1-14 + DAVINCI_LPSC_McBSP1, // 1-15 + DAVINCI_LPSC_LCDC, // 1-16 +}; + +#endif /* CONFIG_SOC_DA8XX */ + +void lpsc_on(unsigned int id); +void dsp_on(void); + +void davinci_enable_uart0(void); +void davinci_enable_emac(void); +void davinci_enable_i2c(void); +void davinci_errata_workarounds(void); + +#ifndef CONFIG_SOC_DA8XX + +/* Some PSC defines */ +#define PSC_CHP_SHRTSW (0x01c40038) +#define PSC_GBLCTL (0x01c41010) +#define PSC_EPCPR (0x01c41070) +#define PSC_EPCCR (0x01c41078) +#define PSC_PTCMD (0x01c41120) +#define PSC_PTSTAT (0x01c41128) +#define PSC_PDSTAT (0x01c41200) +#define PSC_PDSTAT1 (0x01c41204) +#define PSC_PDCTL (0x01c41300) +#define PSC_PDCTL1 (0x01c41304) + +#define PSC_MDCTL_BASE (0x01c41a00) +#define PSC_MDSTAT_BASE (0x01c41800) + +#define VDD3P3V_PWDN (0x01c40048) +#define UART0_PWREMU_MGMT (0x01c20030) + +#define PSC_SILVER_BULLET (0x01c41a20) + +#else /* CONFIG_SOC_DA8XX */ + +#define PSC_PSC0_MODULE_ID_CNT 16 +#define PSC_PSC1_MODULE_ID_CNT 32 + +struct davinci_psc_regs { + dv_reg revid; + dv_reg rsvd0[71]; + dv_reg ptcmd; + dv_reg rsvd1; + dv_reg ptstat; + dv_reg rsvd2[437]; + union { + struct { + dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT]; + dv_reg rsvd3[112]; + dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT]; + } psc0; + struct { + dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT]; + dv_reg rsvd3[96]; + dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT]; + } psc1; + }; +}; + +#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE) +#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE) + +#endif /* CONFIG_SOC_DA8XX */ + +#ifndef CONFIG_SOC_DA8XX + +/* Miscellania... */ +#define VBPR (0x20000020) + +/* NOTE: system control modules are *highly* chip-specific, both + * as to register content (e.g. for muxing) and which registers exist. + */ +#define PINMUX0 0x01c40000 +#define PINMUX1 0x01c40004 +#define PINMUX2 0x01c40008 +#define PINMUX3 0x01c4000c +#define PINMUX4 0x01c40010 + +#else /* CONFIG_SOC_DA8XX */ + +struct davinci_pllc_regs { + dv_reg revid; + dv_reg rsvd1[56]; + dv_reg rstype; + dv_reg rsvd2[6]; + dv_reg pllctl; + dv_reg ocsel; + dv_reg rsvd3[2]; + dv_reg pllm; + dv_reg prediv; + dv_reg plldiv1; + dv_reg plldiv2; + dv_reg plldiv3; + dv_reg oscdiv; + dv_reg postdiv; + dv_reg rsvd4[3]; + dv_reg pllcmd; + dv_reg pllstat; + dv_reg alnctl; + dv_reg dchange; + dv_reg cken; + dv_reg ckstat; + dv_reg systat; + dv_reg rsvd5[3]; + dv_reg plldiv4; + dv_reg plldiv5; + dv_reg plldiv6; + dv_reg plldiv7; + dv_reg rsvd6[32]; + dv_reg emucnt0; + dv_reg emucnt1; +}; + +#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE) +#define DAVINCI_PLLC_DIV_MASK 0x1f + +#define ASYNC3 get_async3_src() +#define EMIFB get_emifb_src() +#define PLL1_PLLM ((1 << 16) | DAVINCI_PLLM_CLKID) +#define PLL1_SYSCLK1 ((1 << 16) | 0x1) +#define PLL1_SYSCLK2 ((1 << 16) | 0x2) + +#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3) +#define DAVINCI_DDR_CLKID EMIFB + +/* Clock IDs */ +enum davinci_clk_ids { + DAVINCI_MMCSD_CLKID = 2, + DAVINCI_SPI0_CLKID = 2, + DAVINCI_UART2_CLKID = 2, + DAVINCI_LCDC_CLKID = 2, + DAVINCI_EMIFA_CLKID = 3, + DAVINCI_MDIO_CLKID = 4, + DAVINCI_ARM_CLKID = 6, + DAVINCI_PLLM_CLKID = 0xff, + DAVINCI_PLLC_CLKID = 0x100, + DAVINCI_AUXCLK_CLKID = 0x101 +}; + +int da8xx_clk_get(enum davinci_clk_ids id); + +/* Boot config */ +struct davinci_syscfg_regs { + dv_reg revid; + dv_reg rsvd[71]; + dv_reg pinmux[20]; + dv_reg suspsrc; + dv_reg chipsig; + dv_reg chipsig_clr; + dv_reg cfgchip0; + dv_reg cfgchip1; + dv_reg cfgchip2; + dv_reg cfgchip3; + dv_reg cfgchip4; +}; + +#define davinci_syscfg_regs \ + ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE) + +/* Emulation suspend bits */ +#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5) +#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16) +#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21) +#define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22) +#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20) +#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27) + +/* Interrupt controller */ +struct davinci_aintc_regs { + dv_reg revid; + dv_reg cr; + dv_reg dummy0[2]; + dv_reg ger; + dv_reg dummy1[219]; + dv_reg ecr1; + dv_reg ecr2; + dv_reg ecr3; + dv_reg dummy2[1117]; + dv_reg hier; +}; + +#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE) + +struct davinci_uart_ctrl_regs { + dv_reg revid1; + dv_reg revid2; + dv_reg pwremu_mgmt; + dv_reg mdr; +}; + +#define DAVINCI_UART_CTRL_BASE 0x28 +#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE) +#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE) +#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE) + +#define davinci_uart0_ctrl_regs \ + ((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR) +#define davinci_uart1_ctrl_regs \ + ((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR) +#define davinci_uart2_ctrl_regs \ + ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR) + +/* UART PWREMU_MGMT definitions */ +#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0) +#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13) +#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14) + +static inline int cpu_is_da830(void) +{ + unsigned int jtag_id = readl(JTAG_ID_REG); + unsigned short part_no = (jtag_id >> 12) & 0xffff; + + return ((part_no == 0xb7df) ? 1 : 0); +} +static inline int cpu_is_da850(void) +{ + unsigned int jtag_id = readl(JTAG_ID_REG); + unsigned short part_no = (jtag_id >> 12) & 0xffff; + + return ((part_no == 0xb7d1) ? 1 : 0); +} + +static inline int get_async3_src(void) +{ + return ((readl(CFGCHIP3) & 0x10) ? PLL1_SYSCLK2 : 2); +} + +static inline int get_emifb_src(void) +{ + return ((readl(CFGCHIP3) & 0x80) ? PLL1_PLLM : PLL1_SYSCLK1); +} + +#endif /* CONFIG_SOC_DA8XX */ + +#endif /* __ASM_ARCH_HARDWARE_H */ -- 1.7.10 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 02/12] mach-davinci: add GPIO support 2012-06-26 9:51 Add basic support for the OMAP-L138/DA850 Jan Luebbe 2012-06-26 9:51 ` [PATCH 01/12] mach-davinci: add platform and minimal board file for HMI10 Jan Luebbe @ 2012-06-26 9:51 ` Jan Luebbe 2012-06-26 9:51 ` [PATCH 03/12] mach-davinci: add pin mux support Jan Luebbe ` (10 subsequent siblings) 12 siblings, 0 replies; 22+ messages in thread From: Jan Luebbe @ 2012-06-26 9:51 UTC (permalink / raw) To: barebox Signed-off-by: Jan Luebbe <jlu@pengutronix.de> --- arch/arm/mach-davinci/Makefile | 1 + arch/arm/mach-davinci/gpio.c | 117 +++++++++++++++++++++++++++++ arch/arm/mach-davinci/include/mach/gpio.h | 11 +++ 3 files changed, 129 insertions(+) create mode 100644 arch/arm/mach-davinci/gpio.c create mode 100644 arch/arm/mach-davinci/include/mach/gpio.h diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 5f1e545..0a4e2dc 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -1,2 +1,3 @@ obj-y += clock.o obj-y += clocksource.o +obj-y += gpio.o diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c new file mode 100644 index 0000000..12a50c1 --- /dev/null +++ b/arch/arm/mach-davinci/gpio.c @@ -0,0 +1,117 @@ +/* + * TI DaVinci GPIO Support + * + * Copyright (c) 2006-2007 David Brownell + * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <common.h> +#include <errno.h> +#include <io.h> +#include <mach/gpio.h> + +#ifndef CONFIG_SOC_DA8XX +#define DAVINCI_GPIO_BASE 0x01C67000 +#else +#define DAVINCI_GPIO_BASE 0x01E26000 +#endif + +struct davinci_gpio_regs { + u32 dir; + u32 out_data; + u32 set_data; + u32 clr_data; + u32 in_data; + u32 set_rising; + u32 clr_rising; + u32 set_falling; + u32 clr_falling; + u32 intstat; +}; + +static void __iomem *gpio_base = (void *)DAVINCI_GPIO_BASE; + +static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio) +{ + void __iomem *ptr; + + if (gpio < 32 * 1) + ptr = gpio_base + 0x10; + else if (gpio < 32 * 2) + ptr = gpio_base + 0x38; + else if (gpio < 32 * 3) + ptr = gpio_base + 0x60; + else if (gpio < 32 * 4) + ptr = gpio_base + 0x88; + else if (gpio < 32 * 5) + ptr = gpio_base + 0xb0; + else + ptr = NULL; + return ptr; +} + +static inline int __davinci_direction(unsigned gpio, bool out, int value) +{ + struct davinci_gpio_regs __iomem *g = gpio2regs(gpio); + u32 temp; + int shift = gpio % 32; + u32 mask = 1 << shift; + + temp = readl(&g->dir); + if (out) { + temp &= ~mask; + writel(mask, value ? &g->set_data : &g->clr_data); + } else { + temp |= mask; + } + writel(temp, &g->dir); + + return 0; +} + +int gpio_direction_input(unsigned gpio) +{ + return __davinci_direction(gpio, false, 0); +} + +int gpio_direction_output(unsigned gpio, int value) +{ + return __davinci_direction(gpio, true, value); +} + +/* + * Read the pin's value (works even if it's set up as output); + * returns zero/nonzero. + * + * Note that changes are synched to the GPIO clock, so reading values back + * right after you've set them may give old values. + */ +int gpio_get_value(unsigned gpio) +{ + struct davinci_gpio_regs __iomem *g = gpio2regs(gpio); + int shift = gpio % 32; + + if (!g) + return -EINVAL; + + return readl(&g->in_data) & (1 << shift) ? 1 : 0; +} + +/* + * Assuming the pin is muxed as a gpio output, set its output value. + */ +void gpio_set_value(unsigned gpio, int value) +{ + struct davinci_gpio_regs __iomem *g = gpio2regs(gpio); + int shift = gpio % 32; + + if (!g) + return; + + writel((1 << shift), value ? &g->set_data : &g->clr_data); +} diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h new file mode 100644 index 0000000..a71946c --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -0,0 +1,11 @@ +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +#define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio)) + +int gpio_direction_output(unsigned gpio, int value); +int gpio_direction_input(unsigned gpio); +int gpio_get_value(unsigned gpio); +void gpio_set_value(unsigned gpio, int value); + +#endif /* __ASM_ARCH_GPIO_H */ -- 1.7.10 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 03/12] mach-davinci: add pin mux support 2012-06-26 9:51 Add basic support for the OMAP-L138/DA850 Jan Luebbe 2012-06-26 9:51 ` [PATCH 01/12] mach-davinci: add platform and minimal board file for HMI10 Jan Luebbe 2012-06-26 9:51 ` [PATCH 02/12] mach-davinci: add GPIO support Jan Luebbe @ 2012-06-26 9:51 ` Jan Luebbe 2012-06-26 18:59 ` Sascha Hauer 2012-06-26 9:51 ` [PATCH 04/12] mach-davinci: setup pin mux for da850 Jan Luebbe ` (9 subsequent siblings) 12 siblings, 1 reply; 22+ messages in thread From: Jan Luebbe @ 2012-06-26 9:51 UTC (permalink / raw) To: barebox Signed-off-by: Jan Luebbe <jlu@pengutronix.de> --- arch/arm/mach-davinci/Makefile | 1 + arch/arm/mach-davinci/include/mach/mux.h | 74 ++++++++++++++++++++++++++++ arch/arm/mach-davinci/mux.c | 78 ++++++++++++++++++++++++++++++ 3 files changed, 153 insertions(+) create mode 100644 arch/arm/mach-davinci/include/mach/mux.h create mode 100644 arch/arm/mach-davinci/mux.c diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 0a4e2dc..936566e 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -1,3 +1,4 @@ obj-y += clock.o obj-y += clocksource.o obj-y += gpio.o +obj-y += mux.o diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h new file mode 100644 index 0000000..c73a5c0 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -0,0 +1,74 @@ +/* + * Table of the DAVINCI register configurations for the PINMUX combinations + * + * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> + * + * Based on linux/include/asm-arm/arch-omap/mux.h: + * Copyright (C) 2003 - 2005 Nokia Corporation + * + * Written by Tony Lindgren + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Copyright (C) 2008 Texas Instruments. + */ + +#ifndef __INC_MACH_MUX_H +#define __INC_MACH_MUX_H + +struct mux_config { + const char *name; + const char *mux_reg_name; + const unsigned char mux_reg; + const unsigned char mask_offset; + const unsigned char mask; + const unsigned char mode; + int debug; +}; + +#define PINMUX(x) (4 * (x)) + +#define MUX_CFG(soc, desc, muxreg, mode_offset, mode_mask, mux_mode, dbg)\ + { \ + .name = #desc, \ + .debug = dbg, \ + .mux_reg_name = "PINMUX"#muxreg, \ + .mux_reg = PINMUX(muxreg), \ + .mask_offset = mode_offset, \ + .mask = mode_mask, \ + .mode = mux_mode, \ + }, + +#define INT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \ + { \ + .name = #desc, \ + .debug = dbg, \ + .mux_reg_name = "INTMUX", \ + .mux_reg = INTMUX, \ + .mask_offset = mode_offset, \ + .mask = mode_mask, \ + .mode = mux_mode, \ + }, + +#define EVT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \ + { \ + .name = #desc, \ + .debug = dbg, \ + .mux_reg_name = "EVTMUX", \ + .mux_reg = EVTMUX, \ + .mask_offset = mode_offset, \ + .mask = mode_mask, \ + .mode = mux_mode, \ + }, + +#define END_CFG()\ + { \ + .name = NULL, \ + }, + +extern int davinci_cfg_reg_list(const struct mux_config pins[]); + +#endif /* __INC_MACH_MUX_H */ diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c new file mode 100644 index 0000000..40e12f5 --- /dev/null +++ b/arch/arm/mach-davinci/mux.c @@ -0,0 +1,78 @@ +/* + * Utility to set the DAVINCI MUX register from a table in mux.h + * + * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> + * + * Based on linux/arch/arm/plat-omap/mux.c: + * Copyright (C) 2003 - 2005 Nokia Corporation + * + * Written by Tony Lindgren + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Copyright (C) 2008 Texas Instruments. + */ + +#include <config.h> +#include <common.h> +#include <errno.h> +#include <io.h> + +#include <mach/da8xx.h> +#include <mach/mux.h> + +static void *pinmux_base = (void*)DA8XX_SYSCFG0_BASE + 0x120; + +/* + * Sets the DAVINCI MUX register + */ +int davinci_cfg_reg(const struct mux_config *cfg) +{ + unsigned int reg_orig = 0, reg = 0; + unsigned int mask, warn = 0; + + /* Update the mux register in question */ + if (cfg->mask) { + unsigned tmp1, tmp2; + + reg_orig = readl(pinmux_base + cfg->mux_reg); + + mask = (cfg->mask << cfg->mask_offset); + tmp1 = reg_orig & mask; + reg = reg_orig & ~mask; + + tmp2 = (cfg->mode << cfg->mask_offset); + reg |= tmp2; + + if (tmp1 != tmp2) + warn = 1; + + writel(reg, pinmux_base + cfg->mux_reg); + } + + if (warn) { +#ifdef DEBUG + printk("MUX: setting register %s in %s (0x%08x) = 0x%08x -> 0x%08x\n", cfg->name, + cfg->mux_reg_name, (unsigned int)pinmux_base + cfg->mux_reg, reg_orig, reg); +#endif + } + + return 0; +} + +int davinci_cfg_reg_list(const struct mux_config pins[]) +{ + int i, error = -EINVAL; + + if (pins) + for (i = 0; pins[i].name != NULL; i++) { + error = davinci_cfg_reg(&pins[i]); + if (error) + break; + } + + return error; +} -- 1.7.10 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 03/12] mach-davinci: add pin mux support 2012-06-26 9:51 ` [PATCH 03/12] mach-davinci: add pin mux support Jan Luebbe @ 2012-06-26 18:59 ` Sascha Hauer 0 siblings, 0 replies; 22+ messages in thread From: Sascha Hauer @ 2012-06-26 18:59 UTC (permalink / raw) To: Jan Luebbe; +Cc: barebox On Tue, Jun 26, 2012 at 11:51:45AM +0200, Jan Luebbe wrote: > Signed-off-by: Jan Luebbe <jlu@pengutronix.de> > --- > +++ b/arch/arm/mach-davinci/mux.c > @@ -0,0 +1,78 @@ > +/* > + * Utility to set the DAVINCI MUX register from a table in mux.h > + * > + * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> > + * > + * Based on linux/arch/arm/plat-omap/mux.c: > + * Copyright (C) 2003 - 2005 Nokia Corporation > + * > + * Written by Tony Lindgren > + * > + * 2007 (c) MontaVista Software, Inc. This file is licensed under > + * the terms of the GNU General Public License version 2. This program > + * is licensed "as is" without any warranty of any kind, whether express > + * or implied. > + * > + * Copyright (C) 2008 Texas Instruments. > + */ > + > +#include <config.h> > +#include <common.h> > +#include <errno.h> > +#include <io.h> > + > +#include <mach/da8xx.h> > +#include <mach/mux.h> > + > +static void *pinmux_base = (void*)DA8XX_SYSCFG0_BASE + 0x120; > + > +/* > + * Sets the DAVINCI MUX register > + */ > +int davinci_cfg_reg(const struct mux_config *cfg) > +{ > + unsigned int reg_orig = 0, reg = 0; > + unsigned int mask, warn = 0; > + > + /* Update the mux register in question */ > + if (cfg->mask) { > + unsigned tmp1, tmp2; > + > + reg_orig = readl(pinmux_base + cfg->mux_reg); > + > + mask = (cfg->mask << cfg->mask_offset); > + tmp1 = reg_orig & mask; > + reg = reg_orig & ~mask; > + > + tmp2 = (cfg->mode << cfg->mask_offset); > + reg |= tmp2; > + > + if (tmp1 != tmp2) > + warn = 1; Does this 'warn' mean that this function actually changes something? If yes, the variable should better be named 'changed'. > + > + writel(reg, pinmux_base + cfg->mux_reg); > + } > + > + if (warn) { > +#ifdef DEBUG > + printk("MUX: setting register %s in %s (0x%08x) = 0x%08x -> 0x%08x\n", cfg->name, > + cfg->mux_reg_name, (unsigned int)pinmux_base + cfg->mux_reg, reg_orig, reg); > +#endif You can just use the debug() function without ifdefs. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 04/12] mach-davinci: setup pin mux for da850 2012-06-26 9:51 Add basic support for the OMAP-L138/DA850 Jan Luebbe ` (2 preceding siblings ...) 2012-06-26 9:51 ` [PATCH 03/12] mach-davinci: add pin mux support Jan Luebbe @ 2012-06-26 9:51 ` Jan Luebbe 2012-06-26 19:00 ` Sascha Hauer 2012-06-26 9:51 ` [PATCH 05/12] mach-davinci: add support for the PSC (Power and Sleep Controller) Jan Luebbe ` (8 subsequent siblings) 12 siblings, 1 reply; 22+ messages in thread From: Jan Luebbe @ 2012-06-26 9:51 UTC (permalink / raw) To: barebox Signed-off-by: Jan Luebbe <jlu@pengutronix.de> --- arch/arm/mach-davinci/Makefile | 1 + arch/arm/mach-davinci/da850.c | 279 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 280 insertions(+) create mode 100644 arch/arm/mach-davinci/da850.c diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 936566e..d617d9e 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -1,4 +1,5 @@ obj-y += clock.o obj-y += clocksource.o +obj-y += da850.o obj-y += gpio.o obj-y += mux.o diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c new file mode 100644 index 0000000..5d89a87 --- /dev/null +++ b/arch/arm/mach-davinci/da850.c @@ -0,0 +1,279 @@ +/* + * TI DA850/OMAP-L138 chip specific setup + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * Derived from: arch/arm/mach-davinci/da830.c + * Original Copyrights follow: + * + * 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#include <config.h> +#include <common.h> +#include <console.h> +#include <errno.h> +#include <init.h> +#include <mach/mux.h> +#include <mach/gpio.h> + +/* + * Device specific mux setup + * + * soc description mux mode mode mux dbg + * reg offset mask mode + */ +const struct mux_config da850_uart0_pins[] = { + /* UART0 function */ + MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false) + MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false) + MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false) + MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false) + END_CFG() +}; + +const struct mux_config da850_uart1_pins[] = { + /* UART1 function */ + MUX_CFG(DA850, NUART1_CTS, 0, 20, 15, 4, false) + MUX_CFG(DA850, NUART1_RTS, 0, 16, 15, 4, false) + MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false) + MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false) + END_CFG() +}; + +const struct mux_config da850_mcasp_pins[] = { + /* McASP function */ + MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false) + MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false) + MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false) + MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false) + MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false) + MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false) + MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false) + MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false) + MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false) + MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false) + MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false) + MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false) + MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false) + MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false) + MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false) + MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false) + MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false) + MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false) + MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false) + MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false) + MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false) + MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false) + MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false) + END_CFG() +}; + +const struct mux_config da850_mmcsd0_pins[] = { + /* MMC/SD0 function */ + MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false) + MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false) + MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false) + MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false) + MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false) + MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false) + END_CFG() +}; + +const struct mux_config da850_gpio_pins[] = { + /* GPIO function */ + MUX_CFG(DA850, GPIO0_0, 1, 28, 15, 8, false) + MUX_CFG(DA850, GPIO1_12, 2, 12, 15, 4, false) + MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false) + MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false) + MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false) + MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false) + MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false) + MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false) + MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false) + MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false) + MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false) + MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false) + END_CFG() +}; + +const struct mux_config da850_i2c1_pins[] = { + /* I2C1 function */ + MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false) + MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false) + END_CFG() +}; + +const struct mux_config da850_i2c0_pins[] = { + /* I2C0 function */ + MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false) + MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false) + END_CFG() +}; + +const struct mux_config da850_lcdcntl_pins[] = { + /* LCD function */ + MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false) + MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false) + MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false) + MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false) + MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false) + MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false) + MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false) + MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false) + MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false) + MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false) + MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false) + MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false) + MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false) + MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false) + MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false) + MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false) + MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false) + MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false) + MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false) + MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false) + END_CFG() +}; + +static const struct mux_config da850_spi0_pins[] = { + // SPI0 + MUX_CFG(DA850, SPI0_CS_2, 3, 28, 15, 1, false) + MUX_CFG(DA850, SPI0_CS_3, 3, 24, 15, 1, false) + MUX_CFG(DA850, SPI0_CLK, 3, 0, 15, 1, false) + MUX_CFG(DA850, SPI0_SOMI, 3, 8, 15, 1, false) + MUX_CFG(DA850, SPI0_SIMO, 3, 12, 15, 1, false) + END_CFG() + +}; + +static const struct mux_config da850_spi1_pins[] = { + // SPI1 + MUX_CFG(DA850, SPI1_CS_0, 5, 4, 15, 1, false) + MUX_CFG(DA850, SPI1_CS_1, 5, 0, 15, 1, false) + MUX_CFG(DA850, SPI1_CLK, 5, 8, 15, 1, false) + MUX_CFG(DA850, SPI1_SOMI, 5, 16, 15, 1, false) + MUX_CFG(DA850, SPI1_SIMO, 5, 20, 15, 1, false) + END_CFG() +}; + + +static const struct mux_config da850_emifa_pins[] = { + /* EMIF2.5/EMIFA function */ + MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false) + MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false) + MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false) + MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false) + MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false) + MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false) + MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false) + MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false) + MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false) + MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false) + MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false) + MUX_CFG(DA850, NEMA_CS_5, 7, 12, 15, 1, false) + MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false) + MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false) + MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false) + MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false) + MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false) + MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false) + MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false) + MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false) + MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false) + MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false) + MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false) + MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false) + MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false) + MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false) + MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false) + MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false) + MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false) + MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false) + /* + MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false) + MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false) + MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false) + MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false) + MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false) + MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false) + MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false) + MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false) + */ + MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false) + MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false) + MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false) + MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false) + MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false) + MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false) + MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false) + MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false) + MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false) + MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false) + MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false) + END_CFG() +}; + +static const struct mux_config da850_uart2_pins[] = { + /* UART2 function */ + MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false) + MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false) + END_CFG() +}; + +static const struct mux_config da850_emac_pins[] = { + /* EMAC function */ + MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false) + MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false) + MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false) + MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false) + MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false) + MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false) + MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false) + MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false) + MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false) + MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false) + MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false) + MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false) + MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false) + MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false) + MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false) + MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false) + MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false) + MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false) + MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false) + MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false) + MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false) + MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false) + MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false) + MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false) + MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false) + END_CFG() +}; + +static int da8xx_mux_init(void) +{ + if (davinci_cfg_reg_list(da850_uart2_pins)) + printf("mux failed for da850_uart2_pins\n"); + + if (davinci_cfg_reg_list(da850_gpio_pins)) + printf("mux failed for da850_gpio_pins\n"); + + if (davinci_cfg_reg_list(da850_emifa_pins)) + printf("mux failed for da850_emifa_pins\n"); + + if (davinci_cfg_reg_list(da850_spi0_pins)) + printf("mux failed for da850_spi0_pins\n"); + + if (davinci_cfg_reg_list(da850_spi1_pins)) + printf("mux failed for da850_spi1_pins\n"); + + if (davinci_cfg_reg_list(da850_emac_pins)) + printf("mux failed for da850_emac_pins\n"); + + return 0; +} +postconsole_initcall(da8xx_mux_init); -- 1.7.10 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 04/12] mach-davinci: setup pin mux for da850 2012-06-26 9:51 ` [PATCH 04/12] mach-davinci: setup pin mux for da850 Jan Luebbe @ 2012-06-26 19:00 ` Sascha Hauer 0 siblings, 0 replies; 22+ messages in thread From: Sascha Hauer @ 2012-06-26 19:00 UTC (permalink / raw) To: Jan Luebbe; +Cc: barebox On Tue, Jun 26, 2012 at 11:51:46AM +0200, Jan Luebbe wrote: > Signed-off-by: Jan Luebbe <jlu@pengutronix.de> > --- > arch/arm/mach-davinci/Makefile | 1 + > arch/arm/mach-davinci/da850.c | 279 ++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 280 insertions(+) > create mode 100644 arch/arm/mach-davinci/da850.c > > diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile > index 936566e..d617d9e 100644 > --- a/arch/arm/mach-davinci/Makefile > +++ b/arch/arm/mach-davinci/Makefile > @@ -1,4 +1,5 @@ > obj-y += clock.o > obj-y += clocksource.o > +obj-y += da850.o > obj-y += gpio.o > obj-y += mux.o > diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c > new file mode 100644 > index 0000000..5d89a87 > --- /dev/null > +++ b/arch/arm/mach-davinci/da850.c > + > +static int da8xx_mux_init(void) > +{ > + if (davinci_cfg_reg_list(da850_uart2_pins)) > + printf("mux failed for da850_uart2_pins\n"); > + > + if (davinci_cfg_reg_list(da850_gpio_pins)) > + printf("mux failed for da850_gpio_pins\n"); > + > + if (davinci_cfg_reg_list(da850_emifa_pins)) > + printf("mux failed for da850_emifa_pins\n"); > + > + if (davinci_cfg_reg_list(da850_spi0_pins)) > + printf("mux failed for da850_spi0_pins\n"); > + > + if (davinci_cfg_reg_list(da850_spi1_pins)) > + printf("mux failed for da850_spi1_pins\n"); > + > + if (davinci_cfg_reg_list(da850_emac_pins)) > + printf("mux failed for da850_emac_pins\n"); > + > + return 0; > +} > +postconsole_initcall(da8xx_mux_init); Is this really common to all da8xx boards? Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 05/12] mach-davinci: add support for the PSC (Power and Sleep Controller) 2012-06-26 9:51 Add basic support for the OMAP-L138/DA850 Jan Luebbe ` (3 preceding siblings ...) 2012-06-26 9:51 ` [PATCH 04/12] mach-davinci: setup pin mux for da850 Jan Luebbe @ 2012-06-26 9:51 ` Jan Luebbe 2012-06-26 19:02 ` Sascha Hauer 2012-06-26 9:51 ` [PATCH 06/12] mach-davinci: support the USB 1.1 host controller (based on OHCI) Jan Luebbe ` (7 subsequent siblings) 12 siblings, 1 reply; 22+ messages in thread From: Jan Luebbe @ 2012-06-26 9:51 UTC (permalink / raw) To: barebox Signed-off-by: Jan Luebbe <jlu@pengutronix.de> --- arch/arm/mach-davinci/Makefile | 1 + arch/arm/mach-davinci/psc.c | 85 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 86 insertions(+) create mode 100644 arch/arm/mach-davinci/psc.c diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index d617d9e..0ac8f9b 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -3,3 +3,4 @@ obj-y += clocksource.o obj-y += da850.o obj-y += gpio.o obj-y += mux.o +obj-y += psc.o diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c new file mode 100644 index 0000000..88d6182 --- /dev/null +++ b/arch/arm/mach-davinci/psc.c @@ -0,0 +1,85 @@ +/* + * Power and Sleep Controller (PSC) functions. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * Copyright (C) 2008 Lyrtech <www.lyrtech.com> + * Copyright (C) 2004 Texas Instruments. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <io.h> +#include <mach/hardware.h> + +/* + * The PSC manages three inputs to a "module" which may be a peripheral or + * CPU. Those inputs are the module's: clock; reset signal; and sometimes + * its power domain. For our purposes, we only care whether clock and power + * are active, and the module is out of reset. + * + * DaVinci chips may include two separate power domains: "Always On" and "DSP". + * Chips without a DSP generally have only one domain. + * + * The "Always On" power domain is always on when the chip is on, and is + * powered by the VDD pins (on DM644X). The majority of DaVinci modules + * lie within the "Always On" power domain. + * + * A separate domain called the "DSP" domain houses the C64x+ and other video + * hardware such as VICP. In some chips, the "DSP" domain is not always on. + * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X). + */ + +/* Works on Always On power domain only (no PD argument) */ +void lpsc_on(unsigned int id) +{ + dv_reg_p mdstat, mdctl, ptstat, ptcmd; + struct davinci_psc_regs *psc_regs; + + if (id < DAVINCI_LPSC_PSC1_BASE) { + if (id >= PSC_PSC0_MODULE_ID_CNT) + return; + psc_regs = davinci_psc0_regs; + mdstat = &psc_regs->psc0.mdstat[id]; + mdctl = &psc_regs->psc0.mdctl[id]; + } else { + id -= DAVINCI_LPSC_PSC1_BASE; + if (id >= PSC_PSC1_MODULE_ID_CNT) + return; + psc_regs = davinci_psc1_regs; + mdstat = &psc_regs->psc1.mdstat[id]; + mdctl = &psc_regs->psc1.mdctl[id]; + } + ptstat = &psc_regs->ptstat; + ptcmd = &psc_regs->ptcmd; + + while (readl(ptstat) & 0x01) + continue; + + if ((readl(mdstat) & 0x1f) == 0x03) + return; /* Already on and enabled */ + + writel(readl(mdctl) | 0x03, mdctl); + + writel(0x01, ptcmd); + + while (readl(ptstat) & 0x01) + continue; + while ((readl(mdstat) & 0x1f) != 0x03) + continue; +} -- 1.7.10 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 05/12] mach-davinci: add support for the PSC (Power and Sleep Controller) 2012-06-26 9:51 ` [PATCH 05/12] mach-davinci: add support for the PSC (Power and Sleep Controller) Jan Luebbe @ 2012-06-26 19:02 ` Sascha Hauer 0 siblings, 0 replies; 22+ messages in thread From: Sascha Hauer @ 2012-06-26 19:02 UTC (permalink / raw) To: Jan Luebbe; +Cc: barebox On Tue, Jun 26, 2012 at 11:51:47AM +0200, Jan Luebbe wrote: > Signed-off-by: Jan Luebbe <jlu@pengutronix.de> > --- > arch/arm/mach-davinci/Makefile | 1 + > arch/arm/mach-davinci/psc.c | 85 ++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 86 insertions(+) > create mode 100644 arch/arm/mach-davinci/psc.c > > + > +/* Works on Always On power domain only (no PD argument) */ > +void lpsc_on(unsigned int id) better give global functions a clear prefix like davinci_* Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 06/12] mach-davinci: support the USB 1.1 host controller (based on OHCI) 2012-06-26 9:51 Add basic support for the OMAP-L138/DA850 Jan Luebbe ` (4 preceding siblings ...) 2012-06-26 9:51 ` [PATCH 05/12] mach-davinci: add support for the PSC (Power and Sleep Controller) Jan Luebbe @ 2012-06-26 9:51 ` Jan Luebbe 2012-06-26 19:05 ` Sascha Hauer 2012-06-26 9:51 ` [PATCH 07/12] mach-davinci: add support for AEMIF (NAND flash) Jan Luebbe ` (6 subsequent siblings) 12 siblings, 1 reply; 22+ messages in thread From: Jan Luebbe @ 2012-06-26 9:51 UTC (permalink / raw) To: barebox Signed-off-by: Jan Luebbe <jlu@pengutronix.de> --- arch/arm/mach-davinci/Makefile | 1 + arch/arm/mach-davinci/include/mach/usb.h | 37 +++++++++++++++++ arch/arm/mach-davinci/usb.c | 66 ++++++++++++++++++++++++++++++ 3 files changed, 104 insertions(+) create mode 100644 arch/arm/mach-davinci/include/mach/usb.h create mode 100644 arch/arm/mach-davinci/usb.c diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 0ac8f9b..0df1e92 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -4,3 +4,4 @@ obj-y += da850.o obj-y += gpio.o obj-y += mux.o obj-y += psc.o +obj-y += usb.o diff --git a/arch/arm/mach-davinci/include/mach/usb.h b/arch/arm/mach-davinci/include/mach/usb.h new file mode 100644 index 0000000..d0fb412 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/usb.h @@ -0,0 +1,37 @@ +/* + * USB related definitions + * + * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com> + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_USB_H +#define __ASM_ARCH_USB_H + +/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */ +#define CFGCHIP2_PHYCLKGD (1 << 17) +#define CFGCHIP2_VBUSSENSE (1 << 16) +#define CFGCHIP2_RESET (1 << 15) +#define CFGCHIP2_OTGMODE (3 << 13) +#define CFGCHIP2_NO_OVERRIDE (0 << 13) +#define CFGCHIP2_FORCE_HOST (1 << 13) +#define CFGCHIP2_FORCE_DEVICE (2 << 13) +#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13) +#define CFGCHIP2_USB1PHYCLKMUX (1 << 12) +#define CFGCHIP2_USB2PHYCLKMUX (1 << 11) +#define CFGCHIP2_PHYPWRDN (1 << 10) +#define CFGCHIP2_OTGPWRDN (1 << 9) +#define CFGCHIP2_DATPOL (1 << 8) +#define CFGCHIP2_USB1SUSPENDM (1 << 7) +#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */ +#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */ +#define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */ +#define CFGCHIP2_REFFREQ (0xf << 0) +#define CFGCHIP2_REFFREQ_12MHZ (1 << 0) +#define CFGCHIP2_REFFREQ_24MHZ (2 << 0) +#define CFGCHIP2_REFFREQ_48MHZ (3 << 0) + +#endif /* ifndef __ASM_ARCH_USB_H */ diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c new file mode 100644 index 0000000..43dcd37 --- /dev/null +++ b/arch/arm/mach-davinci/usb.c @@ -0,0 +1,66 @@ +#include <common.h> +#include <console.h> +#include <driver.h> +#include <init.h> +#include <io.h> +#include <mach/hardware.h> +#include <mach/usb.h> +#include <mach/da8xx.h> + +#define DA8XX_USB0_BASE 0x01e00000 +#define DA8XX_USB1_BASE 0x01e25000 + +static int da8xx_usb11_init(void) +{ + u32 cfgchip2; + + lpsc_on(DAVINCI_LPSC_USB20); + lpsc_on(DAVINCI_LPSC_USB11); + + /* + * Set up USB clock/mode in the CFGCHIP2 register. + * FYI: CFGCHIP2 is 0x0000ef00 initially. + */ + cfgchip2 = readl(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG); + + /* USB2.0 PHY reference clock is 24 MHz */ + cfgchip2 &= ~CFGCHIP2_REFFREQ; + cfgchip2 |= CFGCHIP2_REFFREQ_24MHZ; + + /* + * Select internal reference clock for USB 2.0 PHY + * and use it as a clock source for USB 1.1 PHY + * (this is the default setting anyway). + */ + cfgchip2 &= ~CFGCHIP2_USB1PHYCLKMUX; + cfgchip2 |= CFGCHIP2_USB2PHYCLKMUX; + + /* + * We have to override VBUS/ID signals when MUSB is configured into the + * host-only mode -- ID pin will float if no cable is connected, so the + * controller won't be able to drive VBUS thinking that it's a B-device. + * Otherwise, we want to use the OTG mode and enable VBUS comparators. + */ + cfgchip2 &= ~CFGCHIP2_OTGMODE; + cfgchip2 |= CFGCHIP2_FORCE_HOST; + + cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN); + cfgchip2 |= CFGCHIP2_PHY_PLLON; + + /* + * Enable USB 1.1 PHY + */ + cfgchip2 |= CFGCHIP2_USB1SUSPENDM; + + writel(cfgchip2, DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG); + + printf("waiting for USB PHY clock...\n"); + while (!(readl(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG) & CFGCHIP2_PHYCLKGD)) + continue; + + add_generic_device("ohci", 0, NULL, DA8XX_USB1_BASE, 0x100, + IORESOURCE_MEM, NULL); + return 0; +} + +device_initcall(da8xx_usb11_init); -- 1.7.10 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 06/12] mach-davinci: support the USB 1.1 host controller (based on OHCI) 2012-06-26 9:51 ` [PATCH 06/12] mach-davinci: support the USB 1.1 host controller (based on OHCI) Jan Luebbe @ 2012-06-26 19:05 ` Sascha Hauer 0 siblings, 0 replies; 22+ messages in thread From: Sascha Hauer @ 2012-06-26 19:05 UTC (permalink / raw) To: Jan Luebbe; +Cc: barebox On Tue, Jun 26, 2012 at 11:51:48AM +0200, Jan Luebbe wrote: > Signed-off-by: Jan Luebbe <jlu@pengutronix.de> > --- > arch/arm/mach-davinci/Makefile | 1 + > arch/arm/mach-davinci/include/mach/usb.h | 37 +++++++++++++++++ > arch/arm/mach-davinci/usb.c | 66 ++++++++++++++++++++++++++++++ > 3 files changed, 104 insertions(+) > create mode 100644 arch/arm/mach-davinci/include/mach/usb.h > create mode 100644 arch/arm/mach-davinci/usb.c > > diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile > index 0ac8f9b..0df1e92 100644 > --- a/arch/arm/mach-davinci/Makefile > +++ b/arch/arm/mach-davinci/Makefile > @@ -4,3 +4,4 @@ obj-y += da850.o > obj-y += gpio.o > obj-y += mux.o > obj-y += psc.o > +obj-y += usb.o > + > +static int da8xx_usb11_init(void) > +{ [...] > + > + add_generic_device("ohci", 0, NULL, DA8XX_USB1_BASE, 0x100, > + IORESOURCE_MEM, NULL); > + return 0; > +} > + > +device_initcall(da8xx_usb11_init); Probably not all boards have this USB port populated. You should probably call this function from board code. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 07/12] mach-davinci: add support for AEMIF (NAND flash) 2012-06-26 9:51 Add basic support for the OMAP-L138/DA850 Jan Luebbe ` (5 preceding siblings ...) 2012-06-26 9:51 ` [PATCH 06/12] mach-davinci: support the USB 1.1 host controller (based on OHCI) Jan Luebbe @ 2012-06-26 9:51 ` Jan Luebbe 2012-06-26 9:51 ` [PATCH 08/12] drivers/mtd/nand: add driver for the davinci NAND flash controller Jan Luebbe ` (5 subsequent siblings) 12 siblings, 0 replies; 22+ messages in thread From: Jan Luebbe @ 2012-06-26 9:51 UTC (permalink / raw) To: barebox Signed-off-by: Jan Luebbe <jlu@pengutronix.de> --- arch/arm/mach-davinci/Makefile | 1 + arch/arm/mach-davinci/aemif.c | 128 ++++++++++++++++++++++++++++ arch/arm/mach-davinci/include/mach/aemif.h | 36 ++++++++ 3 files changed, 165 insertions(+) create mode 100644 arch/arm/mach-davinci/aemif.c create mode 100644 arch/arm/mach-davinci/include/mach/aemif.h diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 0df1e92..2c35ca0 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -1,3 +1,4 @@ +obj-y += aemif.o obj-y += clock.o obj-y += clocksource.o obj-y += da850.o diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c new file mode 100644 index 0000000..1468899 --- /dev/null +++ b/arch/arm/mach-davinci/aemif.c @@ -0,0 +1,128 @@ +/* + * AEMIF support for DaVinci SoCs + * + * Copyright (C) 2010 Texas Instruments Incorporated. http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <common.h> +#include <errno.h> +#include <io.h> + +#include <mach/hardware.h> +#include <mach/aemif.h> + +#define NSEC_PER_MSEC (1000*1000) + +/* Timing value configuration */ + +#define TA(x) ((x) << 2) +#define RHOLD(x) ((x) << 4) +#define RSTROBE(x) ((x) << 7) +#define RSETUP(x) ((x) << 13) +#define WHOLD(x) ((x) << 17) +#define WSTROBE(x) ((x) << 20) +#define WSETUP(x) ((x) << 26) + +#define TA_MAX 0x3 +#define RHOLD_MAX 0x7 +#define RSTROBE_MAX 0x3f +#define RSETUP_MAX 0xf +#define WHOLD_MAX 0x7 +#define WSTROBE_MAX 0x3f +#define WSETUP_MAX 0xf + +#define TIMING_MASK (TA(TA_MAX) | \ + RHOLD(RHOLD_MAX) | \ + RSTROBE(RSTROBE_MAX) | \ + RSETUP(RSETUP_MAX) | \ + WHOLD(WHOLD_MAX) | \ + WSTROBE(WSTROBE_MAX) | \ + WSETUP(WSETUP_MAX)) + +/* + * aemif_calc_rate - calculate timing data. + * @wanted: The cycle time needed in nanoseconds. + * @clk: The input clock rate in kHz. + * @max: The maximum divider value that can be programmed. + * + * On success, returns the calculated timing value minus 1 for easy + * programming into AEMIF timing registers, else negative errno. + */ +static int aemif_calc_rate(int wanted, unsigned long clk, int max) +{ + int result; + + result = DIV_ROUND_UP((wanted * clk), NSEC_PER_MSEC) - 1; + + pr_debug("%s: result %d from %ld, %d\n", __func__, result, clk, wanted); + + /* It is generally OK to have a more relaxed timing than requested... */ + if (result < 0) + result = 0; + + /* ... But configuring tighter timings is not an option. */ + else if (result > max) + result = -EINVAL; + + return result; +} + +/** + * davinci_aemif_setup_timing - setup timing values for a given AEMIF interface + * @t: timing values to be progammed + * @base: The virtual base address of the AEMIF interface + * @cs: chip-select to program the timing values for + * + * This function programs the given timing values (in real clock) into the + * AEMIF registers taking the AEMIF clock into account. + * + * This function does not use any locking while programming the AEMIF + * because it is expected that there is only one user of a given + * chip-select. + * + * Returns 0 on success, else negative errno. + */ +int davinci_aemif_setup_timing(struct davinci_aemif_timing *t, + void __iomem *base, unsigned cs) +{ + unsigned set, val; + int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; + unsigned offset = A1CR_OFFSET + cs * 4; + unsigned long clkrate; + + if (!t) + return 0; /* Nothing to do */ + + clkrate = da8xx_clk_get(DAVINCI_EMIFA_CLKID); + + clkrate /= 1000; /* turn clock into kHz for ease of use */ + + ta = aemif_calc_rate(t->ta, clkrate, TA_MAX); + rhold = aemif_calc_rate(t->rhold, clkrate, RHOLD_MAX); + rstrobe = aemif_calc_rate(t->rstrobe, clkrate, RSTROBE_MAX); + rsetup = aemif_calc_rate(t->rsetup, clkrate, RSETUP_MAX); + whold = aemif_calc_rate(t->whold, clkrate, WHOLD_MAX); + wstrobe = aemif_calc_rate(t->wstrobe, clkrate, WSTROBE_MAX); + wsetup = aemif_calc_rate(t->wsetup, clkrate, WSETUP_MAX); + + if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 || + whold < 0 || wstrobe < 0 || wsetup < 0) { + pr_err("%s: cannot get suitable timings\n", __func__); + return -EINVAL; + } + + set = TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) | + WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup); + + val = readl(base + offset); + val &= ~TIMING_MASK; + val |= set; + writel(val, base + offset); + + return 0; +} +EXPORT_SYMBOL(davinci_aemif_setup_timing); diff --git a/arch/arm/mach-davinci/include/mach/aemif.h b/arch/arm/mach-davinci/include/mach/aemif.h new file mode 100644 index 0000000..05b2934 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/aemif.h @@ -0,0 +1,36 @@ +/* + * TI DaVinci AEMIF support + * + * Copyright 2010 (C) Texas Instruments, Inc. http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ +#ifndef _MACH_DAVINCI_AEMIF_H +#define _MACH_DAVINCI_AEMIF_H + +#define NRCSR_OFFSET 0x00 +#define AWCCR_OFFSET 0x04 +#define A1CR_OFFSET 0x10 + +#define ACR_ASIZE_MASK 0x3 +#define ACR_EW_MASK BIT(30) +#define ACR_SS_MASK BIT(31) + +/* All timings in nanoseconds */ +struct davinci_aemif_timing { + u8 wsetup; + u8 wstrobe; + u8 whold; + + u8 rsetup; + u8 rstrobe; + u8 rhold; + + u8 ta; +}; + +int davinci_aemif_setup_timing(struct davinci_aemif_timing *t, + void __iomem *base, unsigned cs); +#endif -- 1.7.10 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 08/12] drivers/mtd/nand: add driver for the davinci NAND flash controller 2012-06-26 9:51 Add basic support for the OMAP-L138/DA850 Jan Luebbe ` (6 preceding siblings ...) 2012-06-26 9:51 ` [PATCH 07/12] mach-davinci: add support for AEMIF (NAND flash) Jan Luebbe @ 2012-06-26 9:51 ` Jan Luebbe 2012-06-26 19:19 ` Sascha Hauer 2012-06-26 9:51 ` [PATCH 09/12] board hmi10: enable support for NAND Jan Luebbe ` (4 subsequent siblings) 12 siblings, 1 reply; 22+ messages in thread From: Jan Luebbe @ 2012-06-26 9:51 UTC (permalink / raw) To: barebox Signed-off-by: Jan Luebbe <jlu@pengutronix.de> --- arch/arm/mach-davinci/include/mach/emif_defs.h | 76 +++ arch/arm/mach-davinci/include/mach/nand.h | 46 ++ arch/arm/mach-davinci/include/mach/nand_defs.h | 43 ++ drivers/mtd/nand/Kconfig | 5 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/davinci_nand.c | 670 ++++++++++++++++++++++++ drivers/mtd/nand/nand_base.c | 4 + include/linux/mtd/nand.h | 1 + 8 files changed, 846 insertions(+) create mode 100644 arch/arm/mach-davinci/include/mach/emif_defs.h create mode 100644 arch/arm/mach-davinci/include/mach/nand.h create mode 100644 arch/arm/mach-davinci/include/mach/nand_defs.h create mode 100644 drivers/mtd/nand/davinci_nand.c diff --git a/arch/arm/mach-davinci/include/mach/emif_defs.h b/arch/arm/mach-davinci/include/mach/emif_defs.h new file mode 100644 index 0000000..3ad0d0f --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/emif_defs.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _EMIF_DEFS_H_ +#define _EMIF_DEFS_H_ + +#include <mach/hardware.h> + +typedef struct { + dv_reg ERCSR; + dv_reg AWCCR; + dv_reg SDBCR; + dv_reg SDRCR; + dv_reg AB1CR; + dv_reg AB2CR; + dv_reg AB3CR; + dv_reg AB4CR; + dv_reg SDTIMR; + dv_reg DDRSR; + dv_reg DDRPHYCR; + dv_reg DDRPHYSR; + dv_reg TOTAR; + dv_reg TOTACTR; + dv_reg DDRPHYID_REV; + dv_reg SDSRETR; + dv_reg EIRR; + dv_reg EIMR; + dv_reg EIMSR; + dv_reg EIMCR; + dv_reg IOCTRLR; + dv_reg IOSTATR; + u_int8_t RSVD0[8]; + dv_reg NANDFCR; + dv_reg NANDFSR; + u_int8_t RSVD1[8]; + dv_reg NANDFECC[4]; + u_int8_t RSVD2[60]; + dv_reg NAND4BITECCLOAD; + dv_reg NAND4BITECC1; + dv_reg NAND4BITECC2; + dv_reg NAND4BITECC3; + dv_reg NAND4BITECC4; + dv_reg NANDERRADD1; + dv_reg NANDERRADD2; + dv_reg NANDERRVAL1; + dv_reg NANDERRVAL2; +} emif_registers; + +typedef emif_registers *emifregs; + +#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2)) +#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) +#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4) +#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2))) +#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) +#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) + +#endif diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h new file mode 100644 index 0000000..3ef652b --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/nand.h @@ -0,0 +1,46 @@ +/* + * mach-davinci/nand.h + * + * Copyright © 2006 Texas Instruments. + * + * Ported to 2.6.23 Copyright © 2008 by + * Sander Huijsen <Shuijsen@optelecom-nkf.com> + * Troy Kisky <troy.kisky@boundarydevices.com> + * Dirk Behme <Dirk.Behme@gmail.com> + * + * -------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ARCH_ARM_DAVINCI_NAND_H +#define __ARCH_ARM_DAVINCI_NAND_H + +#include <linux/mtd/nand.h> + +#include <mach/aemif.h> + +struct davinci_nand_pdata { /* platform_data */ + nand_ecc_modes_t ecc_mode; + u8 ecc_bits; + + /* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */ + unsigned options; + + /* Access timings */ + struct davinci_aemif_timing *timing; +}; + +#endif /* __ARCH_ARM_DAVINCI_NAND_H */ diff --git a/arch/arm/mach-davinci/include/mach/nand_defs.h b/arch/arm/mach-davinci/include/mach/nand_defs.h new file mode 100644 index 0000000..e917aa9 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/nand_defs.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Parts shamelesly stolen from Linux Kernel source tree. + * + * ------------------------------------------------------------ + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _NAND_DEFS_H_ +#define _NAND_DEFS_H_ + +#include <mach/hardware.h> + +#ifdef CONFIG_SOC_DM646X +#define MASK_CLE 0x80000 +#define MASK_ALE 0x40000 +#else +#define MASK_CLE 0x10 +#define MASK_ALE 0x08 +#endif + +#define NAND_READ_START 0x00 +#define NAND_READ_END 0x30 +#define NAND_STATUS 0x70 + +#endif diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 926a64b..b53cfeb 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -65,6 +65,11 @@ config NAND_ATMEL prompt "Atmel (AT91SAM9xxx) NAND driver" depends on ARCH_AT91 +config NAND_DAVINCI + bool + prompt "TI Davinci NAND driver" + depends on ARCH_DAVINCI + config NAND_S3C24XX bool prompt "Samsung S3C24XX NAND driver" diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 5c6d8b3..39a8551 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -14,4 +14,5 @@ obj-$(CONFIG_MTD_NAND_NOMADIK) += nomadik_nand.o obj-$(CONFIG_NAND_IMX) += nand_imx.o obj-$(CONFIG_NAND_OMAP_GPMC) += nand_omap_gpmc.o nand_omap_bch_decoder.o obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o +obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o obj-$(CONFIG_NAND_S3C24XX) += nand_s3c24xx.o diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c new file mode 100644 index 0000000..6dd5b48 --- /dev/null +++ b/drivers/mtd/nand/davinci_nand.c @@ -0,0 +1,670 @@ +/* + * NAND driver for TI DaVinci based boards. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Based on Linux DaVinci NAND driver by TI. Original copyright follows: + */ + +/* + * + * linux/drivers/mtd/nand/nand_davinci.c + * + * NAND Flash Driver + * + * Copyright (C) 2006 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + * + * Overview: + * This is a device driver for the NAND flash device found on the + * DaVinci board which utilizes the Samsung k9k2g08 part. + * + Modifications: + ver. 1.0: Feb 2005, Vinod/Sudhakar + - + * + */ + +#define CONFIG_SYS_NAND_CS 3 +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_PAGE_2K + +#include <config.h> +#include <common.h> +#include <driver.h> +#include <malloc.h> +#include <init.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <io.h> +#include <asm-generic/errno.h> +#include <mach/aemif.h> +#include <mach/nand.h> +#include <mach/nand_defs.h> +#include <mach/emif_defs.h> + +/* Definitions for 4-bit hardware ECC */ +#define NAND_TIMEOUT 10240 +#define NAND_ECC_BUSY 0xC +#define NAND_4BITECC_MASK 0x03FF03FF +#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00 +#define ECC_STATE_NO_ERR 0x0 +#define ECC_STATE_TOO_MANY_ERRS 0x1 +#define ECC_STATE_ERR_CORR_COMP_P 0x2 +#define ECC_STATE_ERR_CORR_COMP_N 0x3 + +static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE; + +struct davinci_nand_host { + struct mtd_info mtd; + struct nand_chip nand; + struct mtd_partition *parts; + struct device_d *dev; + + void __iomem *base; +}; + +/* + * Exploit the little endianness of the ARM to do multi-byte transfers + * per device read. This can perform over twice as quickly as individual + * byte transfers when buffer alignment is conducive. + * + * NOTE: This only works if the NAND is not connected to the 2 LSBs of + * the address bus. On Davinci EVM platforms this has always been true. + */ +static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + const u32 *nand = chip->IO_ADDR_R; + + /* Make sure that buf is 32 bit aligned */ + if (((int)buf & 0x3) != 0) { + if (((int)buf & 0x1) != 0) { + if (len) { + *buf = readb(nand); + buf += 1; + len--; + } + } + + if (((int)buf & 0x3) != 0) { + if (len >= 2) { + *(u16 *)buf = readw(nand); + buf += 2; + len -= 2; + } + } + } + + /* copy aligned data */ + while (len >= 4) { + *(u32 *)buf = readl(nand); + buf += 4; + len -= 4; + } + + /* mop up any remaining bytes */ + if (len) { + if (len >= 2) { + *(u16 *)buf = readw(nand); + buf += 2; + len -= 2; + } + + if (len) + *buf = readb(nand); + } +} + +static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf, + int len) +{ + struct nand_chip *chip = mtd->priv; + const u32 *nand = chip->IO_ADDR_W; + + /* Make sure that buf is 32 bit aligned */ + if (((int)buf & 0x3) != 0) { + if (((int)buf & 0x1) != 0) { + if (len) { + writeb(*buf, nand); + buf += 1; + len--; + } + } + + if (((int)buf & 0x3) != 0) { + if (len >= 2) { + writew(*(u16 *)buf, nand); + buf += 2; + len -= 2; + } + } + } + + /* copy aligned data */ + while (len >= 4) { + writel(*(u32 *)buf, nand); + buf += 4; + len -= 4; + } + + /* mop up any remaining bytes */ + if (len) { + if (len >= 2) { + writew(*(u16 *)buf, nand); + buf += 2; + len -= 2; + } + + if (len) + writeb(*buf, nand); + } +} + +static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W; + + if (ctrl & NAND_CTRL_CHANGE) { + IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); + + if ( ctrl & NAND_CLE ) + IO_ADDR_W |= MASK_CLE; + if ( ctrl & NAND_ALE ) + IO_ADDR_W |= MASK_ALE; + this->IO_ADDR_W = (void __iomem *) IO_ADDR_W; + } + + //printf("nand_davinci_hwcontrol cmd 0x%02x -> addr 0x%08x\n", cmd, IO_ADDR_W); + if (cmd != NAND_CMD_NONE) + writeb(cmd, IO_ADDR_W); +} + +#ifdef CONFIG_SYS_NAND_HW_ECC + +static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) +{ + u_int32_t val; + + printf("nand_davinci_enable_hwecc\n"); + + (void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2])); + + val = readl(&emif_regs->NANDFCR); + val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS); + writel(val, &emif_regs->NANDFCR); +} + +static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) +{ + u_int32_t ecc = 0; + + ecc = readl(&(emif_regs->NANDFECC[region - 1])); + + return(ecc); +} + +static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) +{ + u_int32_t tmp; + const int region = 1; + + tmp = nand_davinci_readecc(mtd, region); + + /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits + * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */ + tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4); + + /* Invert so that erased block ECC is correct */ + tmp = ~tmp; + + *ecc_code++ = tmp; + *ecc_code++ = tmp >> 8; + *ecc_code++ = tmp >> 16; + + /* NOTE: the above code matches mainline Linux: + * .PQR.stu ==> ~PQRstu + * + * MontaVista/TI kernels encode those bytes differently, use + * complicated (and allegedly sometimes-wrong) correction code, + * and usually shipped with U-Boot that uses software ECC: + * .PQR.stu ==> PsQRtu + * + * If you need MV/TI compatible NAND I/O in U-Boot, it should + * be possible to (a) change the mangling above, (b) reverse + * that mangling in nand_davinci_correct_data() below. + */ + + return 0; +} + +static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) +{ + struct nand_chip *this = mtd->priv; + u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) | + (read_ecc[2] << 16); + u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) | + (calc_ecc[2] << 16); + u_int32_t diff = ecc_calc ^ ecc_nand; + + if (diff) { + if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) { + /* Correctable error */ + if ((diff >> (12 + 3)) < this->ecc.size) { + uint8_t find_bit = 1 << ((diff >> 12) & 7); + uint32_t find_byte = diff >> (12 + 3); + + dat[find_byte] ^= find_bit; + MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single " + "bit ECC error at offset: %d, bit: " + "%d\n", find_byte, find_bit); + return 1; + } else { + return -1; + } + } else if (!(diff & (diff - 1))) { + /* Single bit ECC error in the ECC itself, + nothing to fix */ + MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in " + "ECC.\n"); + return 1; + } else { + /* Uncorrectable error */ + MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n"); + return -1; + } + } + return(0); +} +#endif /* CONFIG_SYS_NAND_HW_ECC */ + +#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = { +#if defined(CONFIG_SYS_NAND_PAGE_2K) + .eccbytes = 40, + .eccpos = {6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, + }, + .oobfree = {{2, 4}, {16, 6}, {32, 6}, {48, 6}, +/* + .eccpos = { + 24, 25, 26, 27, 28, + 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, + 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, + 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, + 59, 60, 61, 62, 63, + }, + .oobfree = { + {.offset = 2, .length = 22, }, +*/ + }, +#elif defined(CONFIG_SYS_NAND_PAGE_4K) + .eccbytes = 80, + .eccpos = { + 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, + 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, + 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, + 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, + 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, + 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, + 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, + }, + .oobfree = { + {.offset = 2, .length = 46, }, + }, +#endif +}; + +static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode) +{ + u32 val; + + //printf("nand_davinci_4bit_enable_hwecc\n"); + + switch (mode) { + case NAND_ECC_WRITE: + case NAND_ECC_READ: + /* + * Start a new ECC calculation for reading or writing 512 bytes + * of data. + */ + val = readl(&emif_regs->NANDFCR); + val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK; + val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_4BIT_ECC_START; + writel(val, &emif_regs->NANDFCR); + break; + case NAND_ECC_READSYN: + val = emif_regs->NAND4BITECC1; + break; + default: + break; + } +} + +static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4]) +{ + ecc[0] = emif_regs->NAND4BITECC1 & NAND_4BITECC_MASK; + ecc[1] = emif_regs->NAND4BITECC2 & NAND_4BITECC_MASK; + ecc[2] = emif_regs->NAND4BITECC3 & NAND_4BITECC_MASK; + ecc[3] = emif_regs->NAND4BITECC4 & NAND_4BITECC_MASK; + + return 0; +} + +static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd, + const uint8_t *dat, + uint8_t *ecc_code) +{ + unsigned int hw_4ecc[4]; + unsigned int i; + + nand_davinci_4bit_readecc(mtd, hw_4ecc); + + /*Convert 10 bit ecc value to 8 bit */ + for (i = 0; i < 2; i++) { + unsigned int hw_ecc_low = hw_4ecc[i * 2]; + unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1]; + + /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */ + *ecc_code++ = hw_ecc_low & 0xFF; + + /* + * Take 2 bits as LSB bits from val1 (count1=0) or val5 + * (count1=1) and 6 bits from val2 (count1=0) or + * val5 (count1=1) + */ + *ecc_code++ = + ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC); + + /* + * Take 4 bits from val2 (count1=0) or val5 (count1=1) and + * 4 bits from val3 (count1=0) or val6 (count1=1) + */ + *ecc_code++ = + ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0); + + /* + * Take 6 bits from val3(count1=0) or val6 (count1=1) and + * 2 bits from val4 (count1=0) or val7 (count1=1) + */ + *ecc_code++ = + ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0); + + /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */ + *ecc_code++ = (hw_ecc_hi >> 18) & 0xFF; + } + + return 0; +} + +static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat, + uint8_t *read_ecc, uint8_t *calc_ecc) +{ + int i; + unsigned int hw_4ecc[4]; + unsigned int iserror; + unsigned short *ecc16; + unsigned int numerrors, erroraddress, errorvalue; + u32 val; + + /* + * Check for an ECC where all bytes are 0xFF. If this is the case, we + * will assume we are looking at an erased page and we should ignore + * the ECC. + */ + for (i = 0; i < 10; i++) { + if (read_ecc[i] != 0xFF) + break; + } + if (i == 10) + return 0; + + /* Convert 8 bit in to 10 bit */ + ecc16 = (unsigned short *)&read_ecc[0]; + + /* + * Write the parity values in the NAND Flash 4-bit ECC Load register. + * Write each parity value one at a time starting from 4bit_ecc_val8 + * to 4bit_ecc_val1. + */ + + /*Take 2 bits from 8th byte and 8 bits from 9th byte */ + writel(((ecc16[4]) >> 6) & 0x3FF, &emif_regs->NAND4BITECCLOAD); + + /* Take 4 bits from 7th byte and 6 bits from 8th byte */ + writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0), + &emif_regs->NAND4BITECCLOAD); + + /* Take 6 bits from 6th byte and 4 bits from 7th byte */ + writel((ecc16[3] >> 2) & 0x3FF, &emif_regs->NAND4BITECCLOAD); + + /* Take 8 bits from 5th byte and 2 bits from 6th byte */ + writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300), + &emif_regs->NAND4BITECCLOAD); + + /*Take 2 bits from 3rd byte and 8 bits from 4th byte */ + writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC), + &emif_regs->NAND4BITECCLOAD); + + /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */ + writel(((ecc16[1]) >> 4) & 0x3FF, &emif_regs->NAND4BITECCLOAD); + + /* Take 6 bits from 1st byte and 4 bits from 2nd byte */ + writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0), + &emif_regs->NAND4BITECCLOAD); + + /* Take 10 bits from 0th and 1st bytes */ + writel((ecc16[0]) & 0x3FF, &emif_regs->NAND4BITECCLOAD); + + /* + * Perform a dummy read to the EMIF Revision Code and Status register. + * This is required to ensure time for syndrome calculation after + * writing the ECC values in previous step. + */ + + val = emif_regs->NANDFSR; + + /* + * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers. + * A syndrome value of 0 means no bit errors. If the syndrome is + * non-zero then go further otherwise return. + */ + nand_davinci_4bit_readecc(mtd, hw_4ecc); + + if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3])) + return 0; + + /* + * Clear any previous address calculation by doing a dummy read of an + * error address register. + */ + val = emif_regs->NANDERRADD1; + + /* + * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control + * register to 1. + */ + emif_regs->NANDFCR |= 1 << 13; + + /* + * Wait for the corr_state field (bits 8 to 11)in the + * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3. + */ + i = NAND_TIMEOUT; + do { + val = emif_regs->NANDFSR; + val &= 0xc00; + i--; + } while ((i > 0) && val); + + iserror = emif_regs->NANDFSR; + iserror &= EMIF_NANDFSR_ECC_STATE_MASK; + iserror = iserror >> 8; + + /* + * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be + * corrected (five or more errors). The number of errors + * calculated (err_num field) differs from the number of errors + * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error + * correction complete (errors on bit 8 or 9). + * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction + * complete (error exists). + */ + + if (iserror == ECC_STATE_NO_ERR) { + val = emif_regs->NANDERRVAL1; + return 0; + } else if (iserror == ECC_STATE_TOO_MANY_ERRS) { + val = emif_regs->NANDERRVAL1; + return -1; + } + + numerrors = ((emif_regs->NANDFSR >> 16) & 0x3) + 1; + + /* Read the error address, error value and correct */ + for (i = 0; i < numerrors; i++) { + if (i > 1) { + erroraddress = + ((emif_regs->NANDERRADD2 >> + (16 * (i & 1))) & 0x3FF); + erroraddress = ((512 + 7) - erroraddress); + errorvalue = + ((emif_regs->NANDERRVAL2 >> + (16 * (i & 1))) & 0xFF); + } else { + erroraddress = + ((emif_regs->NANDERRADD1 >> + (16 * (i & 1))) & 0x3FF); + erroraddress = ((512 + 7) - erroraddress); + errorvalue = + ((emif_regs->NANDERRVAL1 >> + (16 * (i & 1))) & 0xFF); + } + /* xor the corrupt data with error value */ + if (erroraddress < 512) + dat[erroraddress] ^= errorvalue; + } + + return numerrors; +} +#endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */ + +static int nand_davinci_dev_ready(struct mtd_info *mtd) +{ + return emif_regs->NANDFSR & 0x1; +} + +static int davinci_nand_probe(struct device_d *dev) +{ + struct nand_chip *chip; + struct davinci_nand_pdata *pdata = dev->platform_data; + struct mtd_info *mtd; + struct davinci_nand_host *host; + u32 val; + int ret; + + /* Allocate memory for MTD device structure and private data */ + host = kzalloc(sizeof(struct davinci_nand_host), GFP_KERNEL); + if (!host) + return -ENOMEM; + + host->dev = dev; + host->base = dev_request_mem_region(dev, 0); + + /* structures must be linked */ + chip = &host->nand; + chip->priv = host; + mtd = &host->mtd; + mtd->priv = chip; + + chip->chip_delay = 0; + chip->IO_ADDR_R = (void *)DAVINCI_ASYNC_EMIF_DATA_CE3_BASE; + chip->IO_ADDR_W = (void *)DAVINCI_ASYNC_EMIF_DATA_CE3_BASE; + +#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT + chip->options |= NAND_USE_FLASH_BBT; +#endif +#ifdef CONFIG_SYS_NAND_HW_ECC + chip->ecc.mode = NAND_ECC_HW; + chip->ecc.size = 512; + chip->ecc.bytes = 3; + chip->ecc.calculate = nand_davinci_calculate_ecc; + chip->ecc.correct = nand_davinci_correct_data; + chip->ecc.hwctl = nand_davinci_enable_hwecc; +#else + chip->ecc.mode = NAND_ECC_SOFT; +#endif /* CONFIG_SYS_NAND_HW_ECC */ +#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST + dev_dbg(dev, "using obbfirst\n"); + chip->ecc.mode = NAND_ECC_HW_OOB_FIRST; + chip->ecc.size = 512; + chip->ecc.bytes = 10; + chip->ecc.calculate = nand_davinci_4bit_calculate_ecc; + chip->ecc.correct = nand_davinci_4bit_correct_data; + chip->ecc.hwctl = nand_davinci_4bit_enable_hwecc; + chip->ecc.layout = &nand_davinci_4bit_layout_oobfirst; +#endif + /* Set address of hardware control function */ + chip->cmd_ctrl = nand_davinci_hwcontrol; + + chip->read_buf = nand_davinci_read_buf; + chip->write_buf = nand_davinci_write_buf; + + chip->dev_ready = nand_davinci_dev_ready; + + davinci_aemif_setup_timing(pdata->timing, (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE, 3-2); + + ///* put CSxNAND into NAND mode */ + val = readl(&emif_regs->NANDFCR); + val |= BIT(3-2); + writel(val, &emif_regs->NANDFCR); + + /* Scan to find existence of the device */ + ret = nand_scan(mtd, 1); + if (ret != 0) { + ret = -ENXIO; + goto on_error; + } + + return add_mtd_device(mtd, "nand"); + +on_error: + free(host); + return ret; +} + +static struct driver_d davinci_nand_driver = { + .name = "davinci_nand", + .probe = davinci_nand_probe, +}; + +static int __init davinci_nand_init(void) +{ + return register_driver(&davinci_nand_driver); +} + +device_initcall(davinci_nand_init); diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index c4eca0d..65ba1e6 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -1344,6 +1344,10 @@ int nand_scan_tail(struct mtd_info *mtd) chip->ecc.bytes = 0; break; #endif + case NAND_ECC_HW_OOB_FIRST: + nand_check_hwecc(mtd, chip); + nand_init_ecc_hw_syndrome(chip); + break; default: printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n", chip->ecc.mode); diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 2a1c4ff..c835832 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -123,6 +123,7 @@ typedef enum { NAND_ECC_SOFT, NAND_ECC_HW, NAND_ECC_HW_SYNDROME, + NAND_ECC_HW_OOB_FIRST, } nand_ecc_modes_t; /* -- 1.7.10 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 08/12] drivers/mtd/nand: add driver for the davinci NAND flash controller 2012-06-26 9:51 ` [PATCH 08/12] drivers/mtd/nand: add driver for the davinci NAND flash controller Jan Luebbe @ 2012-06-26 19:19 ` Sascha Hauer 0 siblings, 0 replies; 22+ messages in thread From: Sascha Hauer @ 2012-06-26 19:19 UTC (permalink / raw) To: Jan Luebbe; +Cc: barebox On Tue, Jun 26, 2012 at 11:51:50AM +0200, Jan Luebbe wrote: > Signed-off-by: Jan Luebbe <jlu@pengutronix.de> > --- > + dv_reg NANDERRVAL1; > + dv_reg NANDERRVAL2; > +} emif_registers; > + > +typedef emif_registers *emifregs; Do not typedef structs please. > diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c > +static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) > +{ > + struct nand_chip *this = mtd->priv; > + u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W; > + > + if (ctrl & NAND_CTRL_CHANGE) { > + IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); > + > + if ( ctrl & NAND_CLE ) > + IO_ADDR_W |= MASK_CLE; > + if ( ctrl & NAND_ALE ) > + IO_ADDR_W |= MASK_ALE; > + this->IO_ADDR_W = (void __iomem *) IO_ADDR_W; > + } > + > + //printf("nand_davinci_hwcontrol cmd 0x%02x -> addr 0x%08x\n", cmd, IO_ADDR_W); No C++ comments please. Can either be removed or use debug() > + (void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2])); > + > + val = readl(&emif_regs->NANDFCR); > + val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); > + val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS); > + writel(val, &emif_regs->NANDFCR); > +} > + > +static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) > +{ > + u_int32_t ecc = 0; No need to initialize this variable. > + > + ecc = readl(&(emif_regs->NANDFECC[region - 1])); > + > + return(ecc); return is not a function. > + "ECC.\n"); > + return 1; > + } else { > + /* Uncorrectable error */ > + MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n"); > + return -1; > + } > + } > + return(0); return is not a function > +static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode) > +{ > + u32 val; > + > + //printf("nand_davinci_4bit_enable_hwecc\n"); debug() or remove > +static int nand_davinci_dev_ready(struct mtd_info *mtd) > +{ > + return emif_regs->NANDFSR & 0x1; readl? > +} > + > +static int davinci_nand_probe(struct device_d *dev) > +{ > + struct nand_chip *chip; > + struct davinci_nand_pdata *pdata = dev->platform_data; > + struct mtd_info *mtd; > + struct davinci_nand_host *host; > + u32 val; > + int ret; > + > + /* Allocate memory for MTD device structure and private data */ > + host = kzalloc(sizeof(struct davinci_nand_host), GFP_KERNEL); > + if (!host) > + return -ENOMEM; > + > + host->dev = dev; > + host->base = dev_request_mem_region(dev, 0); > + > + /* structures must be linked */ > + chip = &host->nand; > + chip->priv = host; > + mtd = &host->mtd; > + mtd->priv = chip; > + > + chip->chip_delay = 0; > + chip->IO_ADDR_R = (void *)DAVINCI_ASYNC_EMIF_DATA_CE3_BASE; > + chip->IO_ADDR_W = (void *)DAVINCI_ASYNC_EMIF_DATA_CE3_BASE; > + > +#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT move to platform data > + chip->options |= NAND_USE_FLASH_BBT; > +#endif > +#ifdef CONFIG_SYS_NAND_HW_ECC ditto > + chip->ecc.mode = NAND_ECC_HW; > + chip->ecc.size = 512; > + chip->ecc.bytes = 3; > + chip->ecc.calculate = nand_davinci_calculate_ecc; > + chip->ecc.correct = nand_davinci_correct_data; > + chip->ecc.hwctl = nand_davinci_enable_hwecc; > +#else > + chip->ecc.mode = NAND_ECC_SOFT; > +#endif /* CONFIG_SYS_NAND_HW_ECC */ > +#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST ditto > + dev_dbg(dev, "using obbfirst\n"); > + chip->ecc.mode = NAND_ECC_HW_OOB_FIRST; > + chip->ecc.size = 512; > + chip->ecc.bytes = 10; > + chip->ecc.calculate = nand_davinci_4bit_calculate_ecc; > + chip->ecc.correct = nand_davinci_4bit_correct_data; > + chip->ecc.hwctl = nand_davinci_4bit_enable_hwecc; > + chip->ecc.layout = &nand_davinci_4bit_layout_oobfirst; > +#endif > + /* Set address of hardware control function */ > + chip->cmd_ctrl = nand_davinci_hwcontrol; > + > + chip->read_buf = nand_davinci_read_buf; > + chip->write_buf = nand_davinci_write_buf; > + > + chip->dev_ready = nand_davinci_dev_ready; > + > + davinci_aemif_setup_timing(pdata->timing, (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE, 3-2); > + > + ///* put CSxNAND into NAND mode */ C++ comment > + val = readl(&emif_regs->NANDFCR); > + val |= BIT(3-2); > + writel(val, &emif_regs->NANDFCR); > + > + /* Scan to find existence of the device */ > + ret = nand_scan(mtd, 1); > + if (ret != 0) { > + ret = -ENXIO; > + goto on_error; > + } > + > + return add_mtd_device(mtd, "nand"); > + > +on_error: > + free(host); > + return ret; > +} > + > +static struct driver_d davinci_nand_driver = { > + .name = "davinci_nand", > + .probe = davinci_nand_probe, > +}; > + > +static int __init davinci_nand_init(void) > +{ > + return register_driver(&davinci_nand_driver); > +} > + > +device_initcall(davinci_nand_init); > diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c > index c4eca0d..65ba1e6 100644 > --- a/drivers/mtd/nand/nand_base.c > +++ b/drivers/mtd/nand/nand_base.c > @@ -1344,6 +1344,10 @@ int nand_scan_tail(struct mtd_info *mtd) > chip->ecc.bytes = 0; > break; > #endif > + case NAND_ECC_HW_OOB_FIRST: > + nand_check_hwecc(mtd, chip); > + nand_init_ecc_hw_syndrome(chip); > + break; This deserves a separate patch with a description what it does. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 09/12] board hmi10: enable support for NAND 2012-06-26 9:51 Add basic support for the OMAP-L138/DA850 Jan Luebbe ` (7 preceding siblings ...) 2012-06-26 9:51 ` [PATCH 08/12] drivers/mtd/nand: add driver for the davinci NAND flash controller Jan Luebbe @ 2012-06-26 9:51 ` Jan Luebbe 2012-06-26 9:51 ` [PATCH 10/12] drivers/spi: add driver for the davinci SPI master Jan Luebbe ` (3 subsequent siblings) 12 siblings, 0 replies; 22+ messages in thread From: Jan Luebbe @ 2012-06-26 9:51 UTC (permalink / raw) To: barebox Signed-off-by: Jan Luebbe <jlu@pengutronix.de> --- arch/arm/boards/hmi10/board.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boards/hmi10/board.c b/arch/arm/boards/hmi10/board.c index be4d920..bc3283d 100644 --- a/arch/arm/boards/hmi10/board.c +++ b/arch/arm/boards/hmi10/board.c @@ -31,7 +31,9 @@ #include <linux/err.h> #include <linux/mtd/nand.h> +#include <mach/aemif.h> #include <mach/hardware.h> +#include <mach/nand.h> #include <mach/da8xx.h> #ifdef CONFIG_DRIVER_SERIAL_NS16550 @@ -82,8 +84,29 @@ static int hmi10_mem_init(void) } mem_initcall(hmi10_mem_init); +static struct davinci_aemif_timing hmi10_nandflash_timing = { + .wsetup = 24, + .wstrobe = 21, + .whold = 14, + .rsetup = 19, + .rstrobe = 50, + .rhold = 0, + .ta = 20, +}; + +static struct davinci_nand_pdata hmi10_nandflash_data = { + .ecc_mode = NAND_ECC_HW, + .ecc_bits = 4, + .options = NAND_USE_FLASH_BBT, + .timing = &hmi10_nandflash_timing, +}; + static int hmi10_devices_init(void) { + lpsc_on(DAVINCI_LPSC_AEMIF); + add_generic_device("davinci_nand", -1, NULL, DAVINCI_ASYNC_EMIF_CNTRL_BASE, 0, + IORESOURCE_MEM, &hmi10_nandflash_data); + armlinux_set_bootparams((void *)0xc0000100); armlinux_set_architecture(MACH_TYPE_DAVINCI_HE_HMI10); -- 1.7.10 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 10/12] drivers/spi: add driver for the davinci SPI master 2012-06-26 9:51 Add basic support for the OMAP-L138/DA850 Jan Luebbe ` (8 preceding siblings ...) 2012-06-26 9:51 ` [PATCH 09/12] board hmi10: enable support for NAND Jan Luebbe @ 2012-06-26 9:51 ` Jan Luebbe 2012-06-26 9:51 ` [PATCH 11/12] board hmi10: enable support for SPI Jan Luebbe ` (2 subsequent siblings) 12 siblings, 0 replies; 22+ messages in thread From: Jan Luebbe @ 2012-06-26 9:51 UTC (permalink / raw) To: barebox Signed-off-by: Jan Luebbe <jlu@pengutronix.de> --- arch/arm/mach-davinci/include/mach/spi.h | 11 + drivers/spi/Kconfig | 5 + drivers/spi/Makefile | 1 + drivers/spi/davinci_spi.c | 355 ++++++++++++++++++++++++++++++ drivers/spi/davinci_spi.h | 123 +++++++++++ 5 files changed, 495 insertions(+) create mode 100644 arch/arm/mach-davinci/include/mach/spi.h create mode 100644 drivers/spi/davinci_spi.c create mode 100644 drivers/spi/davinci_spi.h diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h new file mode 100644 index 0000000..d92465b --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/spi.h @@ -0,0 +1,11 @@ + +#ifndef __MACH_SPI_H_ +#define __MACH_SPI_H_ + +struct davinci_spi_master_pdata { + int num_chipselect; + int bus_num; + int clk_id; +}; + +#endif /* __MACH_SPI_H_*/ diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 609bafd..17930ce 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -4,6 +4,11 @@ config SPI bool "Enable SPI driver support" default y +config DRIVER_SPI_DAVINCI + bool "TI Davinci SPI Master driver" + depends on ARCH_DAVINCI + depends on SPI + config DRIVER_SPI_IMX bool "i.MX SPI Master driver" depends on ARCH_IMX diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 101652f..e91cb08 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_SPI) += spi.o +obj-$(CONFIG_DRIVER_SPI_DAVINCI) += davinci_spi.o obj-$(CONFIG_DRIVER_SPI_IMX) += imx_spi.o obj-$(CONFIG_DRIVER_SPI_ALTERA) += altera_spi.o obj-$(CONFIG_DRIVER_SPI_ATMEL) += atmel_spi.o diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c new file mode 100644 index 0000000..930c999 --- /dev/null +++ b/drivers/spi/davinci_spi.c @@ -0,0 +1,355 @@ +/* + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * Driver for SPI controller on DaVinci. Based on atmel_spi.c + * by Atmel Corporation + * + * Copyright (C) 2007 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +//#define DEBUG + +#include <common.h> +#include <init.h> +#include <driver.h> +#include <errno.h> +#include <malloc.h> +#include <io.h> +#include <spi/spi.h> +#include <mach/spi.h> +#include <mach/hardware.h> +#include "davinci_spi.h" + +#if 0 +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct davinci_spi_slave *ds; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ds = malloc(sizeof(*ds)); + if (!ds) + return NULL; + + ds->slave.bus = bus; + ds->slave.cs = cs; + if (bus == 0) + ds->regs = (struct davinci_spi_regs *) DAVINCI_SPI0_BASE; //CONFIG_SYS_SPI_BASE; + else + ds->regs = (struct davinci_spi_regs *) DAVINCI_SPI1_BASE; //CONFIG_SYS_SPI_BASE; + ds->freq = max_hz; + + return &ds->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct davinci_spi_slave *ds = to_davinci_spi(slave); + + free(ds); +} +#endif + +static int davinci_spi_check_error(struct spi_device *spi) +{ + struct spi_master *master = spi->master; + struct davinci_spi_master *davinci_master = container_of(master, struct davinci_spi_master, master); + + unsigned int int_status = readl(&davinci_master->regs->flg); + if (int_status & SPIFLG_TIMEOUT_MASK) { + dev_err(master->dev, "SPI Time-out Error\n"); + return -ETIMEDOUT; + } + if (int_status & SPIFLG_DESYNC_MASK) { + dev_err(master->dev, "SPI Desynchronization Error\n"); + return -EIO; + } + if (int_status & SPIFLG_BITERR_MASK) { + dev_err(master->dev, "SPI Bit error\n"); + return -EIO; + } + + /* version 2 */ + if (int_status & SPIFLG_DLEN_ERR_MASK) { + dev_err(master->dev, "SPI Data Length Error\n"); + return -EIO; + } + if (int_status & SPIFLG_PARERR_MASK) { + dev_err(master->dev, "SPI Parity Error\n"); + return -EIO; + } + if (int_status & SPIFLG_OVRRUN_MASK) { + dev_err(master->dev, "SPI Data Overrun error\n"); + return -EIO; + } + + return 0; +} + +static int davinci_spi_xfer(struct spi_device *spi, struct spi_transfer *t) +{ + struct spi_master *master = spi->master; + struct davinci_spi_master *davinci_master = container_of(master, struct davinci_spi_master, master); + struct davinci_spi_regs *regs = davinci_master->regs; + unsigned int len = t->len, data1_reg_val = readl(®s->dat1); + int ret = 0, i; + const u8 *txp = t->tx_buf; /* can be NULL for read operation */ + u8 *rxp = t->rx_buf; /* can be NULL for write operation */ + + dev_dbg(master->dev, "xfer\n"); + /* do an empty read to clear the current contents */ + readl(®s->buf); + + /* keep writing and reading 1 byte until done */ + for (i = 0; i < len; i++) { + davinci_spi_check_error(spi); + + /* wait while TXFULL is asserted */ + while (readl(®s->buf) & SPIBUF_TXFULL_MASK); + + /* write the data */ + data1_reg_val &= ~0xFFFF; + if (txp) { + data1_reg_val |= *txp; + txp++; + } + + /* + * Write to DAT1 is required to keep the serial transfer going. + * We just terminate when we reach the end. + */ + if ((i == (len - 1)) && t->cs_change) { + /* clear CS hold */ + data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT); + //dev_dbg(master->dev, "write !cs-hold 0x%08x\n", data1_reg_val); + } else { + /* enable CS hold */ + data1_reg_val |= (1 << SPIDAT1_CSHOLD_SHIFT); + //dev_dbg(master->dev, "write cs-hold 0x%08x\n", data1_reg_val); + } + writel(data1_reg_val, ®s->dat1); + + /* read the data - wait for data availability */ + while (readl(®s->buf) & SPIBUF_RXEMPTY_MASK); + + if (rxp) { + *rxp = readl(®s->buf) & 0xFF; + rxp++; + } else { + /* simply drop the read character */ + readl(®s->buf); + } + } + + return ret; +} + +static int davinci_spi_claim_bus(struct spi_device *spi) +{ + struct spi_master *master = spi->master; + struct device_d spi_dev = spi->dev; + struct davinci_spi_master *davinci_master = container_of(master, struct davinci_spi_master, master); + + unsigned int scalar, phase, polarity, data1_reg_val = 0; + + dev_dbg(master->dev, "claiming bus for device %s\n", spi_dev.name); + + /* Set master mode, powered up and not activated */ + writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &davinci_master->regs->gcr1); + + /* CS, CLK, SIMO and SOMI are functional pins */ + writel((davinci_master->cs_pins | SPIPC0_CLKFUN_MASK | + SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &davinci_master->regs->pc0); + + /* setup format */ + scalar = ((da8xx_clk_get(davinci_master->clk_id) / davinci_master->speed_hz) - 1) & 0xFF; + + phase = (spi->mode & SPI_CPHA) ? 0 : 1; + polarity = (spi->mode & SPI_CPOL) ? 1 : 0; + + /* + * Use following format: + * character length = 8, + * clock signal delayed by half clk cycle, + * clock low in idle state - Mode 0, + * MSB shifted out first + */ + writel(8 | + (scalar << SPIFMT_PRESCALE_SHIFT) | + (phase << SPIFMT_PHASE_SHIFT) | + (polarity << SPIFMT_POLARITY_SHIFT), + &davinci_master->regs->fmt0); + + /* hold cs active at end of transfer until explicitly de-asserted */ + data1_reg_val = (1 << SPIDAT1_CSHOLD_SHIFT) | SPIDAT1_CSNR_MASK; + data1_reg_val &= ~(1 << (SPIDAT1_CSNR_SHIFT + spi->chip_select)); + dev_dbg(master->dev, "write claim 0x%08x\n", data1_reg_val); + /* only write upper 16 bit to avoid initiating a transfer */ + writew((data1_reg_val & 0xFFFF0000) >> 16, (void*)&davinci_master->regs->dat1 + 2); + + /* + * Including a minor delay. No science here. Should be good even with + * no delay + */ + writel((50 << SPI_C2TDELAY_SHIFT) | + (50 << SPI_T2CDELAY_SHIFT), &davinci_master->regs->delay); + + /* default chip select register */ + writel(SPIDEF_CSDEF0_MASK, &davinci_master->regs->def); + + /* no interrupts */ + writel(0, &davinci_master->regs->int0); + writel(0, &davinci_master->regs->lvl); + + /* enable SPI */ + writel((readl(&davinci_master->regs->gcr1) | SPIGCR1_SPIENA_MASK), &davinci_master->regs->gcr1); + + return 0; +} + +static void davinci_spi_release_bus(struct davinci_spi_master *davinci_master) +{ + dev_dbg(davinci_master->master.dev, "releasing bus\n"); + + /* Set master mode and powered down */ + writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &davinci_master->regs->gcr1); + /* Disable the SPI hardware */ + //writel(SPIGCR0_SPIRST_MASK, &davinci_master->regs->gcr0); +} + +static int davinci_spi_setup(struct spi_device *spi) +{ + struct spi_master *master = spi->master; + struct device_d spi_dev = spi->dev; + struct davinci_spi_master *davinci_master = container_of(master, struct davinci_spi_master, master); + + if (spi->bits_per_word != davinci_master->databits) { + dev_err(master->dev, "master doesn't support %d bits per word requested by %s\n", + spi->bits_per_word, spi_dev.name); + return -1; + } + + if ((spi->mode & (SPI_CPHA | SPI_CPOL)) != davinci_master->mode) { + dev_err(master->dev, "master is not configured for SPI_MODE_%d requested by %s\n", + spi->mode & (SPI_CPHA | SPI_CPOL), spi_dev.name); + return -1; + } + + if (spi->max_speed_hz < davinci_master->speed_hz) { + dev_err(master->dev, "frequency is too high for %s\n", spi_dev.name); + return -1; + } + + davinci_master->cs_pins |= 1 << spi->chip_select; + + davinci_spi_release_bus(davinci_master); + + dev_info(master->dev, "mode 0x%08x, bits_per_word: %d, speed: %d\n", + spi->mode, spi->bits_per_word, davinci_master->speed_hz); + + return 0; +} + +static int davinci_spi_transfer(struct spi_device *spi, struct spi_message *mesg) +{ + struct spi_master *master = spi->master; + struct davinci_spi_master *davinci_master = container_of(master, struct davinci_spi_master, master); + struct spi_transfer *t = NULL; + + int ret = 0; + + ret = davinci_spi_claim_bus(spi); + if (ret) + return ret; + + if (list_empty(&mesg->transfers)) + return 0; + + list_last_entry(&mesg->transfers, struct spi_transfer, transfer_list)->cs_change = 1; + + list_for_each_entry(t, &mesg->transfers, transfer_list) { + dev_dbg(master->dev, + " xfer %p: len %u tx %p rx %p cs_change %i\n", + t, t->len, t->tx_buf, t->rx_buf, t->cs_change); + } + + dev_dbg(master->dev, "transfer\n"); + list_for_each_entry(t, &mesg->transfers, transfer_list) { + davinci_spi_xfer(spi, t); + mesg->actual_length += t->len; + } + + davinci_spi_release_bus(davinci_master); + return ret; +} + +static int davinci_spi_probe(struct device_d *dev) +{ + struct spi_master *master; + struct davinci_spi_master *davinci_master; + struct davinci_spi_master_pdata *pdata = dev->platform_data; + + davinci_master = xzalloc(sizeof(*davinci_master)); + + master = &davinci_master->master; + master->dev = dev; + + master->setup = davinci_spi_setup; + master->transfer = davinci_spi_transfer; + master->num_chipselect = pdata->num_chipselect; + master->bus_num = pdata->bus_num; + + davinci_master->regs = dev_request_mem_region(dev, 0); + //davinci_master->mode = pdata->spi_mode; + //davinci_master->databits = pdata->databits; + //davinci_master->speed_hz = pdata->speed_hz; + davinci_master->mode = SPI_MODE_0; + davinci_master->databits = 8; + davinci_master->speed_hz = 20000000; + davinci_master->clk_id = pdata->clk_id; + + /* Enable the SPI hardware */ + writel(SPIGCR0_SPIRST_MASK, &davinci_master->regs->gcr0); + udelay(1000); + writel(SPIGCR0_SPIENA_MASK, &davinci_master->regs->gcr0); + + spi_register_master(master); + + return 0; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 1 && cs == 0; +} + +static struct driver_d davinci_spi_driver = { + .name = "davinci_spi", + .probe = davinci_spi_probe, +}; + +static int davinci_spi_init(void) +{ + return register_driver(&davinci_spi_driver); +} + +device_initcall(davinci_spi_init); diff --git a/drivers/spi/davinci_spi.h b/drivers/spi/davinci_spi.h new file mode 100644 index 0000000..f423141 --- /dev/null +++ b/drivers/spi/davinci_spi.h @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * Register definitions for the DaVinci SPI Controller + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _DAVINCI_SPI_H_ +#define _DAVINCI_SPI_H_ + +#include <mach/hardware.h> + +struct davinci_spi_regs { + dv_reg gcr0; /* 0x00 */ + dv_reg gcr1; /* 0x04 */ + dv_reg int0; /* 0x08 */ + dv_reg lvl; /* 0x0c */ + dv_reg flg; /* 0x10 */ + dv_reg pc0; /* 0x14 */ + dv_reg pc1; /* 0x18 */ + dv_reg pc2; /* 0x1c */ + dv_reg pc3; /* 0x20 */ + dv_reg pc4; /* 0x24 */ + dv_reg pc5; /* 0x28 */ + dv_reg rsvd[3]; + dv_reg dat0; /* 0x38 */ + dv_reg dat1; /* 0x3c */ + dv_reg buf; /* 0x40 */ + dv_reg emu; /* 0x44 */ + dv_reg delay; /* 0x48 */ + dv_reg def; /* 0x4c */ + dv_reg fmt0; /* 0x50 */ + dv_reg fmt1; /* 0x54 */ + dv_reg fmt2; /* 0x58 */ + dv_reg fmt3; /* 0x5c */ + dv_reg intvec0; /* 0x60 */ + dv_reg intvec1; /* 0x64 */ +}; + +/* SPIGCR0 */ +#define SPIGCR0_SPIENA_MASK 0x1 +#define SPIGCR0_SPIRST_MASK 0x0 + +/* SPIGCR0 */ +#define SPIGCR1_CLKMOD_MASK BIT(1) +#define SPIGCR1_MASTER_MASK BIT(0) +#define SPIGCR1_POWERDOWN_MASK BIT(8) +#define SPIGCR1_SPIENA_MASK BIT(24) + +/* SPIFLG */ +#define SPIFLG_DLEN_ERR_MASK BIT(0) +#define SPIFLG_TIMEOUT_MASK BIT(1) +#define SPIFLG_PARERR_MASK BIT(2) +#define SPIFLG_DESYNC_MASK BIT(3) +#define SPIFLG_BITERR_MASK BIT(4) +#define SPIFLG_OVRRUN_MASK BIT(6) + +/* SPIPC0 */ +#define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */ +#define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */ +#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ +#define SPIPC0_EN0FUN_MASK BIT(0) + +/* SPIFMT0 */ +#define SPIFMT_SHIFTDIR_SHIFT 20 +#define SPIFMT_POLARITY_SHIFT 17 +#define SPIFMT_PHASE_SHIFT 16 +#define SPIFMT_PRESCALE_SHIFT 8 + +/* SPIDAT1 */ +#define SPIDAT1_CSHOLD_SHIFT 28 +#define SPIDAT1_CSNR_SHIFT 16 +#define SPIDAT1_CSNR_MASK (0xff << SPIDAT1_CSNR_SHIFT) + +/* SPIDELAY */ +#define SPI_C2TDELAY_SHIFT 24 +#define SPI_T2CDELAY_SHIFT 16 + +/* SPIBUF */ +#define SPIBUF_RXEMPTY_MASK BIT(31) +#define SPIBUF_TXFULL_MASK BIT(29) + +/* SPIDEF */ +#define SPIDEF_CSDEF0_MASK 0xff + +/* +struct davinci_spi_slave { + struct spi_slave slave; + struct davinci_spi_regs *regs; + unsigned int freq; +}; + +static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave) +{ + return container_of(slave, struct davinci_spi_slave, slave); +} +*/ + +struct davinci_spi_master { + struct spi_master master; + struct davinci_spi_regs __iomem *regs; + int mode; + int databits; + int speed_hz; + int clk_id; + unsigned int cs_pins; +}; + +#endif /* _DAVINCI_SPI_H_ */ -- 1.7.10 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 11/12] board hmi10: enable support for SPI 2012-06-26 9:51 Add basic support for the OMAP-L138/DA850 Jan Luebbe ` (9 preceding siblings ...) 2012-06-26 9:51 ` [PATCH 10/12] drivers/spi: add driver for the davinci SPI master Jan Luebbe @ 2012-06-26 9:51 ` Jan Luebbe 2012-06-26 9:51 ` [PATCH 12/12] board hmi10: add default config Jan Luebbe 2012-06-26 11:59 ` Add basic support for the OMAP-L138/DA850 Yegor Yefremov 12 siblings, 0 replies; 22+ messages in thread From: Jan Luebbe @ 2012-06-26 9:51 UTC (permalink / raw) To: barebox Signed-off-by: Jan Luebbe <jlu@pengutronix.de> --- arch/arm/boards/hmi10/board.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boards/hmi10/board.c b/arch/arm/boards/hmi10/board.c index bc3283d..1ec2ea2 100644 --- a/arch/arm/boards/hmi10/board.c +++ b/arch/arm/boards/hmi10/board.c @@ -34,6 +34,7 @@ #include <mach/aemif.h> #include <mach/hardware.h> #include <mach/nand.h> +#include <mach/spi.h> #include <mach/da8xx.h> #ifdef CONFIG_DRIVER_SERIAL_NS16550 @@ -101,12 +102,50 @@ static struct davinci_nand_pdata hmi10_nandflash_data = { .timing = &hmi10_nandflash_timing, }; +static struct spi_board_info hmi10_spi1_board_info[] = { + /* 20 MHz according to datasheet for 130nm and normal READ (!= FAST_READ) */ + { + .name = "m25p", + .max_speed_hz = 20000000, + .bus_num = 1, + .chip_select = 0, + .mode = SPI_MODE_0, + }, + { + .name = "m25p", + .max_speed_hz = 20000000, + .bus_num = 1, + .chip_select = 1, + .mode = SPI_MODE_0, + }, +}; + +static struct davinci_spi_master_pdata hmi10_spi1_pdata = { + .num_chipselect = 2, + .bus_num = 1, +}; + static int hmi10_devices_init(void) { lpsc_on(DAVINCI_LPSC_AEMIF); add_generic_device("davinci_nand", -1, NULL, DAVINCI_ASYNC_EMIF_CNTRL_BASE, 0, IORESOURCE_MEM, &hmi10_nandflash_data); + lpsc_on(DAVINCI_LPSC_SPI1); + spi_register_board_info(hmi10_spi1_board_info, ARRAY_SIZE(hmi10_spi1_board_info)); + hmi10_spi1_pdata.clk_id = DAVINCI_SPI1_CLKID; + add_generic_device("davinci_spi", 1, NULL, DAVINCI_SPI1_BASE, 0x68, + IORESOURCE_MEM, &hmi10_spi1_pdata); + + /* one sector for the UBL (TI User Boot Loader) */ + devfs_add_partition("m25p0", 0x00000, 0x40000, + DEVFS_PARTITION_FIXED|DEVFS_PARTITION_READONLY, "ubl"); /* 256k */ + /* one sector for barebox itself */ + devfs_add_partition("m25p0", 0x40000, 0x40000, + DEVFS_PARTITION_FIXED|DEVFS_PARTITION_READONLY, "self0"); /* 256k */ + /* two sectors for read-write environment */ + devfs_add_partition("m25p0", 0x80000, 0x80000, DEVFS_PARTITION_FIXED, "env0"); /* 512k */ + armlinux_set_bootparams((void *)0xc0000100); armlinux_set_architecture(MACH_TYPE_DAVINCI_HE_HMI10); -- 1.7.10 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 12/12] board hmi10: add default config 2012-06-26 9:51 Add basic support for the OMAP-L138/DA850 Jan Luebbe ` (10 preceding siblings ...) 2012-06-26 9:51 ` [PATCH 11/12] board hmi10: enable support for SPI Jan Luebbe @ 2012-06-26 9:51 ` Jan Luebbe 2012-06-26 11:59 ` Add basic support for the OMAP-L138/DA850 Yegor Yefremov 12 siblings, 0 replies; 22+ messages in thread From: Jan Luebbe @ 2012-06-26 9:51 UTC (permalink / raw) To: barebox Signed-off-by: Jan Luebbe <jlu@pengutronix.de> --- arch/arm/configs/hmi10_defconfig | 59 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 arch/arm/configs/hmi10_defconfig diff --git a/arch/arm/configs/hmi10_defconfig b/arch/arm/configs/hmi10_defconfig new file mode 100644 index 0000000..ce0ef26 --- /dev/null +++ b/arch/arm/configs/hmi10_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARCH_DAVINCI=y +CONFIG_MMU=y +CONFIG_MALLOC_SIZE=0x800000 +CONFIG_KALLSYMS=y +CONFIG_LONGHELP=y +CONFIG_GLOB=y +CONFIG_GLOB_SORT=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/hmi10/env" +CONFIG_POLLER=y +CONFIG_DEBUG_INFO=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GLOBAL=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_UIMAGE=y +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_BMP=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_PING=y +CONFIG_NET_TFTP=y +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_SPI_DAVINCI=y +CONFIG_MTD_M25P80=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_DAVINCI=y +CONFIG_USB=y +CONFIG_USB_OHCI=y +CONFIG_USB_STORAGE=y +CONFIG_VIDEO=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_LFN=y +CONFIG_LZO_DECOMPRESS=y -- 1.7.10 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: Add basic support for the OMAP-L138/DA850 2012-06-26 9:51 Add basic support for the OMAP-L138/DA850 Jan Luebbe ` (11 preceding siblings ...) 2012-06-26 9:51 ` [PATCH 12/12] board hmi10: add default config Jan Luebbe @ 2012-06-26 11:59 ` Yegor Yefremov 2012-06-26 12:06 ` Jan Lübbe 12 siblings, 1 reply; 22+ messages in thread From: Yegor Yefremov @ 2012-06-26 11:59 UTC (permalink / raw) To: Jan Luebbe; +Cc: barebox Hi Jan, > this series introduces a new ARM machine 'davinci' and adds support > for UART, pin mux, power/clock, USB 1.1, NAND and SPI. Included is > support for the HMI10 system which was used to develop and test this > series. > > A second series adding ethernet (EMAC) and display (LCDC) support > will be submitted when this is accepted. do you also have am335x system? AFAIK they both share same IP blocks. Regards, Yegor _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: Add basic support for the OMAP-L138/DA850 2012-06-26 11:59 ` Add basic support for the OMAP-L138/DA850 Yegor Yefremov @ 2012-06-26 12:06 ` Jan Lübbe 2012-06-26 20:52 ` Yegor Yefremov 0 siblings, 1 reply; 22+ messages in thread From: Jan Lübbe @ 2012-06-26 12:06 UTC (permalink / raw) To: Yegor Yefremov; +Cc: barebox On Tue, 2012-06-26 at 13:59 +0200, Yegor Yefremov wrote: > > this series introduces a new ARM machine 'davinci' and adds support > > for UART, pin mux, power/clock, USB 1.1, NAND and SPI. Included is > > support for the HMI10 system which was used to develop and test this > > series. > > > > A second series adding ethernet (EMAC) and display (LCDC) support > > will be submitted when this is accepted. > > do you also have am335x system? AFAIK they both share same IP blocks. I have a BeagleBone, which uses an AM3359. So far it seems that it is closer to the OMAP3530 (beagleboard) than to the L138. The AM3505 shares the EMAC core with the L138 and the AM1808 should be nearly identical to the L138. I've got a simple hack which allows loading barebox on a BeagleBone from U-Boot's SPL (MUX and clocking is missing). You can use it to load a kernel from SD and boot it. Best regards, Jan -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: Add basic support for the OMAP-L138/DA850 2012-06-26 12:06 ` Jan Lübbe @ 2012-06-26 20:52 ` Yegor Yefremov 2012-06-29 11:42 ` [PATCH] Initial BeagleBone support for second stage Jan Luebbe 0 siblings, 1 reply; 22+ messages in thread From: Yegor Yefremov @ 2012-06-26 20:52 UTC (permalink / raw) To: Jan Lübbe; +Cc: barebox On Tue, Jun 26, 2012 at 2:06 PM, Jan Lübbe <jlu@pengutronix.de> wrote: > On Tue, 2012-06-26 at 13:59 +0200, Yegor Yefremov wrote: >> > this series introduces a new ARM machine 'davinci' and adds support >> > for UART, pin mux, power/clock, USB 1.1, NAND and SPI. Included is >> > support for the HMI10 system which was used to develop and test this >> > series. >> > >> > A second series adding ethernet (EMAC) and display (LCDC) support >> > will be submitted when this is accepted. >> >> do you also have am335x system? AFAIK they both share same IP blocks. > > I have a BeagleBone, which uses an AM3359. So far it seems that it is > closer to the OMAP3530 (beagleboard) than to the L138. The AM3505 shares > the EMAC core with the L138 and the AM1808 should be nearly identical to > the L138. > > I've got a simple hack which allows loading barebox on a BeagleBone from > U-Boot's SPL (MUX and clocking is missing). You can use it to load a > kernel from SD and boot it. Could you share the hack? I would really like to see at least one of our systems using barebox instead of u-boot. Yegor _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH] Initial BeagleBone support for second stage 2012-06-26 20:52 ` Yegor Yefremov @ 2012-06-29 11:42 ` Jan Luebbe 0 siblings, 0 replies; 22+ messages in thread From: Jan Luebbe @ 2012-06-29 11:42 UTC (permalink / raw) To: barebox; +Cc: Jan Luebbe This is obviously rather rough, but it was enough to load a kernel when started from TI's u-boot SPL. Build barebox.img, put it on the SD card instead of u-boot.img. Note that the machine id may need changing depending on the kernel. Signed-off-by: Jan Luebbe <jluebbe@debian.org> --- Makefile | 5 + arch/arm/Makefile | 1 + arch/arm/boards/beaglebone/Makefile | 1 + arch/arm/boards/beaglebone/board.c | 317 +++++++++++++++++++++++++++++++++ arch/arm/boards/beaglebone/config.h | 21 +++ arch/arm/boards/beaglebone/env/config | 63 +++++++ arch/arm/mach-omap/Kconfig | 11 +- arch/arm/mach-omap/s32k_clksource.c | 5 +- 8 files changed, 422 insertions(+), 2 deletions(-) create mode 100644 arch/arm/boards/beaglebone/Makefile create mode 100644 arch/arm/boards/beaglebone/board.c create mode 100644 arch/arm/boards/beaglebone/config.h create mode 100644 arch/arm/boards/beaglebone/env/config diff --git a/Makefile b/Makefile index 9294049..ff6a645 100644 --- a/Makefile +++ b/Makefile @@ -672,6 +672,11 @@ barebox.bin: barebox FORCE $(call if_changed,objcopy) $(call cmd,check_file_size,$(CONFIG_BAREBOX_MAX_IMAGE_SIZE)) +barebox.img: barebox.bin + $(srctree)/scripts/mkimage -A $(ARCH) -T firmware -C none \ + -O barebox -a $(CONFIG_TEXT_BASE) -e $(CONFIG_TEXT_BASE) \ + -n "barebox $(KERNELRELEASE)" -d $< $@ + ifdef CONFIG_X86 barebox.S: barebox ifdef CONFIG_X86_HDBOOT diff --git a/arch/arm/Makefile b/arch/arm/Makefile index bd684dc..0644fe7 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -99,6 +99,7 @@ board-$(CONFIG_MACH_NOMADIK_8815NHK) := nhk8815 board-$(CONFIG_MACH_NXDB500) := netx board-$(CONFIG_MACH_OMAP343xSDP) := omap343xdsp board-$(CONFIG_MACH_BEAGLE) := beagle +board-$(CONFIG_MACH_BEAGLEBONE) := beaglebone board-$(CONFIG_MACH_OMAP3EVM) := omap3evm board-$(CONFIG_MACH_PANDA) := panda board-$(CONFIG_MACH_PCM049) := pcm049 diff --git a/arch/arm/boards/beaglebone/Makefile b/arch/arm/boards/beaglebone/Makefile new file mode 100644 index 0000000..dcfc293 --- /dev/null +++ b/arch/arm/boards/beaglebone/Makefile @@ -0,0 +1 @@ +obj-y += board.o diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c new file mode 100644 index 0000000..dadec5a --- /dev/null +++ b/arch/arm/boards/beaglebone/board.c @@ -0,0 +1,317 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Raghavendra KH <r-khandenahally@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/** + * @file + * @brief Beagle Specific Board Initialization routines + */ + +/** + * @page ti_beagle Texas Instruments Beagle Board + * + * FileName: arch/arm/boards/omap/board-beagle.c + * + * Beagle Board from Texas Instruments as described here: + * http://www.beagleboard.org + * + * This board is based on OMAP3530. + * More on OMAP3530 (including documentation can be found here): + * http://focus.ti.com/docs/prod/folders/print/omap3530.html + * + * This file provides initialization in two stages: + * @li boot time initialization - do basics required to get SDRAM working. + * This is run from SRAM - so no case constructs and global vars can be used. + * @li run time initialization - this is for the rest of the initializations + * such as flash, uart etc. + * + * Boot time initialization includes: + * @li SDRAM initialization. + * @li Pin Muxing relevant for Beagle. + * + * Run time initialization includes + * @li serial @ref serial_ns16550.c driver device definition + * + * Originally from arch/arm/boards/omap/board-sdp343x.c + */ + +#include <common.h> +#include <console.h> +#include <init.h> +#include <driver.h> +#include <sizes.h> +#include <io.h> +#include <ns16550.h> +#include <asm/armlinux.h> +#include <generated/mach-types.h> +#include <mach/silicon.h> +#include <mach/sdrc.h> +#include <mach/sys_info.h> +#include <mach/syslib.h> +#include <mach/control.h> +#include <mach/omap3-mux.h> +#include <mach/gpmc.h> +#include <mach/ehci.h> +#include <i2c/i2c.h> +#include <linux/err.h> +#include <usb/ehci.h> +#include <mach/xload.h> + +/******************** Board Boot Time *******************/ + +/** + * @brief Do the SDRC initialization for 128Meg Micron DDR for CS0 + * + * @return void + */ +static void sdrc_init(void) +{ + /* SDRAM software reset */ + /* No idle ack and RESET enable */ + writel(0x1A, SDRC_REG(SYSCONFIG)); + sdelay(100); + /* No idle ack and RESET disable */ + writel(0x18, SDRC_REG(SYSCONFIG)); + + /* SDRC Sharing register */ + /* 32-bit SDRAM on data lane [31:0] - CS0 */ + /* pin tri-stated = 1 */ + writel(0x00000100, SDRC_REG(SHARING)); + + /* ----- SDRC Registers Configuration --------- */ + /* SDRC_MCFG0 register */ + writel(0x02584099, SDRC_REG(MCFG_0)); + + /* SDRC_RFR_CTRL0 register */ + writel(0x54601, SDRC_REG(RFR_CTRL_0)); + + /* SDRC_ACTIM_CTRLA0 register */ + writel(0xA29DB4C6, SDRC_REG(ACTIM_CTRLA_0)); + + /* SDRC_ACTIM_CTRLB0 register */ + writel(0x12214, SDRC_REG(ACTIM_CTRLB_0)); + + /* Disble Power Down of CKE due to 1 CKE on combo part */ + writel(0x00000081, SDRC_REG(POWER)); + + /* SDRC_MANUAL command register */ + /* NOP command */ + writel(0x00000000, SDRC_REG(MANUAL_0)); + /* Precharge command */ + writel(0x00000001, SDRC_REG(MANUAL_0)); + /* Auto-refresh command */ + writel(0x00000002, SDRC_REG(MANUAL_0)); + /* Auto-refresh command */ + writel(0x00000002, SDRC_REG(MANUAL_0)); + + /* SDRC MR0 register Burst length=4 */ + writel(0x00000032, SDRC_REG(MR_0)); + + /* SDRC DLLA control register */ + writel(0x0000000A, SDRC_REG(DLLA_CTRL)); + + return; +} + +/** + * @brief Do the pin muxing required for Board operation. + * We enable ONLY the pins we require to set. OMAP provides pins which do not + * have alternate modes. Such pins done need to be set. + * + * See @ref MUX_VAL for description of the muxing mode. + * + * @return void + */ +static void mux_config(void) +{ + /* SDRC_D0 - SDRC_D31 default mux mode is mode0 */ + + /* GPMC */ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)); + + /* D0-D7 default mux mode is mode0 */ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)); + /* GPMC_NADV_ALE default mux mode is mode0 */ + /* GPMC_NOE default mux mode is mode0 */ + /* GPMC_NWE default mux mode is mode0 */ + /* GPMC_NBE0_CLE default mux mode is mode0 */ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); + /* GPMC_WAIT0 default mux mode is mode0 */ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); + + /* SERIAL INTERFACE */ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)); + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); + /* I2C1_SCL default mux mode is mode0 */ + /* I2C1_SDA default mux mode is mode0 */ + /* USB EHCI (port 2) */ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)); + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)); + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)); + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)); + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)); + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)); + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)); + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)); + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)); + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)); + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)); + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/; +} + +/** + * @brief The basic entry point for board initialization. + * + * This is called as part of machine init (after arch init). + * This is again called with stack in SRAM, so not too many + * constructs possible here. + * + * @return void + */ +static int beagle_board_init(void) +{ + int in_sdram = running_in_sdram(); + + //omap3_core_init(); + + //mux_config(); + /* Dont reconfigure SDRAM while running in SDRAM! */ + //if (!in_sdram) + // sdrc_init(); + + return 0; +} +pure_initcall(beagle_board_init); + +/******************** Board Run Time *******************/ + +#ifdef CONFIG_DRIVER_SERIAL_NS16550 + +static struct NS16550_plat serial_plat = { + .clock = 48000000, /* 48MHz (APLL96/2) */ + .shift = 2, +}; + +/** + * @brief UART serial port initialization - remember to enable COM clocks in + * arch + * + * @return result of device registration + */ +static int beagle_console_init(void) +{ + /* Register the serial port */ + add_ns16550_device(-1, 0x44e09000, 1024, IORESOURCE_MEM_8BIT, + &serial_plat); + + return 0; +} +console_initcall(beagle_console_init); +#endif /* CONFIG_DRIVER_SERIAL_NS16550 */ + +#ifdef CONFIG_USB_EHCI_OMAP +static struct omap_hcd omap_ehci_pdata = { + .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, + .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, + .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .phy_reset = 1, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = 147, + .reset_gpio_port[2] = -EINVAL +}; + +static struct ehci_platform_data ehci_pdata = { + .flags = 0, +}; +#endif /* CONFIG_USB_EHCI_OMAP */ + +static struct i2c_board_info i2c_devices[] = { + { + I2C_BOARD_INFO("twl4030", 0x48), + }, +}; + +static int beagle_mem_init(void) +{ + arm_add_mem_device("ram0", 0x80000000, 256 * 1024 * 1024); + + return 0; +} +mem_initcall(beagle_mem_init); + +static int beagle_devices_init(void) +{ +// i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); +// add_generic_device("i2c-omap", DEVICE_ID_DYNAMIC, NULL, OMAP_I2C1_BASE, SZ_4K, +// IORESOURCE_MEM, NULL); + +#ifdef CONFIG_USB_EHCI_OMAP +// if (ehci_omap_init(&omap_ehci_pdata) >= 0) +// add_usb_ehci_device(DEVICE_ID_DYNAMIC, OMAP_EHCI_BASE, +// OMAP_EHCI_BASE + 0x10, &ehci_pdata); +#endif /* CONFIG_USB_EHCI_OMAP */ +#ifdef CONFIG_OMAP_GPMC + /* WP is made high and WAIT1 active Low */ + //gpmc_generic_init(0x10); +#endif + + add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, 0x48060100, SZ_4K, + IORESOURCE_MEM, NULL); + + armlinux_set_bootparams((void *)0x80000100); + armlinux_set_architecture(MACH_TYPE_OMAP_GENERIC); + + return 0; +} +device_initcall(beagle_devices_init); diff --git a/arch/arm/boards/beaglebone/config.h b/arch/arm/boards/beaglebone/config.h new file mode 100644 index 0000000..b908fc0 --- /dev/null +++ b/arch/arm/boards/beaglebone/config.h @@ -0,0 +1,21 @@ +/** + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/beaglebone/env/config b/arch/arm/boards/beaglebone/env/config new file mode 100644 index 0000000..3aad658 --- /dev/null +++ b/arch/arm/boards/beaglebone/env/config @@ -0,0 +1,63 @@ +#!/bin/sh + +hostname=FIXME +if [ -z "$user" ]; then +# user= +fi + +# Enter MAC address here if not retrieved automatically +#eth0.ethaddr=de:ad:be:ef:00:00 + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp +dhcp_vendor_id=barebox + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.serverip=a.b.c.d +#eth0.gateway=a.b.c.d + +# can be either 'tftp', 'nfs', 'nand', 'nor' or 'disk' +kernel_loc=disk +# can be either 'net', 'nand', 'nor', 'disk' or 'initrd' +rootfs_loc=disk +# can be either 'tftp', 'nfs', 'nand', 'nor', 'disk' or none +oftree_loc=none + +# for flash based rootfs: 'jffs2' or 'ubifs' +# in case of disk any regular filesystem like 'ext2', 'ext3', 'reiserfs' +rootfs_type=ext4 +# where is the rootfs in case of 'rootfs_loc=disk' (linux name) +rootfs_part_linux_dev=mmcblk0p2 +rootfsimage=rootfs-${hostname}.$rootfs_type + +# where is the kernel image in case of 'kernel_loc=disk' +kernel_part=disk0.0 + +#kernelimage=zImage-$hostname +#kernelimage=uImage-$hostname +kernelimage=uImage +#kernelimage=Image-$hostname +#kernelimage=Image-$hostname.lzo + +bareboximage=barebox-${hostname}.bin +bareboxenvimage=barebox-${hostname}.bin + +if [ -n $user ]; then + bareboximage="$user"-"$bareboximage" + bareboxenvimage="$user"-"$bareboxenvimage" + kernelimage="$user"-"$kernelimage" + rootfsimage="$user"-"$rootfsimage" + nfsroot="/home/$user/nfsroot/$hostname" +else + nfsroot="/path/to/nfs/root" +fi + +autoboot_timeout=3 + +bootargs="console=ttyO0,115200n8" + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig index 386c484..117b1cf 100644 --- a/arch/arm/mach-omap/Kconfig +++ b/arch/arm/mach-omap/Kconfig @@ -98,7 +98,8 @@ config ARCH_TEXT_BASE config BOARDINFO default "Texas Instrument's SDP343x" if MACH_OMAP343xSDP - default "Texas Instrument's Beagle" if MACH_BEAGLE + default "Texas Instrument's Beagle Board" if MACH_BEAGLE + default "Texas Instrument's Beagle Bone" if MACH_BEAGLEBONE default "Texas Instrument's OMAP3EVM" if MACH_OMAP3EVM default "Texas Instrument's Panda" if MACH_PANDA default "Phytec phyCORE pcm049" if MACH_PCM049 @@ -123,6 +124,14 @@ config MACH_BEAGLE help Say Y here if you are using Beagle Board +config MACH_BEAGLEBONE + bool "Texas Instrument's Beagle Bone" + select OMAP_CLOCK_ALL + select HAVE_NOSHELL + depends on ARCH_OMAP3 + help + Say Y here if you are using Beagle Bone + config MACH_OMAP3EVM bool "Texas Instrument's OMAP3 EVM" select OMAP_CLOCK_ALL diff --git a/arch/arm/mach-omap/s32k_clksource.c b/arch/arm/mach-omap/s32k_clksource.c index 3ed9448..2c21fe7 100644 --- a/arch/arm/mach-omap/s32k_clksource.c +++ b/arch/arm/mach-omap/s32k_clksource.c @@ -50,7 +50,8 @@ */ static uint64_t s32k_clocksource_read(void) { - return readl(S32K_CR); +// return readl(S32K_CR); + return readl(0x44e0503c); } /* A bit obvious isn't it? */ @@ -73,6 +74,8 @@ static int s32k_clocksource_init(void) { s32k_cs.mult = clocksource_hz2mult(S32K_FREQUENCY, s32k_cs.shift); + writel(0x00000003, 0x44e05038); + return init_clock(&s32k_cs); } -- 1.7.10 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2012-06-29 11:43 UTC | newest] Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2012-06-26 9:51 Add basic support for the OMAP-L138/DA850 Jan Luebbe 2012-06-26 9:51 ` [PATCH 01/12] mach-davinci: add platform and minimal board file for HMI10 Jan Luebbe 2012-06-26 9:51 ` [PATCH 02/12] mach-davinci: add GPIO support Jan Luebbe 2012-06-26 9:51 ` [PATCH 03/12] mach-davinci: add pin mux support Jan Luebbe 2012-06-26 18:59 ` Sascha Hauer 2012-06-26 9:51 ` [PATCH 04/12] mach-davinci: setup pin mux for da850 Jan Luebbe 2012-06-26 19:00 ` Sascha Hauer 2012-06-26 9:51 ` [PATCH 05/12] mach-davinci: add support for the PSC (Power and Sleep Controller) Jan Luebbe 2012-06-26 19:02 ` Sascha Hauer 2012-06-26 9:51 ` [PATCH 06/12] mach-davinci: support the USB 1.1 host controller (based on OHCI) Jan Luebbe 2012-06-26 19:05 ` Sascha Hauer 2012-06-26 9:51 ` [PATCH 07/12] mach-davinci: add support for AEMIF (NAND flash) Jan Luebbe 2012-06-26 9:51 ` [PATCH 08/12] drivers/mtd/nand: add driver for the davinci NAND flash controller Jan Luebbe 2012-06-26 19:19 ` Sascha Hauer 2012-06-26 9:51 ` [PATCH 09/12] board hmi10: enable support for NAND Jan Luebbe 2012-06-26 9:51 ` [PATCH 10/12] drivers/spi: add driver for the davinci SPI master Jan Luebbe 2012-06-26 9:51 ` [PATCH 11/12] board hmi10: enable support for SPI Jan Luebbe 2012-06-26 9:51 ` [PATCH 12/12] board hmi10: add default config Jan Luebbe 2012-06-26 11:59 ` Add basic support for the OMAP-L138/DA850 Yegor Yefremov 2012-06-26 12:06 ` Jan Lübbe 2012-06-26 20:52 ` Yegor Yefremov 2012-06-29 11:42 ` [PATCH] Initial BeagleBone support for second stage Jan Luebbe
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