[PATCH 0/3] omap: 4460 support

[PATCH 0/3] omap: 4460 support

[Jan Weitzel]

Add support for OMAP4460 cpu
on top off 7b0de0e6 (next)

Jan Weitzel (3):
  Add support for OMAP4460 TPS62361
  OMAP4460: ram init changes
  OMAP4460: clock init

 arch/arm/boards/panda/lowlevel.c                |    4 +-
 arch/arm/boards/panda/mux.c                     |    8 +++
 arch/arm/boards/pcm049/lowlevel.c               |   15 ++++--
 arch/arm/boards/pcm049/mux.c                    |    8 +++
 arch/arm/boards/phycard-a-xl2/lowlevel.c        |    9 +++-
 arch/arm/boards/phycard-a-xl2/mux.c             |    8 +++
 arch/arm/mach-omap/include/mach/omap4-clock.h   |   19 +++++++
 arch/arm/mach-omap/include/mach/omap4-silicon.h |   13 +++++-
 arch/arm/mach-omap/omap4_clock.c                |   58 +++++++++++++++++-----
 arch/arm/mach-omap/omap4_generic.c              |   60 +++++++++++++++++++++--
 10 files changed, 178 insertions(+), 24 deletions(-)


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[PATCH 1/3] Add support for OMAP4460 TPS62361

[Jan Weitzel]

based on: [U-Boot] [PATCH v 4/5] omap4: support TPS programming
TPS62361 is the new power supply used in OMAP4460 that
supplies vdd_mpu.

VCORE1 from Phoenix supplies vdd_core and VCORE2 supplies
vdd_iva. VCORE3 is not used in OMAP4460.

Signed-off-by: F. Gasnier fabrice.gasnier@cenosys.com
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
---
 arch/arm/mach-omap/include/mach/omap4-clock.h   |   15 +++++++++
 arch/arm/mach-omap/include/mach/omap4-silicon.h |    9 +++++-
 arch/arm/mach-omap/omap4_clock.c                |   19 +++++++++++
 arch/arm/mach-omap/omap4_generic.c              |   39 +++++++++++++++++++++-
 4 files changed, 79 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap/include/mach/omap4-clock.h b/arch/arm/mach-omap/include/mach/omap4-clock.h
index 0a31d09..391ee63 100644
--- a/arch/arm/mach-omap/include/mach/omap4-clock.h
+++ b/arch/arm/mach-omap/include/mach/omap4-clock.h
@@ -271,6 +271,20 @@
 #define PLL_FAST_RELOCK_BYPASS	6 /* CORE */
 #define PLL_LOCK		7 /* MPU, IVA, CORE & PER */
 
+/* TPS */
+#define TPS62361_I2C_SLAVE_ADDR		0x60
+#define TPS62361_REG_ADDR_SET0		0x0
+#define TPS62361_REG_ADDR_SET1		0x1
+#define TPS62361_REG_ADDR_SET2		0x2
+#define TPS62361_REG_ADDR_SET3		0x3
+#define TPS62361_REG_ADDR_CTRL		0x4
+#define TPS62361_REG_ADDR_TEMP		0x5
+#define TPS62361_REG_ADDR_RMP_CTRL	0x6
+#define TPS62361_REG_ADDR_CHIP_ID	0x8
+#define TPS62361_REG_ADDR_CHIP_ID_2	0x9
+
+#define TPS62361_BASE_VOLT_MV	500
+
 /* Used to index into DPLL parameter tables */
 struct dpll_param {
 	unsigned int m;
@@ -317,4 +331,5 @@ void omap4_configure_core_dpll_no_lock(const struct dpll_param *param);
 void omap4_lock_core_dpll(void);
 void omap4_lock_core_dpll_shadow(const struct dpll_param *param);
 void omap4_enable_all_clocks(void);
+void omap4_do_scale_tps62361(u32 reg, u32 volt_mv);
 
diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
index c785475..d5517c5 100644
--- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
+++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
@@ -60,6 +60,13 @@
 #define OMAP44XX_PRM_VC_VAL_BYPASS	(OMAP44XX_WAKEUP_L4_IO_BASE + 0x7ba0)
 #define OMAP44XX_PRM_VC_CFG_I2C_MODE	(OMAP44XX_WAKEUP_L4_IO_BASE + 0x7ba8)
 #define OMAP44XX_PRM_VC_CFG_I2C_CLK	(OMAP44XX_WAKEUP_L4_IO_BASE + 0x7bac)
+#define OMAP44XX_PRM_VC_VAL_BYPASS_VALID_BIT		0x1000000
+#define OMAP44XX_PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT	0
+#define OMAP44XX_PRM_VC_VAL_BYPASS_SLAVEADDR_MASK	0x7F
+#define OMAP44XX_PRM_VC_VAL_BYPASS_REGADDR_SHIFT	8
+#define OMAP44XX_PRM_VC_VAL_BYPASS_REGADDR_MASK		0xFF
+#define OMAP44XX_PRM_VC_VAL_BYPASS_DATA_SHIFT		16
+#define OMAP44XX_PRM_VC_VAL_BYPASS_DATA_MASK		0xFF
 
 /* IRQ */
 #define OMAP44XX_PRM_IRQSTATUS_MPU_A9	(OMAP44XX_WAKEUP_L4_IO_BASE + 0x6010)
@@ -178,6 +185,6 @@ struct dpll_param;
 void omap4_ddr_init(const struct ddr_regs *, const struct dpll_param *);
 void omap4_power_i2c_send(u32);
 unsigned int omap4_revision(void);
-noinline int omap4_scale_vcores(void);
+noinline int omap4_scale_vcores(unsigned vsel0_pin);
 
 #endif
diff --git a/arch/arm/mach-omap/omap4_clock.c b/arch/arm/mach-omap/omap4_clock.c
index 3ab01f0..564a748 100644
--- a/arch/arm/mach-omap/omap4_clock.c
+++ b/arch/arm/mach-omap/omap4_clock.c
@@ -1,6 +1,7 @@
 #include <common.h>
 #include <io.h>
 #include <mach/syslib.h>
+#include <mach/silicon.h>
 #include <mach/clocks.h>
 
 #define LDELAY	12000000
@@ -378,3 +379,21 @@ void omap4_enable_all_clocks(void)
 	sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
 }
 
+void omap4_do_scale_tps62361(u32 reg, u32 volt_mv)
+{
+	u32 temp, step;
+
+	step = volt_mv - TPS62361_BASE_VOLT_MV;
+	step /= 10;
+
+	temp = TPS62361_I2C_SLAVE_ADDR |
+	    (reg << OMAP44XX_PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
+	    (step << OMAP44XX_PRM_VC_VAL_BYPASS_DATA_SHIFT) |
+	    OMAP44XX_PRM_VC_VAL_BYPASS_VALID_BIT;
+	debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
+
+	writel(temp, OMAP44XX_PRM_VC_VAL_BYPASS);
+	if (!wait_on_value(OMAP44XX_PRM_VC_VAL_BYPASS_VALID_BIT, 0,
+				OMAP44XX_PRM_VC_VAL_BYPASS, LDELAY))
+		puts("Scaling voltage failed for vdd_mpu from TPS\n");
+}
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index de69934..07aa2b4 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -7,6 +7,7 @@
 #include <mach/syslib.h>
 #include <mach/xload.h>
 #include <mach/gpmc.h>
+#include <mach/gpio.h>
 
 /*
  *  The following several lines are taken from U-Boot to support
@@ -466,7 +467,7 @@ enum omap_boot_src omap4_bootsrc(void)
 
 #define I2C_SLAVE 0x12
 
-noinline int omap4_scale_vcores(void)
+noinline int omap4_scale_vcores(unsigned vsel0_pin)
 {
 	unsigned int rev = omap4_revision();
 
@@ -476,8 +477,41 @@ noinline int omap4_scale_vcores(void)
 	writel(0, OMAP44XX_PRM_VC_CFG_I2C_MODE);
 	writel(0x6026, OMAP44XX_PRM_VC_CFG_I2C_CLK);
 
+	/* TPS - supplies vdd_mpu on 4460 */
+	if (rev >= OMAP4460_ES1_0) {
+		/*
+		 * Setup SET1 and SET0 with right values so that kernel
+		 * can use either of them based on its needs.
+		 */
+		omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET0, 1430);
+		omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET1, 1430);
+
+		/*
+		 * Select SET1 in TPS62361:
+		 * VSEL1 is grounded on board. So the following selects
+		 * VSEL1 = 0 and VSEL0 = 1
+		 */
+		gpio_direction_output(vsel0_pin, 0);
+		gpio_set_value(vsel0_pin, 1);
+	}
+
 	/* set VCORE1 force VSEL */
-	omap4_power_i2c_send((0x3A55 << 8) | I2C_SLAVE);
+	/*
+	 * 4430 : supplies vdd_mpu
+	 * Setting a high voltage for Nitro mode as smart reflex is not enabled.
+	 * We use the maximum possible value in the AVS range because the next
+	 * higher voltage in the discrete range (code >= 0b111010) is way too
+	 * high
+	 *
+	 * 4460 : supplies vdd_core
+	 *
+	 */
+	if (rev < OMAP4460_ES1_0)
+		/* 0x55: i2c addr, 3A: ~ 1430 mvolts*/
+		omap4_power_i2c_send((0x3A55 << 8) | I2C_SLAVE);
+	else
+		/* 0x55: i2c addr, 28: ~ 1200 mvolts*/
+		omap4_power_i2c_send((0x2855 << 8) | I2C_SLAVE);
 
 	/* FIXME: set VCORE2 force VSEL, Check the reset value */
 	omap4_power_i2c_send((0x295B << 8) | I2C_SLAVE);
@@ -490,6 +524,7 @@ noinline int omap4_scale_vcores(void)
 	case OMAP4430_ES2_1:
 		omap4_power_i2c_send((0x2A61 << 8) | I2C_SLAVE);
 		break;
+	/* > OMAP4460_ES1_0 : VCORE3 not connected */
 	}
 
 	return 0;
-- 
1.7.0.4


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Re: [PATCH 1/3] Add support for OMAP4460 TPS62361

[Sascha Hauer]

On Fri, Jul 27, 2012 at 03:40:02PM +0200, Jan Weitzel wrote:
> based on: [U-Boot] [PATCH v 4/5] omap4: support TPS programming
> TPS62361 is the new power supply used in OMAP4460 that
> supplies vdd_mpu.
> 
>  
> -noinline int omap4_scale_vcores(void)
> +noinline int omap4_scale_vcores(unsigned vsel0_pin)

Please fix the users of omap4_scale_vcores in this patch aswell.

Sascha

-- 
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[PATCH 3/3] OMAP4460: clock init

[Jan Weitzel]

Change clock init to allow early gpio access. Add support for 4460 clocks.

Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
---
v2: fix omap4_scale_vcores for phycard-a-xl2

 arch/arm/boards/panda/lowlevel.c              |    4 ++-
 arch/arm/boards/panda/mux.c                   |    8 +++++
 arch/arm/boards/pcm049/lowlevel.c             |   15 +++++++--
 arch/arm/boards/pcm049/mux.c                  |    8 +++++
 arch/arm/boards/phycard-a-xl2/lowlevel.c      |   13 ++++++--
 arch/arm/boards/phycard-a-xl2/mux.c           |    8 +++++
 arch/arm/mach-omap/include/mach/omap4-clock.h |    4 ++
 arch/arm/mach-omap/omap4_clock.c              |   39 +++++++++++++++++-------
 8 files changed, 79 insertions(+), 20 deletions(-)

diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c
index 8591fff..0b4b199 100644
--- a/arch/arm/boards/panda/lowlevel.c
+++ b/arch/arm/boards/panda/lowlevel.c
@@ -28,6 +28,8 @@
 #include <mach/syslib.h>
 #include <asm/barebox-arm.h>
 
+#define TPS62361_VSEL0_GPIO    7
+
 void set_muxconf_regs(void);
 
 static const struct ddr_regs ddr_regs_400_mhz_2cs = {
@@ -70,7 +72,7 @@ static void noinline panda_init_lowlevel(void)
 	omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core);
 
 	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
-	omap4_scale_vcores();
+	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
 
 	board_init_lowlevel_return();
 }
diff --git a/arch/arm/boards/panda/mux.c b/arch/arm/boards/panda/mux.c
index 310e433..3783006 100644
--- a/arch/arm/boards/panda/mux.c
+++ b/arch/arm/boards/panda/mux.c
@@ -3,6 +3,7 @@
 #include <io.h>
 #include <mach/omap4-silicon.h>
 #include <mach/omap4-mux.h>
+#include <mach/omap4-clock.h>
 
 static const struct pad_conf_entry core_padconf_array[] = {
 	{ GPMC_AD0, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat0 */ },
@@ -245,4 +246,11 @@ void set_muxconf_regs(void)
 
 	omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array,
 			ARRAY_SIZE(wkup_padconf_array));
+
+	/* gpio_wk7 is used for controlling TPS on 4460 */
+	if (omap4_revision() >= OMAP4460_ES1_0) {
+		writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + PAD1_FREF_CLK4_REQ);
+		/* Enable GPIO-1 clocks before TPS initialization */
+		omap4_enable_gpio1_wup_clocks();
+	}
 }
diff --git a/arch/arm/boards/pcm049/lowlevel.c b/arch/arm/boards/pcm049/lowlevel.c
index 5b91098..65a29ec 100644
--- a/arch/arm/boards/pcm049/lowlevel.c
+++ b/arch/arm/boards/pcm049/lowlevel.c
@@ -28,6 +28,8 @@
 #include <mach/syslib.h>
 #include <asm/barebox-arm.h>
 
+#define TPS62361_VSEL0_GPIO    182
+
 void set_muxconf_regs(void);
 
 static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = {
@@ -46,7 +48,8 @@ static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = {
 static void noinline pcm049_init_lowlevel(void)
 {
 	struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400;
-	struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
+	struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
+	struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920;
 	struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2;
 	struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2;
 	struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2;
@@ -57,12 +60,16 @@ static void noinline pcm049_init_lowlevel(void)
 	omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
 
 	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
-	omap4_scale_vcores();
+	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
 
 	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
 
 	/* Configure all DPLL's at 100% OPP */
-	omap4_configure_mpu_dpll(&mpu);
+	if (omap4_revision() < OMAP4460_ES1_0)
+		omap4_configure_mpu_dpll(&mpu44xx);
+	else
+		omap4_configure_mpu_dpll(&mpu4460);
+
 	omap4_configure_iva_dpll(&iva);
 	omap4_configure_per_dpll(&per);
 	omap4_configure_abe_dpll(&abe);
@@ -88,7 +95,7 @@ void board_init_lowlevel(void)
 		return;
 
 	r = 0x4030d000;
-        __asm__ __volatile__("mov sp, %0" : : "r"(r));
+	__asm__ __volatile__("mov sp, %0" : : "r"(r));
 
 	pcm049_init_lowlevel();
 }
diff --git a/arch/arm/boards/pcm049/mux.c b/arch/arm/boards/pcm049/mux.c
index a7a77b5..04e1d67 100644
--- a/arch/arm/boards/pcm049/mux.c
+++ b/arch/arm/boards/pcm049/mux.c
@@ -3,6 +3,7 @@
 #include <io.h>
 #include <mach/omap4-silicon.h>
 #include <mach/omap4-mux.h>
+#include <mach/omap4-clock.h>
 
 static const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_AD0, (IEN | PTD | DIS | M0)},				/* gpmc_ad0 */
@@ -242,4 +243,11 @@ void set_muxconf_regs(void)
 
 	omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array,
 			ARRAY_SIZE(wkup_padconf_array));
+
+	/* gpio_182 is used for controlling TPS on 4460 */
+	if (omap4_revision() >= OMAP4460_ES1_0) {
+		writew(M3, OMAP44XX_CONTROL_PADCONF_CORE + FREF_CLK2_OUT);
+		/* Enable GPIO-1 clocks before TPS initialization */
+		omap4_enable_gpio_clocks();
+	}
 }
diff --git a/arch/arm/boards/phycard-a-xl2/lowlevel.c b/arch/arm/boards/phycard-a-xl2/lowlevel.c
index b8de2aa..38f80c9 100644
--- a/arch/arm/boards/phycard-a-xl2/lowlevel.c
+++ b/arch/arm/boards/phycard-a-xl2/lowlevel.c
@@ -28,6 +28,8 @@
 #include <mach/syslib.h>
 #include <asm/barebox-arm.h>
 
+#define TPS62361_VSEL0_GPIO    7
+
 void set_muxconf_regs(void);
 
 static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = {
@@ -46,7 +48,8 @@ static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = {
 static noinline void pcaaxl2_init_lowlevel(void)
 {
 	struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400;
-	struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
+	struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
+	struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920;
 	struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2;
 	struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2;
 	struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2;
@@ -57,12 +60,16 @@ static noinline void pcaaxl2_init_lowlevel(void)
 	omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
 
 	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
-	omap4_scale_vcores();
+	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
 
 	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
 
 	/* Configure all DPLL's at 100% OPP */
-	omap4_configure_mpu_dpll(&mpu);
+	if (omap4_revision() < OMAP4460_ES1_0)
+		omap4_configure_mpu_dpll(&mpu44xx);
+	else
+		omap4_configure_mpu_dpll(&mpu4460);
+
 	omap4_configure_iva_dpll(&iva);
 	omap4_configure_per_dpll(&per);
 	omap4_configure_abe_dpll(&abe);
diff --git a/arch/arm/boards/phycard-a-xl2/mux.c b/arch/arm/boards/phycard-a-xl2/mux.c
index 179e6b6..dc605e3 100644
--- a/arch/arm/boards/phycard-a-xl2/mux.c
+++ b/arch/arm/boards/phycard-a-xl2/mux.c
@@ -3,6 +3,7 @@
 #include <io.h>
 #include <mach/omap4-silicon.h>
 #include <mach/omap4-mux.h>
+#include <mach/omap4-clock.h>
 
 static const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_AD0, (IEN | PTD | DIS | M0)},				/* gpmc_ad0 */
@@ -242,4 +243,11 @@ void set_muxconf_regs(void)
 
 	omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array,
 			ARRAY_SIZE(wkup_padconf_array));
+
+	/* gpio_wk7 is used for controlling TPS on 4460 */
+	if (omap4_revision() >= OMAP4460_ES1_0) {
+		writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + PAD1_FREF_CLK4_REQ);
+		/* Enable GPIO-1 clocks before TPS initialization */
+		omap4_enable_gpio1_wup_clocks();
+	}
 }
diff --git a/arch/arm/mach-omap/include/mach/omap4-clock.h b/arch/arm/mach-omap/include/mach/omap4-clock.h
index 391ee63..e5302d6 100644
--- a/arch/arm/mach-omap/include/mach/omap4-clock.h
+++ b/arch/arm/mach-omap/include/mach/omap4-clock.h
@@ -303,6 +303,8 @@ struct dpll_param {
 #define OMAP4_MPU_DPLL_PARAM_38M4		{0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
 #define OMAP4_MPU_DPLL_PARAM_38M4_MPU600	{0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
 #define OMAP4_MPU_DPLL_PARAM_38M4_MPU1000	{0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
+/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */
+#define OMAP4_MPU_DPLL_PARAM_19M2_MPU920	{0x23F, 0x11, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
 
 #define OMAP4_IVA_DPLL_PARAM_19M2		{0x61, 0x01, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}
 #define OMAP4_IVA_DPLL_PARAM_38M4		{0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}
@@ -330,6 +332,8 @@ void omap4_configure_usb_dpll(const struct dpll_param *dpll_param);
 void omap4_configure_core_dpll_no_lock(const struct dpll_param *param);
 void omap4_lock_core_dpll(void);
 void omap4_lock_core_dpll_shadow(const struct dpll_param *param);
+void omap4_enable_gpio1_wup_clocks(void);
+void omap4_enable_gpio_clocks(void);
 void omap4_enable_all_clocks(void);
 void omap4_do_scale_tps62361(u32 reg, u32 volt_mv);
 
diff --git a/arch/arm/mach-omap/omap4_clock.c b/arch/arm/mach-omap/omap4_clock.c
index 564a748..1481f16 100644
--- a/arch/arm/mach-omap/omap4_clock.c
+++ b/arch/arm/mach-omap/omap4_clock.c
@@ -14,6 +14,10 @@ void omap4_configure_mpu_dpll(const struct dpll_param *dpll_param)
 
 	sr32(CM_AUTOIDLE_DPLL_MPU, 0, 3, 0x0); /* Disable DPLL autoidle */
 
+	/* Errata ID: i700, clear CM_CLKSEL_DPLL_MPU[22] : DCC_EN */
+	if (omap4_revision() >= OMAP4460_ES1_0)
+		sr32(CM_CLKSEL_DPLL_MPU, 0, 22, 0);
+
 	/* Set M,N,M2 values */
 	sr32(CM_CLKSEL_DPLL_MPU, 8, 11, dpll_param->m);
 	sr32(CM_CLKSEL_DPLL_MPU, 0, 6, dpll_param->n);
@@ -198,6 +202,27 @@ void omap4_lock_core_dpll_shadow(const struct dpll_param *param)
 	wait_on_value((1 << 0), 1, CM_IDLEST_DPLL_CORE, LDELAY);
 }
 
+void omap4_enable_gpio_clocks(void)
+{
+	sr32(CM_L4PER_GPIO2_CLKCTRL, 0, 32, 0x1);
+	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY);
+	sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1);
+	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY);
+	sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1);
+	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY);
+	sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1);
+	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY);
+	sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1);
+	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY);
+}
+
+void omap4_enable_gpio1_wup_clocks(void)
+{
+	/* WKUP clocks */
+	sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1);
+	wait_on_value((1 << 17)|(1 << 16), 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY);
+}
+
 void omap4_enable_all_clocks(void)
 {
 	/* Enable Ducati clocks */
@@ -255,16 +280,7 @@ void omap4_enable_all_clocks(void)
 	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_DMTIMER9_CLKCTRL, LDELAY);
 
 	/* GPIO clocks */
-	sr32(CM_L4PER_GPIO2_CLKCTRL, 0, 32, 0x1);
-	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY);
-	sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1);
-	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY);
-	sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1);
-	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY);
-	sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1);
-	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY);
-	sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1);
-	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY);
+	omap4_enable_gpio_clocks();
 
 	sr32(CM_L4PER_HDQ1W_CLKCTRL, 0, 32, 0x2);
 
@@ -314,8 +330,7 @@ void omap4_enable_all_clocks(void)
 	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_UART4_CLKCTRL, LDELAY);
 
 	/* WKUP clocks */
-	sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1);
-	wait_on_value((1 << 17)|(1 << 16), 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY);
+	omap4_enable_gpio1_wup_clocks();
 	sr32(CM_WKUP_TIMER1_CLKCTRL, 0, 32, 0x01000002);
 	wait_on_value((1 << 17)|(1 << 16), 0, CM_WKUP_TIMER1_CLKCTRL, LDELAY);
 
-- 
1.7.0.4


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Re: [PATCH 3/3] OMAP4460: clock init

[Sascha Hauer]

Hi Jan,

On Mon, Aug 13, 2012 at 08:07:27AM +0200, Jan Weitzel wrote:
> Change clock init to allow early gpio access. Add support for 4460 clocks.
> 
> Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
> ---
> v2: fix omap4_scale_vcores for phycard-a-xl2

This changes the users of omap4_scale_vcores, but not the function
itself. Probably this should be merged with the earlier patch you sent.

Can you resend the whole series please when you have fixed this?

Thanks
 Sascha

> 
>  arch/arm/boards/panda/lowlevel.c              |    4 ++-
>  arch/arm/boards/panda/mux.c                   |    8 +++++
>  arch/arm/boards/pcm049/lowlevel.c             |   15 +++++++--
>  arch/arm/boards/pcm049/mux.c                  |    8 +++++
>  arch/arm/boards/phycard-a-xl2/lowlevel.c      |   13 ++++++--
>  arch/arm/boards/phycard-a-xl2/mux.c           |    8 +++++
>  arch/arm/mach-omap/include/mach/omap4-clock.h |    4 ++
>  arch/arm/mach-omap/omap4_clock.c              |   39 +++++++++++++++++-------
>  8 files changed, 79 insertions(+), 20 deletions(-)
> 
> diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c
> index 8591fff..0b4b199 100644
> --- a/arch/arm/boards/panda/lowlevel.c
> +++ b/arch/arm/boards/panda/lowlevel.c
> @@ -28,6 +28,8 @@
>  #include <mach/syslib.h>
>  #include <asm/barebox-arm.h>
>  
> +#define TPS62361_VSEL0_GPIO    7
> +
>  void set_muxconf_regs(void);
>  
>  static const struct ddr_regs ddr_regs_400_mhz_2cs = {
> @@ -70,7 +72,7 @@ static void noinline panda_init_lowlevel(void)
>  	omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core);
>  
>  	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
> -	omap4_scale_vcores();
> +	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
>  
>  	board_init_lowlevel_return();
>  }
> diff --git a/arch/arm/boards/panda/mux.c b/arch/arm/boards/panda/mux.c
> index 310e433..3783006 100644
> --- a/arch/arm/boards/panda/mux.c
> +++ b/arch/arm/boards/panda/mux.c
> @@ -3,6 +3,7 @@
>  #include <io.h>
>  #include <mach/omap4-silicon.h>
>  #include <mach/omap4-mux.h>
> +#include <mach/omap4-clock.h>
>  
>  static const struct pad_conf_entry core_padconf_array[] = {
>  	{ GPMC_AD0, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat0 */ },
> @@ -245,4 +246,11 @@ void set_muxconf_regs(void)
>  
>  	omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array,
>  			ARRAY_SIZE(wkup_padconf_array));
> +
> +	/* gpio_wk7 is used for controlling TPS on 4460 */
> +	if (omap4_revision() >= OMAP4460_ES1_0) {
> +		writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + PAD1_FREF_CLK4_REQ);
> +		/* Enable GPIO-1 clocks before TPS initialization */
> +		omap4_enable_gpio1_wup_clocks();
> +	}
>  }
> diff --git a/arch/arm/boards/pcm049/lowlevel.c b/arch/arm/boards/pcm049/lowlevel.c
> index 5b91098..65a29ec 100644
> --- a/arch/arm/boards/pcm049/lowlevel.c
> +++ b/arch/arm/boards/pcm049/lowlevel.c
> @@ -28,6 +28,8 @@
>  #include <mach/syslib.h>
>  #include <asm/barebox-arm.h>
>  
> +#define TPS62361_VSEL0_GPIO    182
> +
>  void set_muxconf_regs(void);
>  
>  static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = {
> @@ -46,7 +48,8 @@ static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = {
>  static void noinline pcm049_init_lowlevel(void)
>  {
>  	struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400;
> -	struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
> +	struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
> +	struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920;
>  	struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2;
>  	struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2;
>  	struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2;
> @@ -57,12 +60,16 @@ static void noinline pcm049_init_lowlevel(void)
>  	omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
>  
>  	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
> -	omap4_scale_vcores();
> +	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
>  
>  	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
>  
>  	/* Configure all DPLL's at 100% OPP */
> -	omap4_configure_mpu_dpll(&mpu);
> +	if (omap4_revision() < OMAP4460_ES1_0)
> +		omap4_configure_mpu_dpll(&mpu44xx);
> +	else
> +		omap4_configure_mpu_dpll(&mpu4460);
> +
>  	omap4_configure_iva_dpll(&iva);
>  	omap4_configure_per_dpll(&per);
>  	omap4_configure_abe_dpll(&abe);
> @@ -88,7 +95,7 @@ void board_init_lowlevel(void)
>  		return;
>  
>  	r = 0x4030d000;
> -        __asm__ __volatile__("mov sp, %0" : : "r"(r));
> +	__asm__ __volatile__("mov sp, %0" : : "r"(r));
>  
>  	pcm049_init_lowlevel();
>  }
> diff --git a/arch/arm/boards/pcm049/mux.c b/arch/arm/boards/pcm049/mux.c
> index a7a77b5..04e1d67 100644
> --- a/arch/arm/boards/pcm049/mux.c
> +++ b/arch/arm/boards/pcm049/mux.c
> @@ -3,6 +3,7 @@
>  #include <io.h>
>  #include <mach/omap4-silicon.h>
>  #include <mach/omap4-mux.h>
> +#include <mach/omap4-clock.h>
>  
>  static const struct pad_conf_entry core_padconf_array[] = {
>  	{GPMC_AD0, (IEN | PTD | DIS | M0)},				/* gpmc_ad0 */
> @@ -242,4 +243,11 @@ void set_muxconf_regs(void)
>  
>  	omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array,
>  			ARRAY_SIZE(wkup_padconf_array));
> +
> +	/* gpio_182 is used for controlling TPS on 4460 */
> +	if (omap4_revision() >= OMAP4460_ES1_0) {
> +		writew(M3, OMAP44XX_CONTROL_PADCONF_CORE + FREF_CLK2_OUT);
> +		/* Enable GPIO-1 clocks before TPS initialization */
> +		omap4_enable_gpio_clocks();
> +	}
>  }
> diff --git a/arch/arm/boards/phycard-a-xl2/lowlevel.c b/arch/arm/boards/phycard-a-xl2/lowlevel.c
> index b8de2aa..38f80c9 100644
> --- a/arch/arm/boards/phycard-a-xl2/lowlevel.c
> +++ b/arch/arm/boards/phycard-a-xl2/lowlevel.c
> @@ -28,6 +28,8 @@
>  #include <mach/syslib.h>
>  #include <asm/barebox-arm.h>
>  
> +#define TPS62361_VSEL0_GPIO    7
> +
>  void set_muxconf_regs(void);
>  
>  static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = {
> @@ -46,7 +48,8 @@ static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = {
>  static noinline void pcaaxl2_init_lowlevel(void)
>  {
>  	struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400;
> -	struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
> +	struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
> +	struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920;
>  	struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2;
>  	struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2;
>  	struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2;
> @@ -57,12 +60,16 @@ static noinline void pcaaxl2_init_lowlevel(void)
>  	omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
>  
>  	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
> -	omap4_scale_vcores();
> +	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
>  
>  	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
>  
>  	/* Configure all DPLL's at 100% OPP */
> -	omap4_configure_mpu_dpll(&mpu);
> +	if (omap4_revision() < OMAP4460_ES1_0)
> +		omap4_configure_mpu_dpll(&mpu44xx);
> +	else
> +		omap4_configure_mpu_dpll(&mpu4460);
> +
>  	omap4_configure_iva_dpll(&iva);
>  	omap4_configure_per_dpll(&per);
>  	omap4_configure_abe_dpll(&abe);
> diff --git a/arch/arm/boards/phycard-a-xl2/mux.c b/arch/arm/boards/phycard-a-xl2/mux.c
> index 179e6b6..dc605e3 100644
> --- a/arch/arm/boards/phycard-a-xl2/mux.c
> +++ b/arch/arm/boards/phycard-a-xl2/mux.c
> @@ -3,6 +3,7 @@
>  #include <io.h>
>  #include <mach/omap4-silicon.h>
>  #include <mach/omap4-mux.h>
> +#include <mach/omap4-clock.h>
>  
>  static const struct pad_conf_entry core_padconf_array[] = {
>  	{GPMC_AD0, (IEN | PTD | DIS | M0)},				/* gpmc_ad0 */
> @@ -242,4 +243,11 @@ void set_muxconf_regs(void)
>  
>  	omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array,
>  			ARRAY_SIZE(wkup_padconf_array));
> +
> +	/* gpio_wk7 is used for controlling TPS on 4460 */
> +	if (omap4_revision() >= OMAP4460_ES1_0) {
> +		writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + PAD1_FREF_CLK4_REQ);
> +		/* Enable GPIO-1 clocks before TPS initialization */
> +		omap4_enable_gpio1_wup_clocks();
> +	}
>  }
> diff --git a/arch/arm/mach-omap/include/mach/omap4-clock.h b/arch/arm/mach-omap/include/mach/omap4-clock.h
> index 391ee63..e5302d6 100644
> --- a/arch/arm/mach-omap/include/mach/omap4-clock.h
> +++ b/arch/arm/mach-omap/include/mach/omap4-clock.h
> @@ -303,6 +303,8 @@ struct dpll_param {
>  #define OMAP4_MPU_DPLL_PARAM_38M4		{0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
>  #define OMAP4_MPU_DPLL_PARAM_38M4_MPU600	{0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
>  #define OMAP4_MPU_DPLL_PARAM_38M4_MPU1000	{0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
> +/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */
> +#define OMAP4_MPU_DPLL_PARAM_19M2_MPU920	{0x23F, 0x11, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
>  
>  #define OMAP4_IVA_DPLL_PARAM_19M2		{0x61, 0x01, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}
>  #define OMAP4_IVA_DPLL_PARAM_38M4		{0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}
> @@ -330,6 +332,8 @@ void omap4_configure_usb_dpll(const struct dpll_param *dpll_param);
>  void omap4_configure_core_dpll_no_lock(const struct dpll_param *param);
>  void omap4_lock_core_dpll(void);
>  void omap4_lock_core_dpll_shadow(const struct dpll_param *param);
> +void omap4_enable_gpio1_wup_clocks(void);
> +void omap4_enable_gpio_clocks(void);
>  void omap4_enable_all_clocks(void);
>  void omap4_do_scale_tps62361(u32 reg, u32 volt_mv);
>  
> diff --git a/arch/arm/mach-omap/omap4_clock.c b/arch/arm/mach-omap/omap4_clock.c
> index 564a748..1481f16 100644
> --- a/arch/arm/mach-omap/omap4_clock.c
> +++ b/arch/arm/mach-omap/omap4_clock.c
> @@ -14,6 +14,10 @@ void omap4_configure_mpu_dpll(const struct dpll_param *dpll_param)
>  
>  	sr32(CM_AUTOIDLE_DPLL_MPU, 0, 3, 0x0); /* Disable DPLL autoidle */
>  
> +	/* Errata ID: i700, clear CM_CLKSEL_DPLL_MPU[22] : DCC_EN */
> +	if (omap4_revision() >= OMAP4460_ES1_0)
> +		sr32(CM_CLKSEL_DPLL_MPU, 0, 22, 0);
> +
>  	/* Set M,N,M2 values */
>  	sr32(CM_CLKSEL_DPLL_MPU, 8, 11, dpll_param->m);
>  	sr32(CM_CLKSEL_DPLL_MPU, 0, 6, dpll_param->n);
> @@ -198,6 +202,27 @@ void omap4_lock_core_dpll_shadow(const struct dpll_param *param)
>  	wait_on_value((1 << 0), 1, CM_IDLEST_DPLL_CORE, LDELAY);
>  }
>  
> +void omap4_enable_gpio_clocks(void)
> +{
> +	sr32(CM_L4PER_GPIO2_CLKCTRL, 0, 32, 0x1);
> +	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY);
> +	sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1);
> +	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY);
> +	sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1);
> +	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY);
> +	sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1);
> +	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY);
> +	sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1);
> +	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY);
> +}
> +
> +void omap4_enable_gpio1_wup_clocks(void)
> +{
> +	/* WKUP clocks */
> +	sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1);
> +	wait_on_value((1 << 17)|(1 << 16), 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY);
> +}
> +
>  void omap4_enable_all_clocks(void)
>  {
>  	/* Enable Ducati clocks */
> @@ -255,16 +280,7 @@ void omap4_enable_all_clocks(void)
>  	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_DMTIMER9_CLKCTRL, LDELAY);
>  
>  	/* GPIO clocks */
> -	sr32(CM_L4PER_GPIO2_CLKCTRL, 0, 32, 0x1);
> -	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY);
> -	sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1);
> -	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY);
> -	sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1);
> -	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY);
> -	sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1);
> -	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY);
> -	sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1);
> -	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY);
> +	omap4_enable_gpio_clocks();
>  
>  	sr32(CM_L4PER_HDQ1W_CLKCTRL, 0, 32, 0x2);
>  
> @@ -314,8 +330,7 @@ void omap4_enable_all_clocks(void)
>  	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_UART4_CLKCTRL, LDELAY);
>  
>  	/* WKUP clocks */
> -	sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1);
> -	wait_on_value((1 << 17)|(1 << 16), 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY);
> +	omap4_enable_gpio1_wup_clocks();
>  	sr32(CM_WKUP_TIMER1_CLKCTRL, 0, 32, 0x01000002);
>  	wait_on_value((1 << 17)|(1 << 16), 0, CM_WKUP_TIMER1_CLKCTRL, LDELAY);
>  
> -- 
> 1.7.0.4
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

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[PATCH 2/3] OMAP4460: ram init changes

[Jan Weitzel]

configure  Memory Adapter for 4460

Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
---
 arch/arm/mach-omap/include/mach/omap4-silicon.h |    4 ++++
 arch/arm/mach-omap/omap4_generic.c              |   21 +++++++++++++++++++--
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
index d5517c5..4082bac 100644
--- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
+++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
@@ -101,6 +101,10 @@
 #define DMM_LISA_MAP_SYS_SIZE_MASK	(7 << 20)
 #define DMM_LISA_MAP_SYS_SIZE_SHIFT	20
 #define DMM_LISA_MAP_SYS_ADDR_MASK	(0xFF << 24)
+
+/* Memory Adapter (4460 onwards) */
+#define OMAP44XX_MA_BASE		0x482AF000
+
 /*
  * Hardware Register Details
  */
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index 07aa2b4..a368759 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -29,6 +29,10 @@
 #define OMAP4460_CONTROL_ID_CODE_ES1_0  0x0B94E02F
 #define OMAP4460_CONTROL_ID_CODE_ES1_1  0x2B94E02F
 
+/* EMIF_L3_CONFIG register value */
+#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0		0x0A0000FF
+#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0	0x0A300000
+
 void __noreturn reset_cpu(unsigned long addr)
 {
 	writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
@@ -270,8 +274,7 @@ static void reset_phy(unsigned int base)
 void omap4_ddr_init(const struct ddr_regs *ddr_regs,
 		const struct dpll_param *core)
 {
-	unsigned int rev;
-	rev = omap4_revision();
+	unsigned int rev = omap4_revision();
 
 	if (rev == OMAP4430_ES2_0) {
 		writel(0x9e9e9e9e, 0x4A100638);
@@ -294,6 +297,13 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
 	*(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_2) = 0x00000000;
 	*(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100;
 
+	if (rev >= OMAP4460_ES1_0) {
+		writel(0x80640300, OMAP44XX_MA_BASE + DMM_LISA_MAP_0);
+
+		*(volatile int*)(OMAP44XX_MA_BASE + DMM_LISA_MAP_2) = 0x00000000;
+		*(volatile int*)(OMAP44XX_MA_BASE + DMM_LISA_MAP_3) = 0xFF020100;
+	}
+
 	/* DDR needs to be initialised @ 19.2 MHz
 	 * So put core DPLL in bypass mode
 	 * Configure the Core DPLL but don't lock it
@@ -336,6 +346,13 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
 	*(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000;
 	*(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000;
 
+	if (rev >= OMAP4460_ES1_0) {
+		writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
+				OMAP44XX_EMIF1_BASE + EMIF_L3_CONFIG);
+		writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
+				OMAP44XX_EMIF2_BASE + EMIF_L3_CONFIG);
+	}
+
 	/*
 	 * DMM : DMM_LISA_MAP_0(Section_0)
 	 * [31:24] SYS_ADDR 		0x80
-- 
1.7.0.4


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Re: [PATCH 2/3] OMAP4460: ram init changes

[Jean-Christophe PLAGNIOL-VILLARD]

On 15:40 Fri 27 Jul     , Jan Weitzel wrote:
> configure  Memory Adapter for 4460
> 
> Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
> ---
>  arch/arm/mach-omap/include/mach/omap4-silicon.h |    4 ++++
>  arch/arm/mach-omap/omap4_generic.c              |   21 +++++++++++++++++++--
>  2 files changed, 23 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
> index d5517c5..4082bac 100644
> --- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
> +++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
> @@ -101,6 +101,10 @@
>  #define DMM_LISA_MAP_SYS_SIZE_MASK	(7 << 20)
>  #define DMM_LISA_MAP_SYS_SIZE_SHIFT	20
>  #define DMM_LISA_MAP_SYS_ADDR_MASK	(0xFF << 24)
> +
> +/* Memory Adapter (4460 onwards) */
> +#define OMAP44XX_MA_BASE		0x482AF000
> +
>  /*
>   * Hardware Register Details
>   */
> diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
> index 07aa2b4..a368759 100644
> --- a/arch/arm/mach-omap/omap4_generic.c
> +++ b/arch/arm/mach-omap/omap4_generic.c
> @@ -29,6 +29,10 @@
>  #define OMAP4460_CONTROL_ID_CODE_ES1_0  0x0B94E02F
>  #define OMAP4460_CONTROL_ID_CODE_ES1_1  0x2B94E02F
>  
> +/* EMIF_L3_CONFIG register value */
> +#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0		0x0A0000FF
> +#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0	0x0A300000
> +
>  void __noreturn reset_cpu(unsigned long addr)
>  {
>  	writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
> @@ -270,8 +274,7 @@ static void reset_phy(unsigned int base)
>  void omap4_ddr_init(const struct ddr_regs *ddr_regs,
>  		const struct dpll_param *core)
>  {
> -	unsigned int rev;
> -	rev = omap4_revision();
> +	unsigned int rev = omap4_revision();
>  
>  	if (rev == OMAP4430_ES2_0) {
>  		writel(0x9e9e9e9e, 0x4A100638);
> @@ -294,6 +297,13 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
>  	*(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_2) = 0x00000000;
>  	*(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100;
>  
> +	if (rev >= OMAP4460_ES1_0) {
> +		writel(0x80640300, OMAP44XX_MA_BASE + DMM_LISA_MAP_0);
> +
> +		*(volatile int*)(OMAP44XX_MA_BASE + DMM_LISA_MAP_2) = 0x00000000;
> +		*(volatile int*)(OMAP44XX_MA_BASE + DMM_LISA_MAP_3) = 0xFF020100;
??

Best Regards,
J.

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Re: [PATCH 2/3] OMAP4460: ram init changes

[Sascha Hauer]

On Fri, Jul 27, 2012 at 04:13:46PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 15:40 Fri 27 Jul     , Jan Weitzel wrote:
> > configure  Memory Adapter for 4460
> > 
> > Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
> > ---
> >  arch/arm/mach-omap/include/mach/omap4-silicon.h |    4 ++++
> >  arch/arm/mach-omap/omap4_generic.c              |   21 +++++++++++++++++++--
> >  2 files changed, 23 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
> > index d5517c5..4082bac 100644
> > --- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
> > +++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
> > @@ -101,6 +101,10 @@
> >  #define DMM_LISA_MAP_SYS_SIZE_MASK	(7 << 20)
> >  #define DMM_LISA_MAP_SYS_SIZE_SHIFT	20
> >  #define DMM_LISA_MAP_SYS_ADDR_MASK	(0xFF << 24)
> > +
> > +/* Memory Adapter (4460 onwards) */
> > +#define OMAP44XX_MA_BASE		0x482AF000
> > +
> >  /*
> >   * Hardware Register Details
> >   */
> > diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
> > index 07aa2b4..a368759 100644
> > --- a/arch/arm/mach-omap/omap4_generic.c
> > +++ b/arch/arm/mach-omap/omap4_generic.c
> > @@ -29,6 +29,10 @@
> >  #define OMAP4460_CONTROL_ID_CODE_ES1_0  0x0B94E02F
> >  #define OMAP4460_CONTROL_ID_CODE_ES1_1  0x2B94E02F
> >  
> > +/* EMIF_L3_CONFIG register value */
> > +#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0		0x0A0000FF
> > +#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0	0x0A300000
> > +
> >  void __noreturn reset_cpu(unsigned long addr)
> >  {
> >  	writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
> > @@ -270,8 +274,7 @@ static void reset_phy(unsigned int base)
> >  void omap4_ddr_init(const struct ddr_regs *ddr_regs,
> >  		const struct dpll_param *core)
> >  {
> > -	unsigned int rev;
> > -	rev = omap4_revision();
> > +	unsigned int rev = omap4_revision();
> >  
> >  	if (rev == OMAP4430_ES2_0) {
> >  		writel(0x9e9e9e9e, 0x4A100638);
> > @@ -294,6 +297,13 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
> >  	*(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_2) = 0x00000000;
> >  	*(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100;
> >  
> > +	if (rev >= OMAP4460_ES1_0) {
> > +		writel(0x80640300, OMAP44XX_MA_BASE + DMM_LISA_MAP_0);
> > +
> > +		*(volatile int*)(OMAP44XX_MA_BASE + DMM_LISA_MAP_2) = 0x00000000;
> > +		*(volatile int*)(OMAP44XX_MA_BASE + DMM_LISA_MAP_3) = 0xFF020100;
> ??

There are bad examples in this file already, see the context of this
patch. Should be fixed before we add more stuff.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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[PATCH] OMAP4: use writel and readl

[Jan Weitzel]

replace *(volatile int*) bei writel and readl

Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
---
 arch/arm/mach-omap/omap4_generic.c |   34 ++++++++++++++++++----------------
 1 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index a368759..617d786 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -268,7 +268,9 @@ int omap4_emif_config(unsigned int base, const struct ddr_regs *ddr_regs)
 
 static void reset_phy(unsigned int base)
 {
-	*(volatile int*)(base + IODFT_TLGC) |= (1 << 10);
+	unsigned int val = readl(base + IODFT_TLGC);
+	val |= (1 << 10);
+	writel(val, base + IODFT_TLGC);
 }
 
 void omap4_ddr_init(const struct ddr_regs *ddr_regs,
@@ -294,14 +296,14 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
 	/* Both EMIFs 128 byte interleaved */
 	writel(0x80640300, OMAP44XX_DMM_BASE + DMM_LISA_MAP_0);
 
-	*(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_2) = 0x00000000;
-	*(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100;
+	writel(0x00000000, OMAP44XX_DMM_BASE + DMM_LISA_MAP_2);
+	writel(0xFF020100, OMAP44XX_DMM_BASE + DMM_LISA_MAP_3);
 
 	if (rev >= OMAP4460_ES1_0) {
 		writel(0x80640300, OMAP44XX_MA_BASE + DMM_LISA_MAP_0);
 
-		*(volatile int*)(OMAP44XX_MA_BASE + DMM_LISA_MAP_2) = 0x00000000;
-		*(volatile int*)(OMAP44XX_MA_BASE + DMM_LISA_MAP_3) = 0xFF020100;
+		writel(0x00000000, OMAP44XX_MA_BASE + DMM_LISA_MAP_2);
+		writel(0xFF020100, OMAP44XX_MA_BASE + DMM_LISA_MAP_3);
 	}
 
 	/* DDR needs to be initialised @ 19.2 MHz
@@ -312,10 +314,10 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
 
 	/* No IDLE: BUG in SDC */
 	sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
-	while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
+	while ((readl(CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
 
-	*(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x0;
-	*(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x0;
+	writel(0x0, OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
+	writel(0x0, OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
 
 	omap4_emif_config(OMAP44XX_EMIF1_BASE, ddr_regs);
 	omap4_emif_config(OMAP44XX_EMIF2_BASE, ddr_regs);
@@ -324,13 +326,13 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
 	omap4_lock_core_dpll_shadow(core);
 
 	/* Set DLL_OVERRIDE = 0 */
-	*(volatile int*)CM_DLL_CTRL = 0x0;
+	writel(0x0, CM_DLL_CTRL);
 
 	delay(200);
 
 	/* Check for DDR PHY ready for EMIF1 & EMIF2 */
-	while((((*(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_STATUS))&(0x04)) != 0x04) \
-	|| (((*(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_STATUS))&(0x04)) != 0x04));
+	while (((readl(OMAP44XX_EMIF1_BASE + EMIF_STATUS) & 0x04) != 0x04) \
+		|| ((readl(OMAP44XX_EMIF2_BASE + EMIF_STATUS) & 0x04) != 0x04));
 
 	/* Reprogram the DDR PYHY Control register */
 	/* PHY control values */
@@ -342,9 +344,9 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
 
 	/* No IDLE: BUG in SDC */
 	//sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
-	//while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
-	*(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000;
-	*(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000;
+	//while ((readl(CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
+	writel(0x80000000, OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
+	writel(0x80000000, OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
 
 	if (rev >= OMAP4460_ES1_0) {
 		writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
@@ -365,8 +367,8 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
 	reset_phy(OMAP44XX_EMIF1_BASE);
 	reset_phy(OMAP44XX_EMIF2_BASE);
 
-	*((volatile int *)0x80000000) = 0;
-	*((volatile int *)0x80000080) = 0;
+	writel(0, 0x80000000);
+	writel(0, 0x80000080);
 }
 
 void omap4_power_i2c_send(u32 r)
-- 
1.7.0.4


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[PATCH v2] OMAP4: use writel and readl

[Jan Weitzel]

replace *(volatile int*) by writel and readl

Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
---
v2 reword commit message

 arch/arm/mach-omap/omap4_generic.c |   34 ++++++++++++++++++----------------
 1 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index a368759..617d786 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -268,7 +268,9 @@ int omap4_emif_config(unsigned int base, const struct ddr_regs *ddr_regs)
 
 static void reset_phy(unsigned int base)
 {
-	*(volatile int*)(base + IODFT_TLGC) |= (1 << 10);
+	unsigned int val = readl(base + IODFT_TLGC);
+	val |= (1 << 10);
+	writel(val, base + IODFT_TLGC);
 }
 
 void omap4_ddr_init(const struct ddr_regs *ddr_regs,
@@ -294,14 +296,14 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
 	/* Both EMIFs 128 byte interleaved */
 	writel(0x80640300, OMAP44XX_DMM_BASE + DMM_LISA_MAP_0);
 
-	*(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_2) = 0x00000000;
-	*(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100;
+	writel(0x00000000, OMAP44XX_DMM_BASE + DMM_LISA_MAP_2);
+	writel(0xFF020100, OMAP44XX_DMM_BASE + DMM_LISA_MAP_3);
 
 	if (rev >= OMAP4460_ES1_0) {
 		writel(0x80640300, OMAP44XX_MA_BASE + DMM_LISA_MAP_0);
 
-		*(volatile int*)(OMAP44XX_MA_BASE + DMM_LISA_MAP_2) = 0x00000000;
-		*(volatile int*)(OMAP44XX_MA_BASE + DMM_LISA_MAP_3) = 0xFF020100;
+		writel(0x00000000, OMAP44XX_MA_BASE + DMM_LISA_MAP_2);
+		writel(0xFF020100, OMAP44XX_MA_BASE + DMM_LISA_MAP_3);
 	}
 
 	/* DDR needs to be initialised @ 19.2 MHz
@@ -312,10 +314,10 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
 
 	/* No IDLE: BUG in SDC */
 	sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
-	while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
+	while ((readl(CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
 
-	*(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x0;
-	*(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x0;
+	writel(0x0, OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
+	writel(0x0, OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
 
 	omap4_emif_config(OMAP44XX_EMIF1_BASE, ddr_regs);
 	omap4_emif_config(OMAP44XX_EMIF2_BASE, ddr_regs);
@@ -324,13 +326,13 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
 	omap4_lock_core_dpll_shadow(core);
 
 	/* Set DLL_OVERRIDE = 0 */
-	*(volatile int*)CM_DLL_CTRL = 0x0;
+	writel(0x0, CM_DLL_CTRL);
 
 	delay(200);
 
 	/* Check for DDR PHY ready for EMIF1 & EMIF2 */
-	while((((*(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_STATUS))&(0x04)) != 0x04) \
-	|| (((*(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_STATUS))&(0x04)) != 0x04));
+	while (((readl(OMAP44XX_EMIF1_BASE + EMIF_STATUS) & 0x04) != 0x04) \
+		|| ((readl(OMAP44XX_EMIF2_BASE + EMIF_STATUS) & 0x04) != 0x04));
 
 	/* Reprogram the DDR PYHY Control register */
 	/* PHY control values */
@@ -342,9 +344,9 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
 
 	/* No IDLE: BUG in SDC */
 	//sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
-	//while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
-	*(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000;
-	*(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000;
+	//while ((readl(CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
+	writel(0x80000000, OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
+	writel(0x80000000, OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
 
 	if (rev >= OMAP4460_ES1_0) {
 		writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
@@ -365,8 +367,8 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
 	reset_phy(OMAP44XX_EMIF1_BASE);
 	reset_phy(OMAP44XX_EMIF2_BASE);
 
-	*((volatile int *)0x80000000) = 0;
-	*((volatile int *)0x80000080) = 0;
+	writel(0, 0x80000000);
+	writel(0, 0x80000080);
 }
 
 void omap4_power_i2c_send(u32 r)
-- 
1.7.0.4


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Re: [PATCH v2] OMAP4: use writel and readl

[Sascha Hauer]

On Mon, Aug 13, 2012 at 02:32:15PM +0200, Jan Weitzel wrote:
> replace *(volatile int*) by writel and readl
> 
> Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
> ---
> v2 reword commit message

Updated, thanks. I also added a ARM prefix to the subject.

Sascha

> 
>  arch/arm/mach-omap/omap4_generic.c |   34 ++++++++++++++++++----------------
>  1 files changed, 18 insertions(+), 16 deletions(-)
> 
> diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
> index a368759..617d786 100644
> --- a/arch/arm/mach-omap/omap4_generic.c
> +++ b/arch/arm/mach-omap/omap4_generic.c
> @@ -268,7 +268,9 @@ int omap4_emif_config(unsigned int base, const struct ddr_regs *ddr_regs)
>  
>  static void reset_phy(unsigned int base)
>  {
> -	*(volatile int*)(base + IODFT_TLGC) |= (1 << 10);
> +	unsigned int val = readl(base + IODFT_TLGC);
> +	val |= (1 << 10);
> +	writel(val, base + IODFT_TLGC);
>  }
>  
>  void omap4_ddr_init(const struct ddr_regs *ddr_regs,
> @@ -294,14 +296,14 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
>  	/* Both EMIFs 128 byte interleaved */
>  	writel(0x80640300, OMAP44XX_DMM_BASE + DMM_LISA_MAP_0);
>  
> -	*(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_2) = 0x00000000;
> -	*(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100;
> +	writel(0x00000000, OMAP44XX_DMM_BASE + DMM_LISA_MAP_2);
> +	writel(0xFF020100, OMAP44XX_DMM_BASE + DMM_LISA_MAP_3);
>  
>  	if (rev >= OMAP4460_ES1_0) {
>  		writel(0x80640300, OMAP44XX_MA_BASE + DMM_LISA_MAP_0);
>  
> -		*(volatile int*)(OMAP44XX_MA_BASE + DMM_LISA_MAP_2) = 0x00000000;
> -		*(volatile int*)(OMAP44XX_MA_BASE + DMM_LISA_MAP_3) = 0xFF020100;
> +		writel(0x00000000, OMAP44XX_MA_BASE + DMM_LISA_MAP_2);
> +		writel(0xFF020100, OMAP44XX_MA_BASE + DMM_LISA_MAP_3);
>  	}
>  
>  	/* DDR needs to be initialised @ 19.2 MHz
> @@ -312,10 +314,10 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
>  
>  	/* No IDLE: BUG in SDC */
>  	sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
> -	while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
> +	while ((readl(CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
>  
> -	*(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x0;
> -	*(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x0;
> +	writel(0x0, OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
> +	writel(0x0, OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
>  
>  	omap4_emif_config(OMAP44XX_EMIF1_BASE, ddr_regs);
>  	omap4_emif_config(OMAP44XX_EMIF2_BASE, ddr_regs);
> @@ -324,13 +326,13 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
>  	omap4_lock_core_dpll_shadow(core);
>  
>  	/* Set DLL_OVERRIDE = 0 */
> -	*(volatile int*)CM_DLL_CTRL = 0x0;
> +	writel(0x0, CM_DLL_CTRL);
>  
>  	delay(200);
>  
>  	/* Check for DDR PHY ready for EMIF1 & EMIF2 */
> -	while((((*(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_STATUS))&(0x04)) != 0x04) \
> -	|| (((*(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_STATUS))&(0x04)) != 0x04));
> +	while (((readl(OMAP44XX_EMIF1_BASE + EMIF_STATUS) & 0x04) != 0x04) \
> +		|| ((readl(OMAP44XX_EMIF2_BASE + EMIF_STATUS) & 0x04) != 0x04));
>  
>  	/* Reprogram the DDR PYHY Control register */
>  	/* PHY control values */
> @@ -342,9 +344,9 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
>  
>  	/* No IDLE: BUG in SDC */
>  	//sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
> -	//while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
> -	*(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000;
> -	*(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000;
> +	//while ((readl(CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
> +	writel(0x80000000, OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
> +	writel(0x80000000, OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
>  
>  	if (rev >= OMAP4460_ES1_0) {
>  		writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
> @@ -365,8 +367,8 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
>  	reset_phy(OMAP44XX_EMIF1_BASE);
>  	reset_phy(OMAP44XX_EMIF2_BASE);
>  
> -	*((volatile int *)0x80000000) = 0;
> -	*((volatile int *)0x80000080) = 0;
> +	writel(0, 0x80000000);
> +	writel(0, 0x80000080);
>  }
>  
>  void omap4_power_i2c_send(u32 r)
> -- 
> 1.7.0.4
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

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[PATCH 3/3] OMAP4460: clock init

[Jan Weitzel]

Change clock init to allow early gpio access. Add support for 4460 clocks.

Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
---
 arch/arm/boards/panda/lowlevel.c              |    4 ++-
 arch/arm/boards/panda/mux.c                   |    8 +++++
 arch/arm/boards/pcm049/lowlevel.c             |   15 +++++++--
 arch/arm/boards/pcm049/mux.c                  |    8 +++++
 arch/arm/boards/phycard-a-xl2/lowlevel.c      |    9 ++++-
 arch/arm/boards/phycard-a-xl2/mux.c           |    8 +++++
 arch/arm/mach-omap/include/mach/omap4-clock.h |    4 ++
 arch/arm/mach-omap/omap4_clock.c              |   39 +++++++++++++++++-------
 8 files changed, 76 insertions(+), 19 deletions(-)

diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c
index 8591fff..0b4b199 100644
--- a/arch/arm/boards/panda/lowlevel.c
+++ b/arch/arm/boards/panda/lowlevel.c
@@ -28,6 +28,8 @@
 #include <mach/syslib.h>
 #include <asm/barebox-arm.h>
 
+#define TPS62361_VSEL0_GPIO    7
+
 void set_muxconf_regs(void);
 
 static const struct ddr_regs ddr_regs_400_mhz_2cs = {
@@ -70,7 +72,7 @@ static void noinline panda_init_lowlevel(void)
 	omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core);
 
 	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
-	omap4_scale_vcores();
+	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
 
 	board_init_lowlevel_return();
 }
diff --git a/arch/arm/boards/panda/mux.c b/arch/arm/boards/panda/mux.c
index 310e433..3783006 100644
--- a/arch/arm/boards/panda/mux.c
+++ b/arch/arm/boards/panda/mux.c
@@ -3,6 +3,7 @@
 #include <io.h>
 #include <mach/omap4-silicon.h>
 #include <mach/omap4-mux.h>
+#include <mach/omap4-clock.h>
 
 static const struct pad_conf_entry core_padconf_array[] = {
 	{ GPMC_AD0, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat0 */ },
@@ -245,4 +246,11 @@ void set_muxconf_regs(void)
 
 	omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array,
 			ARRAY_SIZE(wkup_padconf_array));
+
+	/* gpio_wk7 is used for controlling TPS on 4460 */
+	if (omap4_revision() >= OMAP4460_ES1_0) {
+		writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + PAD1_FREF_CLK4_REQ);
+		/* Enable GPIO-1 clocks before TPS initialization */
+		omap4_enable_gpio1_wup_clocks();
+	}
 }
diff --git a/arch/arm/boards/pcm049/lowlevel.c b/arch/arm/boards/pcm049/lowlevel.c
index 5b91098..65a29ec 100644
--- a/arch/arm/boards/pcm049/lowlevel.c
+++ b/arch/arm/boards/pcm049/lowlevel.c
@@ -28,6 +28,8 @@
 #include <mach/syslib.h>
 #include <asm/barebox-arm.h>
 
+#define TPS62361_VSEL0_GPIO    182
+
 void set_muxconf_regs(void);
 
 static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = {
@@ -46,7 +48,8 @@ static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = {
 static void noinline pcm049_init_lowlevel(void)
 {
 	struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400;
-	struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
+	struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
+	struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920;
 	struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2;
 	struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2;
 	struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2;
@@ -57,12 +60,16 @@ static void noinline pcm049_init_lowlevel(void)
 	omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
 
 	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
-	omap4_scale_vcores();
+	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
 
 	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
 
 	/* Configure all DPLL's at 100% OPP */
-	omap4_configure_mpu_dpll(&mpu);
+	if (omap4_revision() < OMAP4460_ES1_0)
+		omap4_configure_mpu_dpll(&mpu44xx);
+	else
+		omap4_configure_mpu_dpll(&mpu4460);
+
 	omap4_configure_iva_dpll(&iva);
 	omap4_configure_per_dpll(&per);
 	omap4_configure_abe_dpll(&abe);
@@ -88,7 +95,7 @@ void board_init_lowlevel(void)
 		return;
 
 	r = 0x4030d000;
-        __asm__ __volatile__("mov sp, %0" : : "r"(r));
+	__asm__ __volatile__("mov sp, %0" : : "r"(r));
 
 	pcm049_init_lowlevel();
 }
diff --git a/arch/arm/boards/pcm049/mux.c b/arch/arm/boards/pcm049/mux.c
index a7a77b5..04e1d67 100644
--- a/arch/arm/boards/pcm049/mux.c
+++ b/arch/arm/boards/pcm049/mux.c
@@ -3,6 +3,7 @@
 #include <io.h>
 #include <mach/omap4-silicon.h>
 #include <mach/omap4-mux.h>
+#include <mach/omap4-clock.h>
 
 static const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_AD0, (IEN | PTD | DIS | M0)},				/* gpmc_ad0 */
@@ -242,4 +243,11 @@ void set_muxconf_regs(void)
 
 	omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array,
 			ARRAY_SIZE(wkup_padconf_array));
+
+	/* gpio_182 is used for controlling TPS on 4460 */
+	if (omap4_revision() >= OMAP4460_ES1_0) {
+		writew(M3, OMAP44XX_CONTROL_PADCONF_CORE + FREF_CLK2_OUT);
+		/* Enable GPIO-1 clocks before TPS initialization */
+		omap4_enable_gpio_clocks();
+	}
 }
diff --git a/arch/arm/boards/phycard-a-xl2/lowlevel.c b/arch/arm/boards/phycard-a-xl2/lowlevel.c
index b8de2aa..fc599d8 100644
--- a/arch/arm/boards/phycard-a-xl2/lowlevel.c
+++ b/arch/arm/boards/phycard-a-xl2/lowlevel.c
@@ -46,7 +46,8 @@ static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = {
 static noinline void pcaaxl2_init_lowlevel(void)
 {
 	struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400;
-	struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
+	struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
+	struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920;
 	struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2;
 	struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2;
 	struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2;
@@ -62,7 +63,11 @@ static noinline void pcaaxl2_init_lowlevel(void)
 	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
 
 	/* Configure all DPLL's at 100% OPP */
-	omap4_configure_mpu_dpll(&mpu);
+	if (omap4_revision() < OMAP4460_ES1_0)
+		omap4_configure_mpu_dpll(&mpu44xx);
+	else
+		omap4_configure_mpu_dpll(&mpu4460);
+
 	omap4_configure_iva_dpll(&iva);
 	omap4_configure_per_dpll(&per);
 	omap4_configure_abe_dpll(&abe);
diff --git a/arch/arm/boards/phycard-a-xl2/mux.c b/arch/arm/boards/phycard-a-xl2/mux.c
index 179e6b6..dc605e3 100644
--- a/arch/arm/boards/phycard-a-xl2/mux.c
+++ b/arch/arm/boards/phycard-a-xl2/mux.c
@@ -3,6 +3,7 @@
 #include <io.h>
 #include <mach/omap4-silicon.h>
 #include <mach/omap4-mux.h>
+#include <mach/omap4-clock.h>
 
 static const struct pad_conf_entry core_padconf_array[] = {
 	{GPMC_AD0, (IEN | PTD | DIS | M0)},				/* gpmc_ad0 */
@@ -242,4 +243,11 @@ void set_muxconf_regs(void)
 
 	omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array,
 			ARRAY_SIZE(wkup_padconf_array));
+
+	/* gpio_wk7 is used for controlling TPS on 4460 */
+	if (omap4_revision() >= OMAP4460_ES1_0) {
+		writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + PAD1_FREF_CLK4_REQ);
+		/* Enable GPIO-1 clocks before TPS initialization */
+		omap4_enable_gpio1_wup_clocks();
+	}
 }
diff --git a/arch/arm/mach-omap/include/mach/omap4-clock.h b/arch/arm/mach-omap/include/mach/omap4-clock.h
index 391ee63..e5302d6 100644
--- a/arch/arm/mach-omap/include/mach/omap4-clock.h
+++ b/arch/arm/mach-omap/include/mach/omap4-clock.h
@@ -303,6 +303,8 @@ struct dpll_param {
 #define OMAP4_MPU_DPLL_PARAM_38M4		{0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
 #define OMAP4_MPU_DPLL_PARAM_38M4_MPU600	{0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
 #define OMAP4_MPU_DPLL_PARAM_38M4_MPU1000	{0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
+/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */
+#define OMAP4_MPU_DPLL_PARAM_19M2_MPU920	{0x23F, 0x11, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
 
 #define OMAP4_IVA_DPLL_PARAM_19M2		{0x61, 0x01, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}
 #define OMAP4_IVA_DPLL_PARAM_38M4		{0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}
@@ -330,6 +332,8 @@ void omap4_configure_usb_dpll(const struct dpll_param *dpll_param);
 void omap4_configure_core_dpll_no_lock(const struct dpll_param *param);
 void omap4_lock_core_dpll(void);
 void omap4_lock_core_dpll_shadow(const struct dpll_param *param);
+void omap4_enable_gpio1_wup_clocks(void);
+void omap4_enable_gpio_clocks(void);
 void omap4_enable_all_clocks(void);
 void omap4_do_scale_tps62361(u32 reg, u32 volt_mv);
 
diff --git a/arch/arm/mach-omap/omap4_clock.c b/arch/arm/mach-omap/omap4_clock.c
index 564a748..1481f16 100644
--- a/arch/arm/mach-omap/omap4_clock.c
+++ b/arch/arm/mach-omap/omap4_clock.c
@@ -14,6 +14,10 @@ void omap4_configure_mpu_dpll(const struct dpll_param *dpll_param)
 
 	sr32(CM_AUTOIDLE_DPLL_MPU, 0, 3, 0x0); /* Disable DPLL autoidle */
 
+	/* Errata ID: i700, clear CM_CLKSEL_DPLL_MPU[22] : DCC_EN */
+	if (omap4_revision() >= OMAP4460_ES1_0)
+		sr32(CM_CLKSEL_DPLL_MPU, 0, 22, 0);
+
 	/* Set M,N,M2 values */
 	sr32(CM_CLKSEL_DPLL_MPU, 8, 11, dpll_param->m);
 	sr32(CM_CLKSEL_DPLL_MPU, 0, 6, dpll_param->n);
@@ -198,6 +202,27 @@ void omap4_lock_core_dpll_shadow(const struct dpll_param *param)
 	wait_on_value((1 << 0), 1, CM_IDLEST_DPLL_CORE, LDELAY);
 }
 
+void omap4_enable_gpio_clocks(void)
+{
+	sr32(CM_L4PER_GPIO2_CLKCTRL, 0, 32, 0x1);
+	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY);
+	sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1);
+	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY);
+	sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1);
+	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY);
+	sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1);
+	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY);
+	sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1);
+	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY);
+}
+
+void omap4_enable_gpio1_wup_clocks(void)
+{
+	/* WKUP clocks */
+	sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1);
+	wait_on_value((1 << 17)|(1 << 16), 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY);
+}
+
 void omap4_enable_all_clocks(void)
 {
 	/* Enable Ducati clocks */
@@ -255,16 +280,7 @@ void omap4_enable_all_clocks(void)
 	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_DMTIMER9_CLKCTRL, LDELAY);
 
 	/* GPIO clocks */
-	sr32(CM_L4PER_GPIO2_CLKCTRL, 0, 32, 0x1);
-	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY);
-	sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1);
-	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY);
-	sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1);
-	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY);
-	sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1);
-	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY);
-	sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1);
-	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY);
+	omap4_enable_gpio_clocks();
 
 	sr32(CM_L4PER_HDQ1W_CLKCTRL, 0, 32, 0x2);
 
@@ -314,8 +330,7 @@ void omap4_enable_all_clocks(void)
 	wait_on_value((1 << 17)|(1 << 16), 0, CM_L4PER_UART4_CLKCTRL, LDELAY);
 
 	/* WKUP clocks */
-	sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1);
-	wait_on_value((1 << 17)|(1 << 16), 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY);
+	omap4_enable_gpio1_wup_clocks();
 	sr32(CM_WKUP_TIMER1_CLKCTRL, 0, 32, 0x01000002);
 	wait_on_value((1 << 17)|(1 << 16), 0, CM_WKUP_TIMER1_CLKCTRL, LDELAY);
 
-- 
1.7.0.4


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Re: [PATCH 3/3] OMAP4460: clock init

[Jean-Christophe PLAGNIOL-VILLARD]

On 15:40 Fri 27 Jul     , Jan Weitzel wrote:
> Change clock init to allow early gpio access. Add support for 4460 clocks.
> 
> Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
> ---
>  arch/arm/boards/panda/lowlevel.c              |    4 ++-
>  arch/arm/boards/panda/mux.c                   |    8 +++++
>  arch/arm/boards/pcm049/lowlevel.c             |   15 +++++++--
>  arch/arm/boards/pcm049/mux.c                  |    8 +++++
>  arch/arm/boards/phycard-a-xl2/lowlevel.c      |    9 ++++-
>  arch/arm/boards/phycard-a-xl2/mux.c           |    8 +++++
>  arch/arm/mach-omap/include/mach/omap4-clock.h |    4 ++
>  arch/arm/mach-omap/omap4_clock.c              |   39 +++++++++++++++++-------
>  8 files changed, 76 insertions(+), 19 deletions(-)
> 
> diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c
> index 8591fff..0b4b199 100644
> --- a/arch/arm/boards/panda/lowlevel.c
> +++ b/arch/arm/boards/panda/lowlevel.c
> @@ -28,6 +28,8 @@
>  #include <mach/syslib.h>
>  #include <asm/barebox-arm.h>
>  
> +#define TPS62361_VSEL0_GPIO    7
> +
>  void set_muxconf_regs(void);
>  
>  static const struct ddr_regs ddr_regs_400_mhz_2cs = {
> @@ -70,7 +72,7 @@ static void noinline panda_init_lowlevel(void)
>  	omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core);
>  
>  	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
> -	omap4_scale_vcores();
> +	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
>  
>  	board_init_lowlevel_return();
>  }
> diff --git a/arch/arm/boards/panda/mux.c b/arch/arm/boards/panda/mux.c
> index 310e433..3783006 100644
> --- a/arch/arm/boards/panda/mux.c
> +++ b/arch/arm/boards/panda/mux.c
> @@ -3,6 +3,7 @@
>  #include <io.h>
>  #include <mach/omap4-silicon.h>
>  #include <mach/omap4-mux.h>
> +#include <mach/omap4-clock.h>
>  
>  static const struct pad_conf_entry core_padconf_array[] = {
>  	{ GPMC_AD0, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat0 */ },
> @@ -245,4 +246,11 @@ void set_muxconf_regs(void)
>  
>  	omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array,
>  			ARRAY_SIZE(wkup_padconf_array));
> +
> +	/* gpio_wk7 is used for controlling TPS on 4460 */
> +	if (omap4_revision() >= OMAP4460_ES1_0) {
> +		writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + PAD1_FREF_CLK4_REQ);
> +		/* Enable GPIO-1 clocks before TPS initialization */
> +		omap4_enable_gpio1_wup_clocks();
> +	}
can we factorize this?

Best Regards,
J.

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Re: [PATCH 3/3] OMAP4460: clock init

[Jan Weitzel]

Am Freitag, den 27.07.2012, 16:18 +0200 schrieb Jean-Christophe
PLAGNIOL-VILLARD:
> On 15:40 Fri 27 Jul     , Jan Weitzel wrote:
> > Change clock init to allow early gpio access. Add support for 4460 clocks.
> > 
> > Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
> > ---
> >  arch/arm/boards/panda/lowlevel.c              |    4 ++-
> >  arch/arm/boards/panda/mux.c                   |    8 +++++
> >  arch/arm/boards/pcm049/lowlevel.c             |   15 +++++++--
> >  arch/arm/boards/pcm049/mux.c                  |    8 +++++
> >  arch/arm/boards/phycard-a-xl2/lowlevel.c      |    9 ++++-
> >  arch/arm/boards/phycard-a-xl2/mux.c           |    8 +++++
> >  arch/arm/mach-omap/include/mach/omap4-clock.h |    4 ++
> >  arch/arm/mach-omap/omap4_clock.c              |   39 +++++++++++++++++-------
> >  8 files changed, 76 insertions(+), 19 deletions(-)
> > 
> > diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c
> > index 8591fff..0b4b199 100644
> > --- a/arch/arm/boards/panda/lowlevel.c
> > +++ b/arch/arm/boards/panda/lowlevel.c
> > @@ -28,6 +28,8 @@
> >  #include <mach/syslib.h>
> >  #include <asm/barebox-arm.h>
> >  
> > +#define TPS62361_VSEL0_GPIO    7
> > +
> >  void set_muxconf_regs(void);
> >  
> >  static const struct ddr_regs ddr_regs_400_mhz_2cs = {
> > @@ -70,7 +72,7 @@ static void noinline panda_init_lowlevel(void)
> >  	omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core);
> >  
> >  	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
> > -	omap4_scale_vcores();
> > +	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
> >  
> >  	board_init_lowlevel_return();
> >  }
> > diff --git a/arch/arm/boards/panda/mux.c b/arch/arm/boards/panda/mux.c
> > index 310e433..3783006 100644
> > --- a/arch/arm/boards/panda/mux.c
> > +++ b/arch/arm/boards/panda/mux.c
> > @@ -3,6 +3,7 @@
> >  #include <io.h>
> >  #include <mach/omap4-silicon.h>
> >  #include <mach/omap4-mux.h>
> > +#include <mach/omap4-clock.h>
> >  
> >  static const struct pad_conf_entry core_padconf_array[] = {
> >  	{ GPMC_AD0, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat0 */ },
> > @@ -245,4 +246,11 @@ void set_muxconf_regs(void)
> >  
> >  	omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array,
> >  			ARRAY_SIZE(wkup_padconf_array));
> > +
> > +	/* gpio_wk7 is used for controlling TPS on 4460 */
> > +	if (omap4_revision() >= OMAP4460_ES1_0) {
> > +		writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + PAD1_FREF_CLK4_REQ);
> > +		/* Enable GPIO-1 clocks before TPS initialization */
> > +		omap4_enable_gpio1_wup_clocks();
> > +	}
> can we factorize this?
Sorry, I didn't catch this.
Jan
> Best Regards,
> J.



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[PATCH 0/3 v2] omap: 4460 support

[Jan Weitzel]

Add support for OMAP4460 cpu
on top of ed358834 (next)

v2: merge usage of omap4_scale_vcores to 1/3
    avoid volatile int*


Jan Weitzel (3):
  Add support for OMAP4460 TPS62361
  OMAP4460: ram init changes
  OMAP4460: clock init

 arch/arm/boards/panda/lowlevel.c                |    4 +-
 arch/arm/boards/panda/mux.c                     |    8 +++
 arch/arm/boards/pcm049/lowlevel.c               |   15 ++++--
 arch/arm/boards/pcm049/mux.c                    |    8 +++
 arch/arm/boards/phycard-a-xl2/lowlevel.c        |   13 ++++-
 arch/arm/boards/phycard-a-xl2/mux.c             |    8 +++
 arch/arm/mach-omap/include/mach/omap4-clock.h   |   19 +++++++
 arch/arm/mach-omap/include/mach/omap4-silicon.h |   13 +++++-
 arch/arm/mach-omap/omap4_clock.c                |   58 +++++++++++++++++-----
 arch/arm/mach-omap/omap4_generic.c              |   60 +++++++++++++++++++++--
 10 files changed, 181 insertions(+), 25 deletions(-)


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[PATCH 2/3] OMAP4460: ram init changes

[Jan Weitzel]

configure  Memory Adapter for 4460

Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
---
 arch/arm/mach-omap/include/mach/omap4-silicon.h |    4 ++++
 arch/arm/mach-omap/omap4_generic.c              |   21 +++++++++++++++++++--
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
index d5517c5..4082bac 100644
--- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
+++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
@@ -101,6 +101,10 @@
 #define DMM_LISA_MAP_SYS_SIZE_MASK	(7 << 20)
 #define DMM_LISA_MAP_SYS_SIZE_SHIFT	20
 #define DMM_LISA_MAP_SYS_ADDR_MASK	(0xFF << 24)
+
+/* Memory Adapter (4460 onwards) */
+#define OMAP44XX_MA_BASE		0x482AF000
+
 /*
  * Hardware Register Details
  */
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index 3f6865a..617d786 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -29,6 +29,10 @@
 #define OMAP4460_CONTROL_ID_CODE_ES1_0  0x0B94E02F
 #define OMAP4460_CONTROL_ID_CODE_ES1_1  0x2B94E02F
 
+/* EMIF_L3_CONFIG register value */
+#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0		0x0A0000FF
+#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0	0x0A300000
+
 void __noreturn reset_cpu(unsigned long addr)
 {
 	writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
@@ -272,8 +276,7 @@ static void reset_phy(unsigned int base)
 void omap4_ddr_init(const struct ddr_regs *ddr_regs,
 		const struct dpll_param *core)
 {
-	unsigned int rev;
-	rev = omap4_revision();
+	unsigned int rev = omap4_revision();
 
 	if (rev == OMAP4430_ES2_0) {
 		writel(0x9e9e9e9e, 0x4A100638);
@@ -296,6 +299,13 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
 	writel(0x00000000, OMAP44XX_DMM_BASE + DMM_LISA_MAP_2);
 	writel(0xFF020100, OMAP44XX_DMM_BASE + DMM_LISA_MAP_3);
 
+	if (rev >= OMAP4460_ES1_0) {
+		writel(0x80640300, OMAP44XX_MA_BASE + DMM_LISA_MAP_0);
+
+		writel(0x00000000, OMAP44XX_MA_BASE + DMM_LISA_MAP_2);
+		writel(0xFF020100, OMAP44XX_MA_BASE + DMM_LISA_MAP_3);
+	}
+
 	/* DDR needs to be initialised @ 19.2 MHz
 	 * So put core DPLL in bypass mode
 	 * Configure the Core DPLL but don't lock it
@@ -338,6 +348,13 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
 	writel(0x80000000, OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
 	writel(0x80000000, OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
 
+	if (rev >= OMAP4460_ES1_0) {
+		writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
+				OMAP44XX_EMIF1_BASE + EMIF_L3_CONFIG);
+		writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
+				OMAP44XX_EMIF2_BASE + EMIF_L3_CONFIG);
+	}
+
 	/*
 	 * DMM : DMM_LISA_MAP_0(Section_0)
 	 * [31:24] SYS_ADDR 		0x80
-- 
1.7.0.4


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