* [RFC 0/3] MIPS: add pre-bootloader (pbl) image support
@ 2012-11-17 12:10 Antony Pavlov
2012-11-17 12:10 ` [RFC 1/3] " Antony Pavlov
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Antony Pavlov @ 2012-11-17 12:10 UTC (permalink / raw)
To: barebox
This patch series is based on ARM pbl support and allows
creating a pre-bootloader binary for compressed image.
TODO:
* add lowlevel init;
* current MIPS pbl run only on qemu-malta; make it work
on other boards (e.g. add mmc/nand boot support on Ingenic SOCs).
[RFC 1/3] MIPS: add pre-bootloader (pbl) image support
[RFC 2/3] MIPS: boot: realize _start in C
[RFC 3/3] MIPS: qemu-malta_defconfig: use pbl
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [RFC 1/3] MIPS: add pre-bootloader (pbl) image support
2012-11-17 12:10 [RFC 0/3] MIPS: add pre-bootloader (pbl) image support Antony Pavlov
@ 2012-11-17 12:10 ` Antony Pavlov
2012-11-20 7:59 ` Sascha Hauer
2012-11-17 12:10 ` [RFC 2/3] MIPS: boot: realize _start in C Antony Pavlov
2012-11-17 12:10 ` [RFC 3/3] MIPS: qemu-malta_defconfig: use pbl Antony Pavlov
2 siblings, 1 reply; 9+ messages in thread
From: Antony Pavlov @ 2012-11-17 12:10 UTC (permalink / raw)
To: barebox
This patch is based on ARM pbl support and allows
creating a pre-bootloader binary for compressed image.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/Kconfig | 2 +
arch/mips/Makefile | 18 +++++
arch/mips/boot/Makefile | 2 +
arch/mips/boot/main_entry-pbl.c | 90 ++++++++++++++++++++++++
arch/mips/boot/start-pbl.S | 146 +++++++++++++++++++++++++++++++++++++++
arch/mips/pbl/.gitignore | 6 ++
arch/mips/pbl/Makefile | 40 +++++++++++
arch/mips/pbl/piggy.gzip.S | 6 ++
arch/mips/pbl/piggy.lzo.S | 6 ++
arch/mips/pbl/zbarebox.lds.S | 57 +++++++++++++++
10 files changed, 373 insertions(+)
create mode 100644 arch/mips/boot/main_entry-pbl.c
create mode 100644 arch/mips/boot/start-pbl.S
create mode 100644 arch/mips/pbl/.gitignore
create mode 100644 arch/mips/pbl/Makefile
create mode 100644 arch/mips/pbl/piggy.gzip.S
create mode 100644 arch/mips/pbl/piggy.lzo.S
create mode 100644 arch/mips/pbl/zbarebox.lds.S
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 7a1eeac..853d406 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -6,6 +6,8 @@ config MIPS
select HAS_KALLSYMS
select HAVE_CONFIGURABLE_MEMORY_LAYOUT
select HAVE_CONFIGURABLE_TEXT_BASE
+ select HAVE_PBL_IMAGE
+ select HAVE_IMAGE_COMPRESSION
default y
config SYS_SUPPORTS_BIG_ENDIAN
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 5e40de7..819e7a3 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -58,6 +58,15 @@ CPPFLAGS += -fdata-sections -ffunction-sections
LDFLAGS_barebox += -static --gc-sections
endif
+ifdef CONFIG_IMAGE_COMPRESSION
+KBUILD_BINARY := arch/mips/pbl/zbarebox.bin
+KBUILD_TARGET := zbarebox.bin
+$(KBUILD_BINARY): $(KBUILD_TARGET)
+else
+KBUILD_BINARY := barebox.bin
+KBUILD_TARGET := barebox.bin
+endif
+
LDFLAGS_barebox += -nostdlib
machine-$(CONFIG_MACH_MIPS_MALTA) := malta
@@ -106,3 +115,12 @@ CFLAGS += $(cflags-y)
lds-$(CONFIG_GENERIC_LINKER_SCRIPT) := arch/mips/lib/barebox.lds
CLEAN_FILES += arch/mips/lib/barebox.lds barebox.map barebox.S
+
+pbl := arch/mips/pbl
+zbarebox.S zbarebox.bin zbarebox: barebox.bin
+ $(Q)$(MAKE) $(build)=$(pbl) $(pbl)/$@
+
+archclean:
+ $(MAKE) $(clean)=$(pbl)
+
+KBUILD_IMAGE ?= $(KBUILD_BINARY)
diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
index d6d28ce..6b093f1 100644
--- a/arch/mips/boot/Makefile
+++ b/arch/mips/boot/Makefile
@@ -1,2 +1,4 @@
obj-y += start.o
obj-y += main_entry.o
+
+pbl-y += start-pbl.o main_entry-pbl.o
diff --git a/arch/mips/boot/main_entry-pbl.c b/arch/mips/boot/main_entry-pbl.c
new file mode 100644
index 0000000..51b9176
--- /dev/null
+++ b/arch/mips/boot/main_entry-pbl.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2012 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <sizes.h>
+#include <string.h>
+#include <asm/sections.h>
+#include <asm-generic/memory_layout.h>
+#include <debug_ll.h>
+
+extern void *input_data;
+extern void *input_data_end;
+
+unsigned long free_mem_ptr;
+unsigned long free_mem_end_ptr;
+
+#define STATIC static
+
+#ifdef CONFIG_IMAGE_COMPRESSION_LZO
+#include "../../../lib/decompress_unlzo.c"
+#endif
+
+#ifdef CONFIG_IMAGE_COMPRESSION_GZIP
+#include "../../../lib/decompress_inflate.c"
+#endif
+
+void pbl_main_entry(void);
+
+static unsigned long *ttb;
+
+static noinline void errorfn(char *error)
+{
+ PUTS_LL(error);
+ PUTC_LL('\n');
+
+ unreachable();
+}
+
+static void barebox_uncompress(void *compressed_start, unsigned int len)
+{
+ /* set 128 KiB at the end of the MALLOC_BASE for early malloc */
+ free_mem_ptr = MALLOC_BASE + MALLOC_SIZE - SZ_128K;
+ free_mem_end_ptr = free_mem_ptr + SZ_128K;
+
+ ttb = (void *)((free_mem_ptr - 0x4000) & ~0x3fff);
+
+ decompress((void *)compressed_start,
+ len,
+ NULL, NULL,
+ (void *)TEXT_BASE, NULL, errorfn);
+
+ /* FIXME: just now we have no MIPS cache support */
+ /* flush_icache(); */
+}
+
+void __section(.text_entry) pbl_main_entry(void)
+{
+ u32 pg_start, pg_end, pg_len;
+ void (*barebox)(void);
+
+ PUTS_LL("pbl_main_entry()\n");
+
+ /* clear bss */
+ memset(__bss_start, 0, __bss_stop - __bss_start);
+
+ pg_start = (u32)&input_data;
+ pg_end = (u32)&input_data_end;
+ pg_len = pg_end - pg_start;
+
+ barebox_uncompress(&input_data, pg_len);
+
+ barebox = (void *)TEXT_BASE;
+ barebox();
+}
diff --git a/arch/mips/boot/start-pbl.S b/arch/mips/boot/start-pbl.S
new file mode 100644
index 0000000..ad39f42
--- /dev/null
+++ b/arch/mips/boot/start-pbl.S
@@ -0,0 +1,146 @@
+/*
+ * Startup Code for MIPS CPU
+ *
+ * Copyright (C) 2011, 2012 Antony Pavlov <antonynpavlov@gmail.com>
+ * ADR macro copyrighted (C) 2009 by Shinya Kuribayashi <skuribay@pobox.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/asm.h>
+#include <asm-generic/memory_layout.h>
+#include <generated/compile.h>
+#include <generated/utsrelease.h>
+
+//#include <mach/kernel-entry-init.h>
+
+ /*
+ * ADR macro instruction (inspired by ARM)
+ *
+ * ARM architecture doesn't have PC-relative jump instruction
+ * like MIPS' B/BAL insns. When ARM makes PC-relative jumps,
+ * it uses ADR insn. ADR is used to get a destination address
+ * of 'label' against current PC. With this, ARM can safely
+ * make PC-relative jumps.
+ */
+ .macro ADR rd label temp
+ .set push
+ .set noreorder
+ move \temp, ra # preserve ra beforehand
+ bal _pc
+ nop
+_pc: addiu \rd, ra, \label - _pc # label is assumed to be
+ move ra, \temp # within pc +/- 32KB
+ .set pop
+ .endm
+
+ .set noreorder
+ .text
+ .section ".text_head_entry"
+ .align 4
+
+EXPORT(pbl_start)
+
+ b __start
+ nop
+
+ .org 0x10
+ .ascii "barebox " UTS_RELEASE " " UTS_VERSION
+ .byte 0
+
+ .align 4
+__start:
+ /* disable watchpoints */
+ mtc0 zero, CP0_WATCHLO
+ mtc0 zero, CP0_WATCHHI
+
+ /* disable interrupts */
+ mfc0 k0, CP0_STATUS
+ li k1, ~ST0_IE
+ and k0, k1
+ mtc0 k0, CP0_STATUS
+
+ /* cpu specific setup */
+ //kernel_entry_setup
+
+ /* copy barebox to link location */
+ ADR a0, pbl_start, t1 /* a0 <- pc-relative
+ position of pbl_start */
+
+ la a1, pbl_start /* a1 <- link (RAM) pbl_start address */
+
+ beq a0, a1, stack_setup
+ nop
+
+ la t0, pbl_start
+ la t1, __bss_start
+ subu t2, t1, t0 /* t2 <- size of pbl */
+ addu a2, a0, t2 /* a2 <- source end address */
+
+#define LONGSIZE 4
+
+copy_loop:
+ /* copy from source address [a0] */
+ lw t4, LONGSIZE * 0(a0)
+ lw t5, LONGSIZE * 1(a0)
+ lw t6, LONGSIZE * 2(a0)
+ lw t7, LONGSIZE * 3(a0)
+ /* copy fo target address [a1] */
+ sw t4, LONGSIZE * 0(a1)
+ sw t5, LONGSIZE * 1(a1)
+ sw t6, LONGSIZE * 2(a1)
+ sw t7, LONGSIZE * 3(a1)
+ addi a0, LONGSIZE * 4
+ subu t3, a0, a2
+ blez t3, copy_loop
+ addi a1, LONGSIZE * 4
+
+ /*
+ * Dominic Sweetman, See MIPS Run, Morgan Kaufmann, 2nd edition, 2006
+ *
+ * 11.2.2 Stack Argument Structure in o32
+ * ...
+ * At the point where a function is called, sp must be
+ * eight-byte-aligned, matching the alignment of the largest
+ * basic types -- a long long integer or a floating-point double.
+ * The eight-byte alignment is not required by 32-bit MIPS integer
+ * hardware, but it's essential for compatibility with CPUs with
+ * 64-bit registers, and thus part of the rules. Subroutines fit
+ * in with this by always adjusting the stack pointer by a multiple
+ * of eight.
+ * ...
+ * SGI's n32 and n64 standards call for the stack to be maintained
+ * with 16-byte alignment.
+ *
+ */
+
+#if (STACK_BASE + STACK_SIZE) % 16 != 0
+#error stack pointer must be 16-byte-aligned
+#endif
+
+stack_setup:
+
+ /* set stack pointer; reserve four 32-bit argument slots */
+ la sp, STACK_BASE + STACK_SIZE - 16
+
+ la v0, pbl_main_entry
+ jal v0
+ nop
+
+ /* No return */
+__error:
+ b __error
+ nop
diff --git a/arch/mips/pbl/.gitignore b/arch/mips/pbl/.gitignore
new file mode 100644
index 0000000..d71bb7c
--- /dev/null
+++ b/arch/mips/pbl/.gitignore
@@ -0,0 +1,6 @@
+piggy.gzip
+piggy.lzo
+zbarebox
+zbarebox.bin
+zbarebox.lds
+zbarebox.map
diff --git a/arch/mips/pbl/Makefile b/arch/mips/pbl/Makefile
new file mode 100644
index 0000000..7faa51a
--- /dev/null
+++ b/arch/mips/pbl/Makefile
@@ -0,0 +1,40 @@
+
+suffix_$(CONFIG_IMAGE_COMPRESSION_GZIP) = gzip
+suffix_$(CONFIG_IMAGE_COMPRESSION_LZO) = lzo
+
+OBJCOPYFLAGS_zbarebox.bin = -O binary
+piggy_o := piggy.$(suffix_y).o
+
+targets := zbarebox.lds zbarebox zbarebox.bin zbarebox.S \
+ $(piggy_o) piggy.$(suffix_y)
+
+# Make sure files are removed during clean
+extra-y += piggy.gzip piggy.lzo piggy.lzma piggy.xzkern zbarebox.map
+
+$(obj)/zbarebox.bin: $(obj)/zbarebox FORCE
+ $(call if_changed,objcopy)
+ $(call cmd,check_file_size,$(CONFIG_BAREBOX_MAX_IMAGE_SIZE))
+ $(Q)$(kecho) ' Barebox: $@ is ready'
+
+$(obj)/zbarebox.S: $(obj)/zbarebox FORCE
+ $(call if_changed,disasm)
+
+PBL_CPPFLAGS += -fdata-sections -ffunction-sections
+LDFLAGS_zbarebox := -Map $(obj)/zbarebox.map
+LDFLAGS_zbarebox += -static --gc-sections
+zbarebox-common := $(barebox-pbl-common) $(obj)/$(piggy_o)
+zbarebox-lds := $(obj)/zbarebox.lds
+
+quiet_cmd_zbarebox__ ?= LD $@
+ cmd_zbarebox__ ?= $(LD) $(LDFLAGS) $(LDFLAGS_zbarebox) -o $@ \
+ -T $(zbarebox-lds) \
+ --start-group $(zbarebox-common) --end-group \
+ $(filter-out $(zbarebox-lds) $(zbarebox-common) FORCE ,$^)
+
+$(obj)/zbarebox: $(zbarebox-lds) $(zbarebox-common) FORCE
+ $(call if_changed,zbarebox__)
+
+$(obj)/piggy.$(suffix_y): $(obj)/../../../barebox.bin FORCE
+ $(call if_changed,$(suffix_y))
+
+$(obj)/$(piggy_o): $(obj)/piggy.$(suffix_y) FORCE
diff --git a/arch/mips/pbl/piggy.gzip.S b/arch/mips/pbl/piggy.gzip.S
new file mode 100644
index 0000000..1e6bbef
--- /dev/null
+++ b/arch/mips/pbl/piggy.gzip.S
@@ -0,0 +1,6 @@
+#include <asm/asm.h>
+
+ .section .data
+EXPORT(input_data)
+ .incbin "arch/mips/pbl/piggy.gzip"
+EXPORT(input_data_end)
diff --git a/arch/mips/pbl/piggy.lzo.S b/arch/mips/pbl/piggy.lzo.S
new file mode 100644
index 0000000..6f1af1f
--- /dev/null
+++ b/arch/mips/pbl/piggy.lzo.S
@@ -0,0 +1,6 @@
+#include <asm/asm.h>
+
+ .section .data
+EXPORT(input_data)
+ .incbin "arch/mips/pbl/piggy.lzo"
+EXPORT(input_data_end)
diff --git a/arch/mips/pbl/zbarebox.lds.S b/arch/mips/pbl/zbarebox.lds.S
new file mode 100644
index 0000000..3a26942
--- /dev/null
+++ b/arch/mips/pbl/zbarebox.lds.S
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm-generic/barebox.lds.h>
+#include <asm-generic/memory_layout.h>
+
+OUTPUT_ARCH("mips")
+ENTRY(pbl_start)
+SECTIONS
+{
+ . = HEAD_TEXT_BASE;
+
+ PRE_IMAGE
+
+ . = ALIGN(4);
+ .text :
+ {
+ _stext = .;
+ _text = .;
+ *(.text_head_entry*)
+ __bare_init_start = .;
+ *(.text_bare_init*)
+ __bare_init_end = .;
+ *(.text*)
+ }
+
+ BAREBOX_BARE_INIT_SIZE
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata*) }
+
+ _etext = .; /* End of text and rodata section */
+
+ . = ALIGN(4);
+ .data : { *(.data*) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss*) }
+ __bss_stop = .;
+ _end = .;
+}
--
1.7.10.4
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [RFC 2/3] MIPS: boot: realize _start in C
2012-11-17 12:10 [RFC 0/3] MIPS: add pre-bootloader (pbl) image support Antony Pavlov
2012-11-17 12:10 ` [RFC 1/3] " Antony Pavlov
@ 2012-11-17 12:10 ` Antony Pavlov
2012-11-20 7:58 ` Sascha Hauer
2012-11-17 12:10 ` [RFC 3/3] MIPS: qemu-malta_defconfig: use pbl Antony Pavlov
2 siblings, 1 reply; 9+ messages in thread
From: Antony Pavlov @ 2012-11-17 12:10 UTC (permalink / raw)
To: barebox
The pbl will be incharge of the lowlevel init and
barebox relocation. So we can skip it in barebox itself
and use simple _start.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/boot/Makefile | 1 -
arch/mips/boot/main_entry.c | 18 ++++++
arch/mips/boot/start.S | 142 -------------------------------------------
3 files changed, 18 insertions(+), 143 deletions(-)
delete mode 100644 arch/mips/boot/start.S
diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
index 6b093f1..4f11a48 100644
--- a/arch/mips/boot/Makefile
+++ b/arch/mips/boot/Makefile
@@ -1,4 +1,3 @@
-obj-y += start.o
obj-y += main_entry.o
pbl-y += start-pbl.o main_entry-pbl.o
diff --git a/arch/mips/boot/main_entry.c b/arch/mips/boot/main_entry.c
index 0a33c45..422d40b 100644
--- a/arch/mips/boot/main_entry.c
+++ b/arch/mips/boot/main_entry.c
@@ -22,6 +22,8 @@
#include <asm/cpu-features.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
+#include <asm/regdef.h>
+#include <asm-generic/memory_layout.h>
extern void start_barebox(void);
extern void handle_reserved(void);
@@ -92,3 +94,19 @@ void main_entry(void)
start_barebox();
}
+
+void __naked __section(.text_entry) _start(void)
+{
+ u32 r;
+
+ /* setup the stack */
+ r = STACK_BASE + STACK_SIZE - 16;
+
+ __asm__ __volatile__(
+ "move\t$sp, %0\n\t"
+ : /* no outputs */
+ : "r" (r)
+ );
+
+ main_entry();
+}
diff --git a/arch/mips/boot/start.S b/arch/mips/boot/start.S
deleted file mode 100644
index 7e2ae5e..0000000
--- a/arch/mips/boot/start.S
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Startup Code for MIPS CPU
- *
- * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
- * Used code copyrighted (C) 2009 by Shinya Kuribayashi <skuribay@pobox.com>
- *
- * This file is part of barebox.
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-#include <asm/asm.h>
-#include <asm-generic/memory_layout.h>
-#include <generated/compile.h>
-#include <generated/utsrelease.h>
-
- /*
- * ADR macro instruction (inspired by ARM)
- *
- * ARM architecture doesn't have PC-relative jump instruction
- * like MIPS' B/BAL insns. When ARM makes PC-relative jumps,
- * it uses ADR insn. ADR is used to get a destination address
- * of 'label' against current PC. With this, ARM can safely
- * make PC-relative jumps.
- */
- .macro ADR rd label temp
- .set push
- .set noreorder
- move \temp, ra # preserve ra beforehand
- bal _pc
- nop
-_pc: addiu \rd, ra, \label - _pc # label is assumed to be
- move ra, \temp # within pc +/- 32KB
- .set pop
- .endm
-
- .set noreorder
- .text
- .section ".text_bare_init"
- .align 4
-
-EXPORT(_start)
-
- b __start
- nop
-
- .org 0x10
- .ascii "barebox " UTS_RELEASE " " UTS_VERSION
- .byte 0
-
- .align 4
-__start:
- /* disable watchpoints */
- mtc0 zero, CP0_WATCHLO
- mtc0 zero, CP0_WATCHHI
-
- /* disable interrupts */
- mfc0 k0, CP0_STATUS
- li k1, ~ST0_IE
- and k0, k1
- mtc0 k0, CP0_STATUS
-
- /* copy barebox to link location */
- ADR a0, _start, t1 /* a0 <- pc-relative position of _start */
-
- la a1, _start /* link (RAM) _start address */
-
- beq a0, a1, stack_setup
- nop
-
- la t0, _start
- la t1, __bss_start
- subu t2, t1, t0 /* t2 <- size of barebox */
- addu a2, a0, t2 /* a2 <- source end address */
-
-#define LONGSIZE 4
-
-copy_loop:
- /* copy from source address [a0] */
- lw t4, LONGSIZE * 0(a0)
- lw t5, LONGSIZE * 1(a0)
- lw t6, LONGSIZE * 2(a0)
- lw t7, LONGSIZE * 3(a0)
- /* copy fo target address [a1] */
- sw t4, LONGSIZE * 0(a1)
- sw t5, LONGSIZE * 1(a1)
- sw t6, LONGSIZE * 2(a1)
- sw t7, LONGSIZE * 3(a1)
- addi a0, LONGSIZE * 4
- subu t3, a0, a2
- blez t3, copy_loop
- addi a1, LONGSIZE * 4
-
- /*
- * Dominic Sweetman, See MIPS Run, Morgan Kaufmann, 2nd edition, 2006
- *
- * 11.2.2 Stack Argument Structure in o32
- * ...
- * At the point where a function is called, sp must be
- * eight-byte-aligned, matching the alignment of the largest
- * basic types -- a long long integer or a floating-point double.
- * The eight-byte alignment is not required by 32-bit MIPS integer
- * hardware, but it's essential for compatibility with CPUs with
- * 64-bit registers, and thus part of the rules. Subroutines fit
- * in with this by always adjusting the stack pointer by a multiple
- * of eight.
- * ...
- * SGI's n32 and n64 standards call for the stack to be maintained
- * with 16-byte alignment.
- *
- */
-
-#if (STACK_BASE + STACK_SIZE) % 16 != 0
-#error stack pointer must be 16-byte-aligned
-#endif
-
-stack_setup:
- la sp, STACK_BASE + STACK_SIZE
-
- /* reserve four 32-bit argument slots */
- addiu sp, -16
-
- la v0, main_entry
- jal v0
- nop
-
- /* No return */
-
-__error:
- b __error
- nop
--
1.7.10.4
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [RFC 3/3] MIPS: qemu-malta_defconfig: use pbl
2012-11-17 12:10 [RFC 0/3] MIPS: add pre-bootloader (pbl) image support Antony Pavlov
2012-11-17 12:10 ` [RFC 1/3] " Antony Pavlov
2012-11-17 12:10 ` [RFC 2/3] MIPS: boot: realize _start in C Antony Pavlov
@ 2012-11-17 12:10 ` Antony Pavlov
2 siblings, 0 replies; 9+ messages in thread
From: Antony Pavlov @ 2012-11-17 12:10 UTC (permalink / raw)
To: barebox
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
arch/mips/configs/qemu-malta_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/configs/qemu-malta_defconfig b/arch/mips/configs/qemu-malta_defconfig
index 7ade1aa..7dab969 100644
--- a/arch/mips/configs/qemu-malta_defconfig
+++ b/arch/mips/configs/qemu-malta_defconfig
@@ -1,3 +1,4 @@
+CONFIG_PBL_IMAGE=y
CONFIG_STACK_SIZE=0x7000
CONFIG_BROKEN=y
CONFIG_EXPERIMENTAL=y
--
1.7.10.4
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC 2/3] MIPS: boot: realize _start in C
2012-11-17 12:10 ` [RFC 2/3] MIPS: boot: realize _start in C Antony Pavlov
@ 2012-11-20 7:58 ` Sascha Hauer
2012-11-24 16:18 ` Antony Pavlov
0 siblings, 1 reply; 9+ messages in thread
From: Sascha Hauer @ 2012-11-20 7:58 UTC (permalink / raw)
To: Antony Pavlov; +Cc: barebox
On Sat, Nov 17, 2012 at 04:10:38PM +0400, Antony Pavlov wrote:
> The pbl will be incharge of the lowlevel init and
> barebox relocation. So we can skip it in barebox itself
> and use simple _start.
>
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> ---
> arch/mips/boot/Makefile | 1 -
> arch/mips/boot/main_entry.c | 18 ++++++
> arch/mips/boot/start.S | 142 -------------------------------------------
> 3 files changed, 18 insertions(+), 143 deletions(-)
> delete mode 100644 arch/mips/boot/start.S
>
> diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
> index 6b093f1..4f11a48 100644
> --- a/arch/mips/boot/Makefile
> +++ b/arch/mips/boot/Makefile
> @@ -1,4 +1,3 @@
> -obj-y += start.o
> obj-y += main_entry.o
>
> pbl-y += start-pbl.o main_entry-pbl.o
> diff --git a/arch/mips/boot/main_entry.c b/arch/mips/boot/main_entry.c
> index 0a33c45..422d40b 100644
> --- a/arch/mips/boot/main_entry.c
> +++ b/arch/mips/boot/main_entry.c
> @@ -22,6 +22,8 @@
> #include <asm/cpu-features.h>
> #include <asm/mipsregs.h>
> #include <asm/addrspace.h>
> +#include <asm/regdef.h>
> +#include <asm-generic/memory_layout.h>
>
> extern void start_barebox(void);
> extern void handle_reserved(void);
> @@ -92,3 +94,19 @@ void main_entry(void)
>
> start_barebox();
> }
> +
> +void __naked __section(.text_entry) _start(void)
> +{
> + u32 r;
> +
> + /* setup the stack */
> + r = STACK_BASE + STACK_SIZE - 16;
> +
> + __asm__ __volatile__(
> + "move\t$sp, %0\n\t"
> + : /* no outputs */
> + : "r" (r)
> + );
> +
> + main_entry();
I wonder that the C function skips several things the Assembler version
does. Is this done in the pbl now? Does this patch make the pbl
mandatory? We haven't done this on Arm, mostly because we were not
confident enough that it works on every board. That may be different on
mips, but should be mentioned in the commit log. But maybe I am
misreading the patches...
Sascha
> +}
> diff --git a/arch/mips/boot/start.S b/arch/mips/boot/start.S
> deleted file mode 100644
> index 7e2ae5e..0000000
> --- a/arch/mips/boot/start.S
> +++ /dev/null
> @@ -1,142 +0,0 @@
> -/*
> - * Startup Code for MIPS CPU
> - *
> - * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
> - * Used code copyrighted (C) 2009 by Shinya Kuribayashi <skuribay@pobox.com>
> - *
> - * This file is part of barebox.
> - * See file CREDITS for list of people who contributed to this project.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2
> - * as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - */
> -
> -#include <asm/regdef.h>
> -#include <asm/mipsregs.h>
> -#include <asm/asm.h>
> -#include <asm-generic/memory_layout.h>
> -#include <generated/compile.h>
> -#include <generated/utsrelease.h>
> -
> - /*
> - * ADR macro instruction (inspired by ARM)
> - *
> - * ARM architecture doesn't have PC-relative jump instruction
> - * like MIPS' B/BAL insns. When ARM makes PC-relative jumps,
> - * it uses ADR insn. ADR is used to get a destination address
> - * of 'label' against current PC. With this, ARM can safely
> - * make PC-relative jumps.
> - */
> - .macro ADR rd label temp
> - .set push
> - .set noreorder
> - move \temp, ra # preserve ra beforehand
> - bal _pc
> - nop
> -_pc: addiu \rd, ra, \label - _pc # label is assumed to be
> - move ra, \temp # within pc +/- 32KB
> - .set pop
> - .endm
> -
> - .set noreorder
> - .text
> - .section ".text_bare_init"
> - .align 4
> -
> -EXPORT(_start)
> -
> - b __start
> - nop
> -
> - .org 0x10
> - .ascii "barebox " UTS_RELEASE " " UTS_VERSION
> - .byte 0
> -
> - .align 4
> -__start:
> - /* disable watchpoints */
> - mtc0 zero, CP0_WATCHLO
> - mtc0 zero, CP0_WATCHHI
> -
> - /* disable interrupts */
> - mfc0 k0, CP0_STATUS
> - li k1, ~ST0_IE
> - and k0, k1
> - mtc0 k0, CP0_STATUS
> -
> - /* copy barebox to link location */
> - ADR a0, _start, t1 /* a0 <- pc-relative position of _start */
> -
> - la a1, _start /* link (RAM) _start address */
> -
> - beq a0, a1, stack_setup
> - nop
> -
> - la t0, _start
> - la t1, __bss_start
> - subu t2, t1, t0 /* t2 <- size of barebox */
> - addu a2, a0, t2 /* a2 <- source end address */
> -
> -#define LONGSIZE 4
> -
> -copy_loop:
> - /* copy from source address [a0] */
> - lw t4, LONGSIZE * 0(a0)
> - lw t5, LONGSIZE * 1(a0)
> - lw t6, LONGSIZE * 2(a0)
> - lw t7, LONGSIZE * 3(a0)
> - /* copy fo target address [a1] */
> - sw t4, LONGSIZE * 0(a1)
> - sw t5, LONGSIZE * 1(a1)
> - sw t6, LONGSIZE * 2(a1)
> - sw t7, LONGSIZE * 3(a1)
> - addi a0, LONGSIZE * 4
> - subu t3, a0, a2
> - blez t3, copy_loop
> - addi a1, LONGSIZE * 4
> -
> - /*
> - * Dominic Sweetman, See MIPS Run, Morgan Kaufmann, 2nd edition, 2006
> - *
> - * 11.2.2 Stack Argument Structure in o32
> - * ...
> - * At the point where a function is called, sp must be
> - * eight-byte-aligned, matching the alignment of the largest
> - * basic types -- a long long integer or a floating-point double.
> - * The eight-byte alignment is not required by 32-bit MIPS integer
> - * hardware, but it's essential for compatibility with CPUs with
> - * 64-bit registers, and thus part of the rules. Subroutines fit
> - * in with this by always adjusting the stack pointer by a multiple
> - * of eight.
> - * ...
> - * SGI's n32 and n64 standards call for the stack to be maintained
> - * with 16-byte alignment.
> - *
> - */
> -
> -#if (STACK_BASE + STACK_SIZE) % 16 != 0
> -#error stack pointer must be 16-byte-aligned
> -#endif
> -
> -stack_setup:
> - la sp, STACK_BASE + STACK_SIZE
> -
> - /* reserve four 32-bit argument slots */
> - addiu sp, -16
> -
> - la v0, main_entry
> - jal v0
> - nop
> -
> - /* No return */
> -
> -__error:
> - b __error
> - nop
> --
> 1.7.10.4
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC 1/3] MIPS: add pre-bootloader (pbl) image support
2012-11-17 12:10 ` [RFC 1/3] " Antony Pavlov
@ 2012-11-20 7:59 ` Sascha Hauer
2012-11-24 15:45 ` Antony Pavlov
0 siblings, 1 reply; 9+ messages in thread
From: Sascha Hauer @ 2012-11-20 7:59 UTC (permalink / raw)
To: Antony Pavlov; +Cc: barebox
On Sat, Nov 17, 2012 at 04:10:37PM +0400, Antony Pavlov wrote:
> This patch is based on ARM pbl support and allows
> creating a pre-bootloader binary for compressed image.
>
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> ---
> arch/mips/Kconfig | 2 +
> arch/mips/Makefile | 18 +++++
> arch/mips/boot/Makefile | 2 +
> arch/mips/boot/main_entry-pbl.c | 90 ++++++++++++++++++++++++
> arch/mips/boot/start-pbl.S | 146 +++++++++++++++++++++++++++++++++++++++
> arch/mips/pbl/.gitignore | 6 ++
> arch/mips/pbl/Makefile | 40 +++++++++++
> arch/mips/pbl/piggy.gzip.S | 6 ++
> arch/mips/pbl/piggy.lzo.S | 6 ++
> arch/mips/pbl/zbarebox.lds.S | 57 +++++++++++++++
> 10 files changed, 373 insertions(+)
> create mode 100644 arch/mips/boot/main_entry-pbl.c
> create mode 100644 arch/mips/boot/start-pbl.S
> create mode 100644 arch/mips/pbl/.gitignore
> create mode 100644 arch/mips/pbl/Makefile
> create mode 100644 arch/mips/pbl/piggy.gzip.S
> create mode 100644 arch/mips/pbl/piggy.lzo.S
> create mode 100644 arch/mips/pbl/zbarebox.lds.S
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 7a1eeac..853d406 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -6,6 +6,8 @@ config MIPS
> select HAS_KALLSYMS
> select HAVE_CONFIGURABLE_MEMORY_LAYOUT
> select HAVE_CONFIGURABLE_TEXT_BASE
> + select HAVE_PBL_IMAGE
> + select HAVE_IMAGE_COMPRESSION
> default y
>
> config SYS_SUPPORTS_BIG_ENDIAN
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index 5e40de7..819e7a3 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -58,6 +58,15 @@ CPPFLAGS += -fdata-sections -ffunction-sections
> LDFLAGS_barebox += -static --gc-sections
> endif
>
> +ifdef CONFIG_IMAGE_COMPRESSION
> +KBUILD_BINARY := arch/mips/pbl/zbarebox.bin
> +KBUILD_TARGET := zbarebox.bin
> +$(KBUILD_BINARY): $(KBUILD_TARGET)
> +else
> +KBUILD_BINARY := barebox.bin
> +KBUILD_TARGET := barebox.bin
> +endif
> +
> LDFLAGS_barebox += -nostdlib
>
> machine-$(CONFIG_MACH_MIPS_MALTA) := malta
> @@ -106,3 +115,12 @@ CFLAGS += $(cflags-y)
> lds-$(CONFIG_GENERIC_LINKER_SCRIPT) := arch/mips/lib/barebox.lds
>
> CLEAN_FILES += arch/mips/lib/barebox.lds barebox.map barebox.S
> +
> +pbl := arch/mips/pbl
> +zbarebox.S zbarebox.bin zbarebox: barebox.bin
> + $(Q)$(MAKE) $(build)=$(pbl) $(pbl)/$@
> +
> +archclean:
> + $(MAKE) $(clean)=$(pbl)
> +
> +KBUILD_IMAGE ?= $(KBUILD_BINARY)
> diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
> index d6d28ce..6b093f1 100644
> --- a/arch/mips/boot/Makefile
> +++ b/arch/mips/boot/Makefile
> @@ -1,2 +1,4 @@
> obj-y += start.o
> obj-y += main_entry.o
> +
> +pbl-y += start-pbl.o main_entry-pbl.o
> diff --git a/arch/mips/boot/main_entry-pbl.c b/arch/mips/boot/main_entry-pbl.c
> new file mode 100644
> index 0000000..51b9176
> --- /dev/null
> +++ b/arch/mips/boot/main_entry-pbl.c
> @@ -0,0 +1,90 @@
> +/*
> + * Copyright (C) 2012 Antony Pavlov <antonynpavlov@gmail.com>
> + *
> + * This file is part of barebox.
> + * See file CREDITS for list of people who contributed to this project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +#include <sizes.h>
> +#include <string.h>
> +#include <asm/sections.h>
> +#include <asm-generic/memory_layout.h>
> +#include <debug_ll.h>
> +
> +extern void *input_data;
> +extern void *input_data_end;
> +
> +unsigned long free_mem_ptr;
> +unsigned long free_mem_end_ptr;
> +
> +#define STATIC static
> +
> +#ifdef CONFIG_IMAGE_COMPRESSION_LZO
> +#include "../../../lib/decompress_unlzo.c"
> +#endif
> +
> +#ifdef CONFIG_IMAGE_COMPRESSION_GZIP
> +#include "../../../lib/decompress_inflate.c"
> +#endif
> +
> +void pbl_main_entry(void);
> +
> +static unsigned long *ttb;
> +
> +static noinline void errorfn(char *error)
> +{
> + PUTS_LL(error);
> + PUTC_LL('\n');
> +
> + unreachable();
> +}
> +
> +static void barebox_uncompress(void *compressed_start, unsigned int len)
> +{
> + /* set 128 KiB at the end of the MALLOC_BASE for early malloc */
> + free_mem_ptr = MALLOC_BASE + MALLOC_SIZE - SZ_128K;
> + free_mem_end_ptr = free_mem_ptr + SZ_128K;
> +
> + ttb = (void *)((free_mem_ptr - 0x4000) & ~0x3fff);
> +
> + decompress((void *)compressed_start,
> + len,
> + NULL, NULL,
> + (void *)TEXT_BASE, NULL, errorfn);
> +
> + /* FIXME: just now we have no MIPS cache support */
> + /* flush_icache(); */
> +}
> +
> +void __section(.text_entry) pbl_main_entry(void)
> +{
> + u32 pg_start, pg_end, pg_len;
> + void (*barebox)(void);
> +
> + PUTS_LL("pbl_main_entry()\n");
> +
> + /* clear bss */
> + memset(__bss_start, 0, __bss_stop - __bss_start);
> +
> + pg_start = (u32)&input_data;
> + pg_end = (u32)&input_data_end;
> + pg_len = pg_end - pg_start;
> +
> + barebox_uncompress(&input_data, pg_len);
> +
> + barebox = (void *)TEXT_BASE;
> + barebox();
> +}
> diff --git a/arch/mips/boot/start-pbl.S b/arch/mips/boot/start-pbl.S
> new file mode 100644
> index 0000000..ad39f42
> --- /dev/null
> +++ b/arch/mips/boot/start-pbl.S
> @@ -0,0 +1,146 @@
> +/*
> + * Startup Code for MIPS CPU
> + *
> + * Copyright (C) 2011, 2012 Antony Pavlov <antonynpavlov@gmail.com>
> + * ADR macro copyrighted (C) 2009 by Shinya Kuribayashi <skuribay@pobox.com>
> + *
> + * This file is part of barebox.
> + * See file CREDITS for list of people who contributed to this project.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2
> + * as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include <asm/regdef.h>
> +#include <asm/mipsregs.h>
> +#include <asm/asm.h>
> +#include <asm-generic/memory_layout.h>
> +#include <generated/compile.h>
> +#include <generated/utsrelease.h>
> +
> +//#include <mach/kernel-entry-init.h>
> +
> + /*
> + * ADR macro instruction (inspired by ARM)
> + *
> + * ARM architecture doesn't have PC-relative jump instruction
> + * like MIPS' B/BAL insns. When ARM makes PC-relative jumps,
> + * it uses ADR insn. ADR is used to get a destination address
> + * of 'label' against current PC. With this, ARM can safely
> + * make PC-relative jumps.
> + */
> + .macro ADR rd label temp
> + .set push
> + .set noreorder
> + move \temp, ra # preserve ra beforehand
> + bal _pc
> + nop
This file contains some whitespace damages you could cleanup along the
way.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC 1/3] MIPS: add pre-bootloader (pbl) image support
2012-11-20 7:59 ` Sascha Hauer
@ 2012-11-24 15:45 ` Antony Pavlov
2012-11-26 8:05 ` Sascha Hauer
0 siblings, 1 reply; 9+ messages in thread
From: Antony Pavlov @ 2012-11-24 15:45 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
Sorry for delay.
On 20 November 2012 11:59, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Sat, Nov 17, 2012 at 04:10:37PM +0400, Antony Pavlov wrote:
>> This patch is based on ARM pbl support and allows
>> creating a pre-bootloader binary for compressed image.
>>
>> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
>> ---
>> arch/mips/Kconfig | 2 +
>> arch/mips/Makefile | 18 +++++
>> arch/mips/boot/Makefile | 2 +
>> arch/mips/boot/main_entry-pbl.c | 90 ++++++++++++++++++++++++
>> arch/mips/boot/start-pbl.S | 146 +++++++++++++++++++++++++++++++++++++++
>> arch/mips/pbl/.gitignore | 6 ++
>> arch/mips/pbl/Makefile | 40 +++++++++++
>> arch/mips/pbl/piggy.gzip.S | 6 ++
>> arch/mips/pbl/piggy.lzo.S | 6 ++
>> arch/mips/pbl/zbarebox.lds.S | 57 +++++++++++++++
>> 10 files changed, 373 insertions(+)
>> create mode 100644 arch/mips/boot/main_entry-pbl.c
>> create mode 100644 arch/mips/boot/start-pbl.S
>> create mode 100644 arch/mips/pbl/.gitignore
>> create mode 100644 arch/mips/pbl/Makefile
>> create mode 100644 arch/mips/pbl/piggy.gzip.S
>> create mode 100644 arch/mips/pbl/piggy.lzo.S
>> create mode 100644 arch/mips/pbl/zbarebox.lds.S
>>
>> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
>> index 7a1eeac..853d406 100644
>> --- a/arch/mips/Kconfig
>> +++ b/arch/mips/Kconfig
>> @@ -6,6 +6,8 @@ config MIPS
>> select HAS_KALLSYMS
>> select HAVE_CONFIGURABLE_MEMORY_LAYOUT
>> select HAVE_CONFIGURABLE_TEXT_BASE
>> + select HAVE_PBL_IMAGE
>> + select HAVE_IMAGE_COMPRESSION
>> default y
>>
>> config SYS_SUPPORTS_BIG_ENDIAN
>> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
>> index 5e40de7..819e7a3 100644
>> --- a/arch/mips/Makefile
>> +++ b/arch/mips/Makefile
>> @@ -58,6 +58,15 @@ CPPFLAGS += -fdata-sections -ffunction-sections
>> LDFLAGS_barebox += -static --gc-sections
>> endif
>>
>> +ifdef CONFIG_IMAGE_COMPRESSION
>> +KBUILD_BINARY := arch/mips/pbl/zbarebox.bin
>> +KBUILD_TARGET := zbarebox.bin
>> +$(KBUILD_BINARY): $(KBUILD_TARGET)
>> +else
>> +KBUILD_BINARY := barebox.bin
>> +KBUILD_TARGET := barebox.bin
>> +endif
>> +
>> LDFLAGS_barebox += -nostdlib
>>
>> machine-$(CONFIG_MACH_MIPS_MALTA) := malta
>> @@ -106,3 +115,12 @@ CFLAGS += $(cflags-y)
>> lds-$(CONFIG_GENERIC_LINKER_SCRIPT) := arch/mips/lib/barebox.lds
>>
>> CLEAN_FILES += arch/mips/lib/barebox.lds barebox.map barebox.S
>> +
>> +pbl := arch/mips/pbl
>> +zbarebox.S zbarebox.bin zbarebox: barebox.bin
>> + $(Q)$(MAKE) $(build)=$(pbl) $(pbl)/$@
>> +
>> +archclean:
>> + $(MAKE) $(clean)=$(pbl)
>> +
>> +KBUILD_IMAGE ?= $(KBUILD_BINARY)
>> diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
>> index d6d28ce..6b093f1 100644
>> --- a/arch/mips/boot/Makefile
>> +++ b/arch/mips/boot/Makefile
>> @@ -1,2 +1,4 @@
>> obj-y += start.o
>> obj-y += main_entry.o
>> +
>> +pbl-y += start-pbl.o main_entry-pbl.o
>> diff --git a/arch/mips/boot/main_entry-pbl.c b/arch/mips/boot/main_entry-pbl.c
>> new file mode 100644
>> index 0000000..51b9176
>> --- /dev/null
>> +++ b/arch/mips/boot/main_entry-pbl.c
>> @@ -0,0 +1,90 @@
>> +/*
>> + * Copyright (C) 2012 Antony Pavlov <antonynpavlov@gmail.com>
>> + *
>> + * This file is part of barebox.
>> + * See file CREDITS for list of people who contributed to this project.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + */
>> +
>> +#include <common.h>
>> +#include <init.h>
>> +#include <sizes.h>
>> +#include <string.h>
>> +#include <asm/sections.h>
>> +#include <asm-generic/memory_layout.h>
>> +#include <debug_ll.h>
>> +
>> +extern void *input_data;
>> +extern void *input_data_end;
>> +
>> +unsigned long free_mem_ptr;
>> +unsigned long free_mem_end_ptr;
>> +
>> +#define STATIC static
>> +
>> +#ifdef CONFIG_IMAGE_COMPRESSION_LZO
>> +#include "../../../lib/decompress_unlzo.c"
>> +#endif
>> +
>> +#ifdef CONFIG_IMAGE_COMPRESSION_GZIP
>> +#include "../../../lib/decompress_inflate.c"
>> +#endif
>> +
>> +void pbl_main_entry(void);
>> +
>> +static unsigned long *ttb;
>> +
>> +static noinline void errorfn(char *error)
>> +{
>> + PUTS_LL(error);
>> + PUTC_LL('\n');
>> +
>> + unreachable();
>> +}
>> +
>> +static void barebox_uncompress(void *compressed_start, unsigned int len)
>> +{
>> + /* set 128 KiB at the end of the MALLOC_BASE for early malloc */
>> + free_mem_ptr = MALLOC_BASE + MALLOC_SIZE - SZ_128K;
>> + free_mem_end_ptr = free_mem_ptr + SZ_128K;
>> +
>> + ttb = (void *)((free_mem_ptr - 0x4000) & ~0x3fff);
>> +
>> + decompress((void *)compressed_start,
>> + len,
>> + NULL, NULL,
>> + (void *)TEXT_BASE, NULL, errorfn);
>> +
>> + /* FIXME: just now we have no MIPS cache support */
>> + /* flush_icache(); */
>> +}
>> +
>> +void __section(.text_entry) pbl_main_entry(void)
>> +{
>> + u32 pg_start, pg_end, pg_len;
>> + void (*barebox)(void);
>> +
>> + PUTS_LL("pbl_main_entry()\n");
>> +
>> + /* clear bss */
>> + memset(__bss_start, 0, __bss_stop - __bss_start);
>> +
>> + pg_start = (u32)&input_data;
>> + pg_end = (u32)&input_data_end;
>> + pg_len = pg_end - pg_start;
>> +
>> + barebox_uncompress(&input_data, pg_len);
>> +
>> + barebox = (void *)TEXT_BASE;
>> + barebox();
>> +}
>> diff --git a/arch/mips/boot/start-pbl.S b/arch/mips/boot/start-pbl.S
>> new file mode 100644
>> index 0000000..ad39f42
>> --- /dev/null
>> +++ b/arch/mips/boot/start-pbl.S
>> @@ -0,0 +1,146 @@
>> +/*
>> + * Startup Code for MIPS CPU
>> + *
>> + * Copyright (C) 2011, 2012 Antony Pavlov <antonynpavlov@gmail.com>
>> + * ADR macro copyrighted (C) 2009 by Shinya Kuribayashi <skuribay@pobox.com>
>> + *
>> + * This file is part of barebox.
>> + * See file CREDITS for list of people who contributed to this project.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2
>> + * as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + */
>> +
>> +#include <asm/regdef.h>
>> +#include <asm/mipsregs.h>
>> +#include <asm/asm.h>
>> +#include <asm-generic/memory_layout.h>
>> +#include <generated/compile.h>
>> +#include <generated/utsrelease.h>
>> +
>> +//#include <mach/kernel-entry-init.h>
>> +
>> + /*
>> + * ADR macro instruction (inspired by ARM)
>> + *
>> + * ARM architecture doesn't have PC-relative jump instruction
>> + * like MIPS' B/BAL insns. When ARM makes PC-relative jumps,
>> + * it uses ADR insn. ADR is used to get a destination address
>> + * of 'label' against current PC. With this, ARM can safely
>> + * make PC-relative jumps.
>> + */
>> + .macro ADR rd label temp
>> + .set push
>> + .set noreorder
>> + move \temp, ra # preserve ra beforehand
>> + bal _pc
>> + nop
>
> This file contains some whitespace damages you could cleanup along the
> way.
If you are about this fragment
>> + bal _pc
>> + nop
then there is no whitespace damage --- the 'nop' instruction is in the
delay slot of the branch instruction (bal).
--
Best regards,
Antony Pavlov
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC 2/3] MIPS: boot: realize _start in C
2012-11-20 7:58 ` Sascha Hauer
@ 2012-11-24 16:18 ` Antony Pavlov
0 siblings, 0 replies; 9+ messages in thread
From: Antony Pavlov @ 2012-11-24 16:18 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
Sorry for delay.
On 20 November 2012 11:58, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> On Sat, Nov 17, 2012 at 04:10:38PM +0400, Antony Pavlov wrote:
>> The pbl will be incharge of the lowlevel init and
>> barebox relocation. So we can skip it in barebox itself
>> and use simple _start.
>>
>> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
>> ---
>> arch/mips/boot/Makefile | 1 -
>> arch/mips/boot/main_entry.c | 18 ++++++
>> arch/mips/boot/start.S | 142 -------------------------------------------
>> 3 files changed, 18 insertions(+), 143 deletions(-)
>> delete mode 100644 arch/mips/boot/start.S
>>
>> diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
>> index 6b093f1..4f11a48 100644
>> --- a/arch/mips/boot/Makefile
>> +++ b/arch/mips/boot/Makefile
>> @@ -1,4 +1,3 @@
>> -obj-y += start.o
>> obj-y += main_entry.o
>>
>> pbl-y += start-pbl.o main_entry-pbl.o
>> diff --git a/arch/mips/boot/main_entry.c b/arch/mips/boot/main_entry.c
>> index 0a33c45..422d40b 100644
>> --- a/arch/mips/boot/main_entry.c
>> +++ b/arch/mips/boot/main_entry.c
>> @@ -22,6 +22,8 @@
>> #include <asm/cpu-features.h>
>> #include <asm/mipsregs.h>
>> #include <asm/addrspace.h>
>> +#include <asm/regdef.h>
>> +#include <asm-generic/memory_layout.h>
>>
>> extern void start_barebox(void);
>> extern void handle_reserved(void);
>> @@ -92,3 +94,19 @@ void main_entry(void)
>>
>> start_barebox();
>> }
>> +
>> +void __naked __section(.text_entry) _start(void)
>> +{
>> + u32 r;
>> +
>> + /* setup the stack */
>> + r = STACK_BASE + STACK_SIZE - 16;
>> +
>> + __asm__ __volatile__(
>> + "move\t$sp, %0\n\t"
>> + : /* no outputs */
>> + : "r" (r)
>> + );
>> +
>> + main_entry();
>
> I wonder that the C function skips several things the Assembler version
> does. Is this done in the pbl now?
Yes, all lowlevel init is in pbl after this patch.
> Does this patch make the pbl mandatory?
Not at all, but the patch decrease pbl-free barebox "survival".
> We haven't done this on Arm, mostly because we were not
> confident enough that it works on every board. That may be different on
> mips, but should be mentioned in the commit log. But maybe I am
> misreading the patches...
Now I think you are right and we must postpone this patch. It make
sense to introduce this patch after full ELF support adding. If we had
ELF support, we should load barebox ELF image without pbl and drop
bin-image support in bootm.
--
Best regards,
Antony Pavlov
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC 1/3] MIPS: add pre-bootloader (pbl) image support
2012-11-24 15:45 ` Antony Pavlov
@ 2012-11-26 8:05 ` Sascha Hauer
0 siblings, 0 replies; 9+ messages in thread
From: Sascha Hauer @ 2012-11-26 8:05 UTC (permalink / raw)
To: Antony Pavlov; +Cc: barebox
On Sat, Nov 24, 2012 at 07:45:01PM +0400, Antony Pavlov wrote:
> Sorry for delay.
>
> On 20 November 2012 11:59, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > On Sat, Nov 17, 2012 at 04:10:37PM +0400, Antony Pavlov wrote:
> >> This patch is based on ARM pbl support and allows
> >> creating a pre-bootloader binary for compressed image.
> >>
> >> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> >> ---
> >> + .macro ADR rd label temp
> >> + .set push
> >> + .set noreorder
> >> + move \temp, ra # preserve ra beforehand
> >> + bal _pc
> >> + nop
> >
> > This file contains some whitespace damages you could cleanup along the
> > way.
>
> If you are about this fragment
> >> + bal _pc
> >> + nop
>
> then there is no whitespace damage --- the 'nop' instruction is in the
> delay slot of the branch instruction (bal).
Ok, forget this one. I'm not familiar with Mips assembly.
Sascha
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2012-11-26 8:05 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-11-17 12:10 [RFC 0/3] MIPS: add pre-bootloader (pbl) image support Antony Pavlov
2012-11-17 12:10 ` [RFC 1/3] " Antony Pavlov
2012-11-20 7:59 ` Sascha Hauer
2012-11-24 15:45 ` Antony Pavlov
2012-11-26 8:05 ` Sascha Hauer
2012-11-17 12:10 ` [RFC 2/3] MIPS: boot: realize _start in C Antony Pavlov
2012-11-20 7:58 ` Sascha Hauer
2012-11-24 16:18 ` Antony Pavlov
2012-11-17 12:10 ` [RFC 3/3] MIPS: qemu-malta_defconfig: use pbl Antony Pavlov
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