From: Juergen Beisert <jbe@pengutronix.de>
To: barebox@lists.infradead.org
Subject: Re: s3c2440's register: MRSR6
Date: Sun, 13 Jan 2013 11:55:59 +0100 [thread overview]
Message-ID: <201301131156.00055.jbe@pengutronix.de> (raw)
In-Reply-To: <5908839.6Wy9GUm0p4@yiqingliang-pc>
Hi Yi,
niqingliang2003@gmail.com wrote:
> Hello, I compiled barebox (based on mini2440).
> and start from nand, can't start normally,
> after changed MRSRB6 to 0x30, ok.
>
> I have checked uboot, it does use 0x30 for mini2440.
> but barebox use 0x20 (work on mini2440, but not work on my 2442
> board).
>
> what does it depend on?
> in other words, what does the CL value depend on?
You should read the manual of the used SDRAM. As SDRAM is a synchronous
memory, the SDRAM device and the SDRAM controller must be programmed in the
same way (same CL value).
The CL value in MRSRB6 must correspond with the Trcd in the BANKCON* register.
Note: the impact of higher CL values is huge. Data throughput with 100 MHz @
CL2 is higher than at 133 MHz @ CL3.
Regards,
Juergen
--
Pengutronix e.K. | Juergen Beisert |
Linux Solutions for Science and Industry | http://www.pengutronix.de/ |
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prev parent reply other threads:[~2013-01-13 10:56 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-12 9:53 niqingliang2003
2013-01-13 10:55 ` Juergen Beisert [this message]
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