* [PATCH] Add DataModul Realq7 board support
@ 2013-03-08 12:08 Sascha Hauer
2013-03-08 12:08 ` [PATCH 1/3] ARM i.MX6: Add mmdc calibration support Sascha Hauer
` (2 more replies)
0 siblings, 3 replies; 14+ messages in thread
From: Sascha Hauer @ 2013-03-08 12:08 UTC (permalink / raw)
To: barebox
This adds support for the DataModul Realq7 board. This is
a i.MX6 based board with a q7 form factor.
Sascha
----------------------------------------------------------------
Sascha Hauer (3):
ARM i.MX6: Add mmdc calibration support
Add DMO RealQ7 board support
Add DMO RealQ7 defconfig
arch/arm/Makefile | 1 +
arch/arm/boards/dmo-mx6-realq7/Makefile | 2 +
arch/arm/boards/dmo-mx6-realq7/board.c | 404 +++++++++++
arch/arm/boards/dmo-mx6-realq7/config.h | 4 +
arch/arm/boards/dmo-mx6-realq7/env/init/hostname | 8 +
arch/arm/boards/dmo-mx6-realq7/flash_header.c | 40 ++
arch/arm/boards/dmo-mx6-realq7/lowlevel.c | 146 ++++
arch/arm/configs/dmo-realq7_defconfig | 91 +++
arch/arm/mach-imx/Kconfig | 6 +
arch/arm/mach-imx/Makefile | 3 +-
arch/arm/mach-imx/imx6-mmdc.c | 839 +++++++++++++++++++++++
arch/arm/mach-imx/include/mach/devices-imx6.h | 20 +
arch/arm/mach-imx/include/mach/imx6-mmdc.h | 7 +
13 files changed, 1570 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boards/dmo-mx6-realq7/Makefile
create mode 100644 arch/arm/boards/dmo-mx6-realq7/board.c
create mode 100644 arch/arm/boards/dmo-mx6-realq7/config.h
create mode 100644 arch/arm/boards/dmo-mx6-realq7/env/init/hostname
create mode 100644 arch/arm/boards/dmo-mx6-realq7/flash_header.c
create mode 100644 arch/arm/boards/dmo-mx6-realq7/lowlevel.c
create mode 100644 arch/arm/configs/dmo-realq7_defconfig
create mode 100644 arch/arm/mach-imx/imx6-mmdc.c
create mode 100644 arch/arm/mach-imx/include/mach/imx6-mmdc.h
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 1/3] ARM i.MX6: Add mmdc calibration support 2013-03-08 12:08 [PATCH] Add DataModul Realq7 board support Sascha Hauer @ 2013-03-08 12:08 ` Sascha Hauer 2013-03-08 12:17 ` Alexander Shiyan 2013-03-08 12:46 ` Jean-Christophe PLAGNIOL-VILLARD 2013-03-08 12:08 ` [PATCH 2/3] Add DMO RealQ7 board support Sascha Hauer 2013-03-08 12:08 ` [PATCH 3/3] Add DMO RealQ7 defconfig Sascha Hauer 2 siblings, 2 replies; 14+ messages in thread From: Sascha Hauer @ 2013-03-08 12:08 UTC (permalink / raw) To: barebox This adds support for the various DDR calibration functions in the i.MX6 MMDC. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- arch/arm/mach-imx/Makefile | 3 +- arch/arm/mach-imx/imx6-mmdc.c | 839 +++++++++++++++++++++++++++++ arch/arm/mach-imx/include/mach/imx6-mmdc.h | 7 + 3 files changed, 848 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-imx/imx6-mmdc.c create mode 100644 arch/arm/mach-imx/include/mach/imx6-mmdc.h diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 4adf522..5f95ff4 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -8,7 +8,8 @@ obj-$(CONFIG_ARCH_IMX35) += imx35.o iomux-v3.o clk-imx35.o obj-$(CONFIG_ARCH_IMX51) += imx51.o iomux-v3.o imx5.o clk-imx5.o obj-$(CONFIG_ARCH_IMX53) += imx53.o iomux-v3.o imx5.o clk-imx5.o esdctl-v4.o pbl-$(CONFIG_ARCH_IMX53) += imx53.o imx5.o esdctl-v4.o -obj-$(CONFIG_ARCH_IMX6) += imx6.o iomux-v3.o usb-imx6.o clk-imx6.o +obj-$(CONFIG_ARCH_IMX6) += imx6.o iomux-v3.o usb-imx6.o clk-imx6.o imx6-mmdc.o +pbl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o obj-$(CONFIG_IMX_IIM) += iim.o obj-$(CONFIG_NAND_IMX) += nand.o lwl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o diff --git a/arch/arm/mach-imx/imx6-mmdc.c b/arch/arm/mach-imx/imx6-mmdc.c new file mode 100644 index 0000000..66136d3 --- /dev/null +++ b/arch/arm/mach-imx/imx6-mmdc.c @@ -0,0 +1,839 @@ +#include <common.h> +#include <io.h> +#include <mach/imx6-regs.h> +#include <mach/imx6-mmdc.h> + +#define MMDC_P0_IPS_BASE_ADDR 0x021b0000 +#define MMDC_P1_IPS_BASE_ADDR 0x021b4000 + +#define MDCTL_OFFSET 0x000 +#define MDPDC_OFFSET 0x004 +#define MDSCR_OFFSET 0x01c +#define MDMISC_OFFSET 0x018 +#define MDREF_OFFSET 0x020 +#define MAPSR_OFFSET 0x404 +#define MPZQHWCTRL_OFFSET 0x800 +#define MPWLGCR_OFFSET 0x808 +#define MPWLDECTRL0_OFFSET 0x80c +#define MPWLDECTRL1_OFFSET 0x810 +#define MPPDCMPR1_OFFSET 0x88c +#define MPSWDAR_OFFSET 0x894 +#define MPRDDLCTL_OFFSET 0x848 +#define MPMUR_OFFSET 0x8b8 +#define MPDGCTRL0_OFFSET 0x83c +#define MPDGHWST0_OFFSET 0x87c +#define MPDGHWST1_OFFSET 0x880 +#define MPDGHWST2_OFFSET 0x884 +#define MPDGHWST3_OFFSET 0x888 +#define MPDGCTRL1_OFFSET 0x840 +#define MPRDDLHWCTL_OFFSET 0x860 +#define MPWRDLCTL_OFFSET 0x850 +#define MPWRDLHWCTL_OFFSET 0x864 + +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 (MX6_IOMUXC_BASE_ADDR + 0x5a8) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 (MX6_IOMUXC_BASE_ADDR + 0x5b0) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 (MX6_IOMUXC_BASE_ADDR + 0x524) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 (MX6_IOMUXC_BASE_ADDR + 0x51c) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 (MX6_IOMUXC_BASE_ADDR + 0x518) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 (MX6_IOMUXC_BASE_ADDR + 0x50c) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 (MX6_IOMUXC_BASE_ADDR + 0x5b8) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 (MX6_IOMUXC_BASE_ADDR + 0x5c0) + +static inline u32 reg32_read(u32 reg) +{ + return readl(reg); +} + +static inline void reg32_write(u32 reg, u32 val) +{ + writel(val, reg); +} + +static inline void reg32setbit(u32 reg, int bit) +{ + u32 val; + + val = readl(reg); + val |= 1 << bit; + writel(val, reg); +} + +static inline void reg32clrbit(u32 reg, int bit) +{ + u32 val; + + val = readl(reg); + val &= ~(1 << bit); + writel(val, reg); +} + +int mmdc_do_write_level_calibration(void) +{ + u32 esdmisc_val, zq_val; + int errorcount = 0; + u32 val; + u32 ddr_mr1 = 0x4; + + /* disable DDR logic power down timer */ + val = readl((MMDC_P0_IPS_BASE_ADDR + MDPDC_OFFSET)); + val &= 0xffff00ff; + writel(val, (MMDC_P0_IPS_BASE_ADDR + MDPDC_OFFSET)), + + /* disable Adopt power down timer */ + val = readl((MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET)); + val |= 0x1; + writel(val, (MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET)); + + debug("Start write leveling calibration \n"); + + /* + * disable auto refresh and ZQ calibration + * before proceeding with Write Leveling calibration + */ + esdmisc_val = readl(MMDC_P0_IPS_BASE_ADDR + MDREF_OFFSET); + writel(0x0000C000, (MMDC_P0_IPS_BASE_ADDR + MDREF_OFFSET)); + zq_val = readl(MMDC_P0_IPS_BASE_ADDR + MPZQHWCTRL_OFFSET); + writel(zq_val & ~(0x3), (MMDC_P0_IPS_BASE_ADDR + MPZQHWCTRL_OFFSET)); + + /* + * Configure the external DDR device to enter write leveling mode + * through Load Mode Register command + * Register setting: + * Bits[31:16] MR1 value (0x0080 write leveling enable) + * Bit[9] set WL_EN to enable MMDC DQS output + * Bits[6:4] set CMD bits for Load Mode Register programming + * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming + */ + writel(0x00808231, MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET); + + /* Activate automatic calibration by setting MPWLGCR[HW_WL_EN] */ + writel(0x00000001, MMDC_P0_IPS_BASE_ADDR + MPWLGCR_OFFSET); + + /* Upon completion of this process the MMDC de-asserts the MPWLGCR[HW_WL_EN] */ + while (readl(MMDC_P0_IPS_BASE_ADDR + MPWLGCR_OFFSET) & 0x00000001); + + /* check for any errors: check both PHYs for x64 configuration, if x32, check only PHY0 */ + if ((readl(MMDC_P0_IPS_BASE_ADDR + MPWLGCR_OFFSET) & 0x00000F00) || + (readl(MMDC_P1_IPS_BASE_ADDR + MPWLGCR_OFFSET) & 0x00000F00)) { + errorcount++; + } + + debug("Write leveling calibration completed\n"); + + /* + * User should issue MRS command to exit write leveling mode + * through Load Mode Register command + * Register setting: + * Bits[31:16] MR1 value "ddr_mr1" value from initialization + * Bit[9] clear WL_EN to disable MMDC DQS output + * Bits[6:4] set CMD bits for Load Mode Register programming + * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming + */ + writel(((ddr_mr1 << 16)+0x8031), MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET); + + /* re-enable to auto refresh and zq cal */ + writel(esdmisc_val, (MMDC_P0_IPS_BASE_ADDR + MDREF_OFFSET)); + writel(zq_val, (MMDC_P0_IPS_BASE_ADDR + MPZQHWCTRL_OFFSET)); + + debug("MMDC_MPWLDECTRL0 after write level cal: 0x%08X\n", + readl(MMDC_P0_IPS_BASE_ADDR + MPWLDECTRL0_OFFSET)); + debug("MMDC_MPWLDECTRL1 after write level cal: 0x%08X\n", + readl(MMDC_P0_IPS_BASE_ADDR + MPWLDECTRL1_OFFSET)); + debug("MMDC_MPWLDECTRL0 after write level cal: 0x%08X\n", + readl(MMDC_P1_IPS_BASE_ADDR + MPWLDECTRL0_OFFSET)); + debug("MMDC_MPWLDECTRL1 after write level cal: 0x%08X\n", + readl(MMDC_P1_IPS_BASE_ADDR + MPWLDECTRL1_OFFSET)); + + /* enable DDR logic power down timer */ + val = readl((MMDC_P0_IPS_BASE_ADDR + MDPDC_OFFSET)); + val |= 0x00005500; + writel(val, (MMDC_P0_IPS_BASE_ADDR + MDPDC_OFFSET)); + + /* enable Adopt power down timer: */ + val = readl(MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET); + val &= 0xfffffff7; + writel(val, (MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET)); + + /* clear CON_REQ */ + writel(0, (MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET)); + + return 0; +} + +static void modify_dg_result(int reg_st0, int reg_st1, int reg_ctrl) +{ + u32 dg_tmp_val, dg_dl_abs_offset, dg_hc_del, val_ctrl; + + /* + * DQS gating absolute offset should be modified from reflecting (HW_DG_LOWx + HW_DG_UPx)/2 + * to reflecting (HW_DG_UPx - 0x80) + */ + + val_ctrl = reg32_read(reg_ctrl); + val_ctrl &= 0xf0000000; + + dg_tmp_val = ((reg32_read(reg_st0) & 0x07ff0000) >> 16) - 0xc0; + dg_dl_abs_offset = dg_tmp_val & 0x7f; + dg_hc_del = (dg_tmp_val & 0x780) << 1; + + val_ctrl |= dg_dl_abs_offset + dg_hc_del; + + dg_tmp_val = ((reg32_read(reg_st1) & 0x07ff0000) >> 16) - 0xc0; + dg_dl_abs_offset = dg_tmp_val & 0x7f; + dg_hc_del = (dg_tmp_val & 0x780) << 1; + + val_ctrl |= (dg_dl_abs_offset + dg_hc_del) << 16; + + reg32_write(reg_ctrl, val_ctrl); +} + +static void mmdc_precharge_all(int cs0_enable, int cs1_enable) +{ + /* + * Issue the Precharge-All command to the DDR device for both chip selects + * Note, CON_REQ bit should also remain set + * If only using one chip select, then precharge only the desired chip select + */ + if (cs0_enable) + reg32_write((MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET), 0x04008050); + if (cs1_enable) + reg32_write((MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET), 0x04008058); +} + +static void mmdc_force_delay_measurement(int data_bus_size) +{ + reg32_write(MMDC_P0_IPS_BASE_ADDR + MPMUR_OFFSET, 0x800); + + if (data_bus_size == 0x2) + reg32_write(MMDC_P1_IPS_BASE_ADDR + MPMUR_OFFSET, 0x800); +} + +static void mmdc_reset_read_data_fifos(void) +{ + /* + * Reset the read data FIFOs (two resets); only need to issue reset to PHY0 since in x64 + * mode, the reset will also go to PHY1 + * read data FIFOs reset1 + */ + reg32_write((MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET), + reg32_read((MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET)) | 0x80000000); + + while (reg32_read((MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET)) & 0x80000000); + + /* read data FIFOs reset2 */ + reg32_write((MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET), + reg32_read((MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET)) | 0x80000000); + + while (reg32_read((MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET)) & 0x80000000); +} + +int mmdc_do_dqs_calibration(void) +{ + u32 esdmisc_val; + int g_error_write_cal; + int temp_ref; + int cs0_enable_initial; + int cs1_enable_initial; + int PDDWord = 0x00ffff00; + int errorcount = 0; + int cs0_enable; + int cs1_enable; + int data_bus_size; + + /* check to see which chip selects are enabled */ + cs0_enable_initial = (reg32_read(MMDC_P0_IPS_BASE_ADDR + MDCTL_OFFSET) & 0x80000000) >> 31; + cs1_enable_initial = (reg32_read(MMDC_P0_IPS_BASE_ADDR + MDCTL_OFFSET) & 0x40000000) >> 30; + + /* disable DDR logic power down timer */ + reg32_write(MMDC_P0_IPS_BASE_ADDR + MDPDC_OFFSET, + reg32_read((MMDC_P0_IPS_BASE_ADDR + MDPDC_OFFSET)) & 0xffff00ff); + + /* disable Adopt power down timer */ + reg32_write(MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET, + reg32_read((MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET)) | 0x1); + + /* set DQS pull ups */ + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0) | 0x7000); + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1) | 0x7000); + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2) | 0x7000); + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3) | 0x7000); + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4) | 0x7000); + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5) | 0x7000); + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6) | 0x7000); + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7) | 0x7000); + + esdmisc_val = reg32_read(MMDC_P0_IPS_BASE_ADDR + MDMISC_OFFSET); + + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MDMISC_OFFSET, 6); /* set RALAT to max */ + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MDMISC_OFFSET, 7); + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MDMISC_OFFSET, 8); + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MDMISC_OFFSET, 16); /* set WALAT to max */ + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MDMISC_OFFSET, 17); + + /* + * disable auto refresh + * before proceeding with calibration + */ + temp_ref = reg32_read(MMDC_P0_IPS_BASE_ADDR + MDREF_OFFSET); + reg32_write(MMDC_P0_IPS_BASE_ADDR + MDREF_OFFSET, 0x0000C000); + + /* + * per the ref manual, issue one refresh cycle MDSCR[CMD]= 0x2, + * this also sets the CON_REQ bit. + */ + if (cs0_enable_initial) + reg32_write(MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET, 0x00008020); + if (cs1_enable_initial) + reg32_write(MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET, 0x00008028); + + /* poll to make sure the con_ack bit was asserted */ + while (!(reg32_read(MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET) & 0x00004000)) ; + + /* + * check MDMISC register CALIB_PER_CS to see which CS calibration is + * targeted to (under normal cases, it should be cleared as this is the + * default value, indicating calibration is directed to CS0). Disable + * the other chip select not being target for calibration to avoid any + * potential issues This will get re-enabled at end of calibration. + */ + if ((reg32_read(MMDC_P0_IPS_BASE_ADDR + MDMISC_OFFSET) & 0x00100000) == 0) + reg32clrbit(MMDC_P0_IPS_BASE_ADDR + MDCTL_OFFSET, 30); /* clear SDE_1 */ + else + reg32clrbit(MMDC_P0_IPS_BASE_ADDR + MDCTL_OFFSET, 31); /* clear SDE_0 */ + + /* + * check to see which chip selects are now enabled for the remainder + * of the calibration. + */ + cs0_enable = (reg32_read(MMDC_P0_IPS_BASE_ADDR + MDCTL_OFFSET) & 0x80000000) >> 31; + cs1_enable = (reg32_read(MMDC_P0_IPS_BASE_ADDR + MDCTL_OFFSET) & 0x40000000) >> 30; + + /* check to see what is the data bus size */ + data_bus_size = (reg32_read(MMDC_P0_IPS_BASE_ADDR + MDCTL_OFFSET) & 0x30000) >> 16; + + mmdc_precharge_all(cs0_enable, cs1_enable); + + /* Write the pre-defined value into MPPDCMPR1 */ + reg32_write((MMDC_P0_IPS_BASE_ADDR + MPPDCMPR1_OFFSET), PDDWord); + + /* + * Issue a write access to the external DDR device by setting the bit SW_DUMMY_WR (bit 0) + * in the MPSWDAR0 and then poll this bit until it clears to indicate completion of the + * write access. + */ + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET, 0); + + while (reg32_read(MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET) & 0x00000001); + + /* + * Set the RD_DL_ABS_OFFSET# bits to their default values (will be calibrated later in + * the read delay-line calibration) + * Both PHYs for x64 configuration, if x32, do only PHY0 + */ + reg32_write(MMDC_P0_IPS_BASE_ADDR + MPRDDLCTL_OFFSET, 0x40404040); + if (data_bus_size == 0x2) + reg32_write(MMDC_P1_IPS_BASE_ADDR + MPRDDLCTL_OFFSET, 0x40404040); + + /* Force a measurement, for previous delay setup to take effect */ + mmdc_force_delay_measurement(data_bus_size); + + /* + * Read DQS Gating calibration + */ + + debug("Starting DQS gating calibration...\n"); + + mmdc_reset_read_data_fifos(); + + /* + * Start the automatic read DQS gating calibration process by asserting + * MPDGCTRL0[HW_DG_EN] and MPDGCTRL0[DG_CMP_CYC] and then poll + * MPDGCTRL0[HW_DG_EN]] until this bit clears to indicate completion. + * Also, ensure that MPDGCTRL0[HW_DG_ERR] is clear to indicate no errors + * were seen during calibration. Set bit 30: chooses option to wait 32 + * cycles instead of 16 before comparing read data + */ + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET, 30); + + /* Set bit 28 to start automatic read DQS gating calibration */ + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET, 28); + + /* + * Poll for completion + * MPDGCTRL0[HW_DG_EN] should be 0 + */ + while (reg32_read(MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET) & 0x10000000); + + /* + * Check to see if any errors were encountered during calibration + * (check MPDGCTRL0[HW_DG_ERR]) + * check both PHYs for x64 configuration, if x32, check only PHY0 + */ + if (data_bus_size == 0x2) { + if ((reg32_read(MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET) & 0x00001000) || + (reg32_read(MMDC_P1_IPS_BASE_ADDR + MPDGCTRL0_OFFSET) & 0x00001000)) + errorcount++; + } else { + if (reg32_read(MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET) & 0x00001000) + errorcount++; + } + + /* + * DQS gating absolute offset should be modified from reflecting + * (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80) + */ + modify_dg_result(MMDC_P0_IPS_BASE_ADDR + MPDGHWST0_OFFSET, + MMDC_P0_IPS_BASE_ADDR + MPDGHWST1_OFFSET, + MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET); + + modify_dg_result(MMDC_P0_IPS_BASE_ADDR + MPDGHWST2_OFFSET, + MMDC_P0_IPS_BASE_ADDR + MPDGHWST3_OFFSET, + MMDC_P0_IPS_BASE_ADDR + MPDGCTRL1_OFFSET); + + if (data_bus_size == 0x2) { + modify_dg_result(MMDC_P1_IPS_BASE_ADDR + MPDGHWST0_OFFSET, + MMDC_P1_IPS_BASE_ADDR + MPDGHWST1_OFFSET, + MMDC_P1_IPS_BASE_ADDR + MPDGCTRL0_OFFSET); + modify_dg_result(MMDC_P1_IPS_BASE_ADDR + MPDGHWST2_OFFSET, + MMDC_P1_IPS_BASE_ADDR + MPDGHWST3_OFFSET, + MMDC_P1_IPS_BASE_ADDR + MPDGCTRL1_OFFSET); + } + + debug("DQS gating calibration completed.\n"); + + /* + * Read delay Calibration + */ + + debug("Starting read calibration...\n"); + + mmdc_reset_read_data_fifos(); + + mmdc_precharge_all(cs0_enable, cs1_enable); + + /* + * Read delay-line calibration + * Start the automatic read calibration process by asserting MPRDDLHWCTL[ HW_RD_DL_EN] + */ + reg32_write(MMDC_P0_IPS_BASE_ADDR + MPRDDLHWCTL_OFFSET, 0x00000030); + + /* + * poll for completion + * MMDC indicates that the write data calibration had finished by setting + * MPRDDLHWCTL[HW_RD_DL_EN] = 0 + * Also, ensure that no error bits were set + */ + while (reg32_read(MMDC_P0_IPS_BASE_ADDR + MPRDDLHWCTL_OFFSET) & 0x00000010) ; + + /* check both PHYs for x64 configuration, if x32, check only PHY0 */ + if (data_bus_size == 0x2) { + if ((reg32_read(MMDC_P0_IPS_BASE_ADDR + MPRDDLHWCTL_OFFSET) & 0x0000000f) || + (reg32_read(MMDC_P1_IPS_BASE_ADDR + MPRDDLHWCTL_OFFSET) & 0x0000000f)) { + errorcount++; + } + } else { + if (reg32_read(MMDC_P0_IPS_BASE_ADDR + MPRDDLHWCTL_OFFSET) & 0x0000000f) { + errorcount++; + } + } + + debug("Read calibration completed\n"); + + /* + * Write delay Calibration + */ + + debug("Starting write calibration...\n"); + + mmdc_reset_read_data_fifos(); + + mmdc_precharge_all(cs0_enable, cs1_enable); + + /* + * Set the WR_DL_ABS_OFFSET# bits to their default values + * Both PHYs for x64 configuration, if x32, do only PHY0 + */ + reg32_write(MMDC_P0_IPS_BASE_ADDR + MPWRDLCTL_OFFSET, 0x40404040); + if (data_bus_size == 0x2) + reg32_write(MMDC_P1_IPS_BASE_ADDR + MPWRDLCTL_OFFSET, 0x40404040); + + mmdc_force_delay_measurement(data_bus_size); + + /* Start the automatic write calibration process by asserting MPWRDLHWCTL0[HW_WR_DL_EN] */ + reg32_write(MMDC_P0_IPS_BASE_ADDR + MPWRDLHWCTL_OFFSET, 0x00000030); + + /* + * poll for completion + * MMDC indicates that the write data calibration had finished by setting + * MPWRDLHWCTL[HW_WR_DL_EN] = 0 + * Also, ensure that no error bits were set + */ + while (reg32_read(MMDC_P0_IPS_BASE_ADDR + MPWRDLHWCTL_OFFSET) & 0x00000010) ; + + /* check both PHYs for x64 configuration, if x32, check only PHY0 */ + if (data_bus_size == 0x2) { + if ((reg32_read(MMDC_P0_IPS_BASE_ADDR + MPWRDLHWCTL_OFFSET) & 0x0000000f) || + (reg32_read(MMDC_P1_IPS_BASE_ADDR + MPWRDLHWCTL_OFFSET) & 0x0000000f)) { + errorcount++; + g_error_write_cal = 1; // set the g_error_write_cal + } + } else { + if (reg32_read(MMDC_P0_IPS_BASE_ADDR + MPWRDLHWCTL_OFFSET) & 0x0000000f) { + errorcount++; + g_error_write_cal = 1; // set the g_error_write_cal + } + } + + debug("Write calibration completed\n"); + + mmdc_reset_read_data_fifos(); + + debug("\n"); + + /* enable DDR logic power down timer */ + reg32_write(MMDC_P0_IPS_BASE_ADDR + MDPDC_OFFSET, + reg32_read(MMDC_P0_IPS_BASE_ADDR + MDPDC_OFFSET) | 0x00005500); + + /* enable Adopt power down timer */ + reg32_write(MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET, + reg32_read(MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET) & 0xfffffff7); + + /* restore MDMISC value (RALAT, WALAT) */ + reg32_write(MMDC_P1_IPS_BASE_ADDR + MDMISC_OFFSET, esdmisc_val); + + /* clear DQS pull ups */ + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0) & 0xffff0fff); + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1) & 0xffff0fff); + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2) & 0xffff0fff); + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3) & 0xffff0fff); + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4) & 0xffff0fff); + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5) & 0xffff0fff); + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6) & 0xffff0fff); + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7) & 0xffff0fff); + + /* re-enable SDE (chip selects) if they were set initially */ + if (cs1_enable_initial == 1) + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MDCTL_OFFSET, 30); /* set SDE_1 */ + + if (cs0_enable_initial == 1) + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MDCTL_OFFSET, 31); /* set SDE_0 */ + + /* re-enable to auto refresh */ + reg32_write(MMDC_P0_IPS_BASE_ADDR + MDREF_OFFSET, temp_ref); + + /* clear the MDSCR (including the con_req bit) */ + reg32_write(MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET, 0x0); /* CS0 */ + + /* poll to make sure the con_ack bit is clear */ + while (reg32_read(MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET) & 0x00004000) ; + + debug("MMDC registers updated from calibration \n"); + debug("\nRead DQS Gating calibration\n"); + debug("MPDGCTRL0 PHY0 (0x021b083c) = 0x%08X\n", reg32_read(0x021b083c)); + debug("MPDGCTRL1 PHY0 (0x021b0840) = 0x%08X\n", reg32_read(0x021b0840)); + debug("MPDGCTRL0 PHY1 (0x021b483c) = 0x%08X\n", reg32_read(0x021b483c)); + debug("MPDGCTRL1 PHY1 (0x021b4840) = 0x%08X\n", reg32_read(0x021b4840)); + debug("\nRead calibration\n"); + debug("MPRDDLCTL PHY0 (0x021b0848) = 0x%08X\n", reg32_read(0x021b0848)); + debug("MPRDDLCTL PHY1 (0x021b4848) = 0x%08X\n", reg32_read(0x021b4848)); + debug("\nWrite calibration\n"); + debug("MPWRDLCTL PHY0 (0x021b0850) = 0x%08X\n", reg32_read(0x021b0850)); + debug("MPWRDLCTL PHY1 (0x021b4850) = 0x%08X\n", reg32_read(0x021b4850)); + debug("\n"); + /* + * registers below are for debugging purposes + * these print out the upper and lower boundaries captured during read DQS gating calibration + */ + debug("Status registers, upper and lower bounds, for read DQS gating. \n"); + debug("MPDGHWST0 PHY0 (0x021b087c) = 0x%08X\n", reg32_read(0x021b087c)); + debug("MPDGHWST1 PHY0 (0x021b0880) = 0x%08X\n", reg32_read(0x021b0880)); + debug("MPDGHWST2 PHY0 (0x021b0884) = 0x%08X\n", reg32_read(0x021b0884)); + debug("MPDGHWST3 PHY0 (0x021b0888) = 0x%08X\n", reg32_read(0x021b0888)); + debug("MPDGHWST0 PHY1 (0x021b487c) = 0x%08X\n", reg32_read(0x021b487c)); + debug("MPDGHWST1 PHY1 (0x021b4880) = 0x%08X\n", reg32_read(0x021b4880)); + debug("MPDGHWST2 PHY1 (0x021b4884) = 0x%08X\n", reg32_read(0x021b4884)); + debug("MPDGHWST3 PHY1 (0x021b4888) = 0x%08X\n", reg32_read(0x021b4888)); + + return errorcount; +} + +#ifdef MMDC_SOFTWARE_CALIBRATION + +static void mmdc_set_dqs(u32 value) +{ + value |= value << 8 | value << 16 | value << 24; + + reg32_write(MMDC_P0_IPS_BASE_ADDR + MPRDDLCTL_OFFSET, value); + + if (data_bus_size == 0x2) + reg32_write(MMDC_P1_IPS_BASE_ADDR + MPRDDLCTL_OFFSET, value); +} + +static void mmdc_set_wr_delay(u32 value) +{ + value |= value << 8 | value << 16 | value << 24; + + reg32_write(MMDC_P0_IPS_BASE_ADDR + MPWRDLCTL_OFFSET, value); + + if (data_bus_size == 0x2) + reg32_write(MMDC_P1_IPS_BASE_ADDR + MPWRDLCTL_OFFSET, value); +} + +static void mmdc_issue_write_access(void __iomem *base) +{ + /* + * Issue a write access to the external DDR device by setting the bit SW_DUMMY_WR (bit 0) + * in the MPSWDAR0 and then poll this bit until it clears to indicate completion of the + * write access. + */ + + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET, 0); + + while (reg32_read(MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET) & 0x00000001); +} + +static void mmdc_issue_read_access(void __iomem *base) +{ + /* + * Issue a write access to the external DDR device by setting the bit SW_DUMMY_WR (bit 0) + * in the MPSWDAR0 and then poll this bit until it clears to indicate completion of the + * write access. + */ + + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET, 1); + + while (reg32_read(MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET) & 0x00000002); +} + +static int total_lower[2] = { 0x0, 0x0 }; +static int total_upper[2] = { 0xff, 0xff }; + +static int mmdc_is_valid(void __iomem *base, int delay, int rd) +{ + u32 val; + + if (rd) + mmdc_set_dqs(delay); + else + mmdc_set_wr_delay(delay); + + mmdc_force_delay_measurement(); + + mdelay(1); + + if (!rd) + mmdc_issue_write_access(base); + + mmdc_issue_read_access(base); + + val = readl(base + MPSWDAR_OFFSET); + + if ((val & 0x3c) == 0x3c) + return 1; + else + return 0; +#ifdef MMDC_SOFWARE_CALIB_COMPARE_RESULTS + if ((val & 0x3c) == 0x3c) { + if (lower < 0) + lower = i; + } + + if ((val & 0x3c) != 0x3c) { + if (lower > 0 && upper < 0) + upper = i; + } + + debug("0x%02x: compare: 0x%08x ", i, readl(MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET)); + for (j = 0; j < 8; j++) { + debug("0x%08x ", readl(MMDC_P0_IPS_BASE_ADDR + 0x898 + j * 4)); + } + debug("\n"); +#endif +} + +static void mmdc_sw_read_calib(int ch, u32 wr_value) +{ + int rd = 1; + void __iomem *base; + int i; + int lower = 0x0, upper = 0x7f; + + if (ch) + base = (void *)MMDC_P1_IPS_BASE_ADDR; + else + base = (void *)MMDC_P0_IPS_BASE_ADDR; + + /* 1. Precharge */ + mmdc_precharge_all(cs0_enable, cs1_enable); + + /* 2. Configure pre-defined value */ + reg32_write(MMDC_P0_IPS_BASE_ADDR + MPPDCMPR1_OFFSET, wr_value); + + /* 3. Issue write access */ + mmdc_issue_write_access(base); + + for (i = 0; i < 100; i++) { + if (mmdc_is_valid(base, 0x40, rd)) { + goto middle_passed; + } + } + + debug("ch: %d value: 0x%08x middle test failed\n", ch, wr_value); + return; + +middle_passed: + for (i = 0x40; i < 0x7f; i++) { + if (!mmdc_is_valid(base, i, rd)) { + upper = i; + break; + } + } + + for (i = 0; i < 100; i++) { + if (mmdc_is_valid(base, 0x40, rd)) { + goto go_on; + } + } + + debug("ch: %d value: 0x%08x middle test 1 failed\n", ch, wr_value); + return; + +go_on: + for (i = 0x40; i >= 0; i--) { + if (!mmdc_is_valid(base, i, rd)) { + lower = i; + break; + } + } + + if (lower > total_lower[ch]) + total_lower[ch] = lower; + + if (upper < total_upper[ch]) + total_upper[ch] = upper; + + debug("ch: %d value: 0x%08x lower: %-3d upper: %-3d\n", ch, wr_value, lower, upper); +} + +static void mmdc_sw_write_calib(int ch, u32 wr_value) +{ + int rd = 0; + void __iomem *base; + int i; + int lower = 0x0, upper = 0x7f; + + if (ch) + base = (void *)MMDC_P1_IPS_BASE_ADDR; + else + base = (void *)MMDC_P0_IPS_BASE_ADDR; + + /* 1. Precharge */ + mmdc_precharge_all(cs0_enable, cs1_enable); + + /* 2. Configure pre-defined value */ + reg32_write(MMDC_P0_IPS_BASE_ADDR + MPPDCMPR1_OFFSET, wr_value); + + /* 3. Issue write access */ + mmdc_issue_write_access(base); + + for (i = 0; i < 100; i++) { + if (mmdc_is_valid(base, 0x40, rd)) { + goto middle_passed; + } + } + + debug("ch: %d value: 0x%08x middle test failed\n", ch, wr_value); + return; + +middle_passed: + for (i = 0x40; i < 0x7f; i++) { + if (!mmdc_is_valid(base, i, rd)) { + upper = i; + break; + } + } + + for (i = 0; i < 100; i++) { + if (mmdc_is_valid(base, 0x40, rd)) { + goto go_on; + } + } + + debug("ch: %d value: 0x%08x middle test 1 failed\n", ch, wr_value); + return; + +go_on: + for (i = 0x40; i >= 0; i--) { + if (!mmdc_is_valid(base, i, rd)) { + lower = i; + break; + } + } + + if (lower > total_lower[ch]) + total_lower[ch] = lower; + + if (upper < total_upper[ch]) + total_upper[ch] = upper; + + debug("ch: %d value: 0x%08x lower: %-3d upper: %-3d\n", ch, wr_value, lower, upper); +} + +int mmdc_do_software_calibration(void) +{ + u32 s; + int ch; + + for (ch = 0; ch < 2; ch++) { + mmdc_sw_read_calib(ch, 0x00000055); + mmdc_sw_read_calib(ch, 0x00005500); + mmdc_sw_read_calib(ch, 0x00550000); + mmdc_sw_read_calib(ch, 0x55000000); + mmdc_sw_read_calib(ch, 0x00ffff00); + mmdc_sw_read_calib(ch, 0xff0000ff); + mmdc_sw_read_calib(ch, 0x55aaaa55); + mmdc_sw_read_calib(ch, 0xaa5555aa); + + for (s = 1; s; s <<= 1) + mmdc_sw_read_calib(ch, s); + } + + printk("ch0 total lower: %d upper: %d avg: 0x%02x\n", + total_lower[0], total_upper[0], + (total_lower[0] + total_upper[0]) / 2); + printk("ch1 total lower: %d upper: %d avg: 0x%02x\n", + total_lower[1], total_upper[1], + (total_lower[1] + total_upper[1]) / 2); + + mmdc_set_dqs(0x40); + + total_lower[0] = 0; + total_lower[1] = 0; + total_upper[0] = 0xff; + total_upper[1] = 0xff; + + for (ch = 0; ch < 2; ch++) { + mmdc_sw_write_calib(ch, 0x00000055); + mmdc_sw_write_calib(ch, 0x00005500); + mmdc_sw_write_calib(ch, 0x00550000); + mmdc_sw_write_calib(ch, 0x55000000); + mmdc_sw_write_calib(ch, 0x00ffff00); + mmdc_sw_write_calib(ch, 0xff0000ff); + mmdc_sw_write_calib(ch, 0x55aaaa55); + mmdc_sw_write_calib(ch, 0xaa5555aa); + + for (s = 1; s; s <<= 1) + mmdc_sw_write_calib(ch, s); + } + + printk("ch0 total lower: %d upper: %d avg: 0x%02x\n", + total_lower[0], total_upper[0], + (total_lower[0] + total_upper[0]) / 2); + printk("ch1 total lower: %d upper: %d avg: 0x%02x\n", + total_lower[1], total_upper[1], + (total_lower[1] + total_upper[1]) / 2); + + return 0; +} + +#endif /* MMDC_SOFTWARE_CALIBRATION */ diff --git a/arch/arm/mach-imx/include/mach/imx6-mmdc.h b/arch/arm/mach-imx/include/mach/imx6-mmdc.h new file mode 100644 index 0000000..4ad939e --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx6-mmdc.h @@ -0,0 +1,7 @@ +#ifndef __MACH_MMDC_H +#define __MACH_MMDC_H + +int mmdc_do_write_level_calibration(void); +int mmdc_do_dqs_calibration(void); + +#endif /* __MACH_MMDC_H */ -- 1.8.2.rc2 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] ARM i.MX6: Add mmdc calibration support 2013-03-08 12:08 ` [PATCH 1/3] ARM i.MX6: Add mmdc calibration support Sascha Hauer @ 2013-03-08 12:17 ` Alexander Shiyan 2013-03-08 14:00 ` Sascha Hauer 2013-03-08 12:46 ` Jean-Christophe PLAGNIOL-VILLARD 1 sibling, 1 reply; 14+ messages in thread From: Alexander Shiyan @ 2013-03-08 12:17 UTC (permalink / raw) To: Sascha Hauer; +Cc: barebox Hello. Only few questions inlined. > This adds support for the various DDR calibration functions in the > i.MX6 MMDC. ... > +static inline u32 reg32_read(u32 reg) > +{ > + return readl(reg); > +} > + > +static inline void reg32_write(u32 reg, u32 val) > +{ > + writel(val, reg); > +} > + What a reason to separate functions instead of readl/writel? > +static inline void reg32setbit(u32 reg, int bit) > +{ > + u32 val; > + > + val = readl(reg); > + val |= 1 << bit; > + writel(val, reg); > +} > + > +static inline void reg32clrbit(u32 reg, int bit) > +{ > + u32 val; > + > + val = readl(reg); > + val &= ~(1 << bit); > + writel(val, reg); > +} Maybe move this into asm-generic/io.h? Seems it can be reused by other users. Thanks. --- _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] ARM i.MX6: Add mmdc calibration support 2013-03-08 12:17 ` Alexander Shiyan @ 2013-03-08 14:00 ` Sascha Hauer 0 siblings, 0 replies; 14+ messages in thread From: Sascha Hauer @ 2013-03-08 14:00 UTC (permalink / raw) To: Alexander Shiyan; +Cc: barebox On Fri, Mar 08, 2013 at 04:17:22PM +0400, Alexander Shiyan wrote: > Hello. > > Only few questions inlined. > > > This adds support for the various DDR calibration functions in the > > i.MX6 MMDC. > ... > > +static inline u32 reg32_read(u32 reg) > > +{ > > + return readl(reg); > > +} > > + > > +static inline void reg32_write(u32 reg, u32 val) > > +{ > > + writel(val, reg); > > +} > > + > > What a reason to separate functions instead of readl/writel? The reason is that the original code had this and I was too lazy to swap the argument order, but I can fix this. > > > +static inline void reg32setbit(u32 reg, int bit) > > +{ > > + u32 val; > > + > > + val = readl(reg); > > + val |= 1 << bit; > > + writel(val, reg); > > +} > > + > > +static inline void reg32clrbit(u32 reg, int bit) > > +{ > > + u32 val; > > + > > + val = readl(reg); > > + val &= ~(1 << bit); > > + writel(val, reg); > > +} > > Maybe move this into asm-generic/io.h? Seems it can be reused by other > users. Dropped these. I'm not so convinced of helpers for these, at least not enough to write them myself. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] ARM i.MX6: Add mmdc calibration support 2013-03-08 12:08 ` [PATCH 1/3] ARM i.MX6: Add mmdc calibration support Sascha Hauer 2013-03-08 12:17 ` Alexander Shiyan @ 2013-03-08 12:46 ` Jean-Christophe PLAGNIOL-VILLARD 1 sibling, 0 replies; 14+ messages in thread From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-03-08 12:46 UTC (permalink / raw) To: Sascha Hauer; +Cc: barebox On 13:08 Fri 08 Mar , Sascha Hauer wrote: > This adds support for the various DDR calibration functions in the > i.MX6 MMDC. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > arch/arm/mach-imx/Makefile | 3 +- > arch/arm/mach-imx/imx6-mmdc.c | 839 +++++++++++++++++++++++++++++ > arch/arm/mach-imx/include/mach/imx6-mmdc.h | 7 + > 3 files changed, 848 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/mach-imx/imx6-mmdc.c > create mode 100644 arch/arm/mach-imx/include/mach/imx6-mmdc.h > > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile > index 4adf522..5f95ff4 100644 > --- a/arch/arm/mach-imx/Makefile > +++ b/arch/arm/mach-imx/Makefile > @@ -8,7 +8,8 @@ obj-$(CONFIG_ARCH_IMX35) += imx35.o iomux-v3.o clk-imx35.o > obj-$(CONFIG_ARCH_IMX51) += imx51.o iomux-v3.o imx5.o clk-imx5.o > obj-$(CONFIG_ARCH_IMX53) += imx53.o iomux-v3.o imx5.o clk-imx5.o esdctl-v4.o > pbl-$(CONFIG_ARCH_IMX53) += imx53.o imx5.o esdctl-v4.o > -obj-$(CONFIG_ARCH_IMX6) += imx6.o iomux-v3.o usb-imx6.o clk-imx6.o > +obj-$(CONFIG_ARCH_IMX6) += imx6.o iomux-v3.o usb-imx6.o clk-imx6.o imx6-mmdc.o > +pbl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o only for the pbl? or use lwl-y? > obj-$(CONFIG_IMX_IIM) += iim.o > obj-$(CONFIG_NAND_IMX) += nand.o > lwl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o > diff --git a/arch/arm/mach-imx/imx6-mmdc.c b/arch/arm/mach-imx/imx6-mmdc.c > new file mode 100644 > index 0000000..66136d3 > --- /dev/null > +++ b/arch/arm/mach-imx/imx6-mmdc.c > @@ -0,0 +1,839 @@ > +#include <common.h> > +#include <io.h> > +#include <mach/imx6-regs.h> > +#include <mach/imx6-mmdc.h> > + > +#define MMDC_P0_IPS_BASE_ADDR 0x021b0000 > +#define MMDC_P1_IPS_BASE_ADDR 0x021b4000 > + > +#define MDCTL_OFFSET 0x000 > +#define MDPDC_OFFSET 0x004 > +#define MDSCR_OFFSET 0x01c > +#define MDMISC_OFFSET 0x018 > +#define MDREF_OFFSET 0x020 > +#define MAPSR_OFFSET 0x404 > +#define MPZQHWCTRL_OFFSET 0x800 > +#define MPWLGCR_OFFSET 0x808 > +#define MPWLDECTRL0_OFFSET 0x80c > +#define MPWLDECTRL1_OFFSET 0x810 > +#define MPPDCMPR1_OFFSET 0x88c > +#define MPSWDAR_OFFSET 0x894 > +#define MPRDDLCTL_OFFSET 0x848 > +#define MPMUR_OFFSET 0x8b8 > +#define MPDGCTRL0_OFFSET 0x83c > +#define MPDGHWST0_OFFSET 0x87c > +#define MPDGHWST1_OFFSET 0x880 > +#define MPDGHWST2_OFFSET 0x884 > +#define MPDGHWST3_OFFSET 0x888 > +#define MPDGCTRL1_OFFSET 0x840 > +#define MPRDDLHWCTL_OFFSET 0x860 > +#define MPWRDLCTL_OFFSET 0x850 > +#define MPWRDLHWCTL_OFFSET 0x864 > + > +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 (MX6_IOMUXC_BASE_ADDR + 0x5a8) > +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 (MX6_IOMUXC_BASE_ADDR + 0x5b0) > +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 (MX6_IOMUXC_BASE_ADDR + 0x524) > +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 (MX6_IOMUXC_BASE_ADDR + 0x51c) > +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 (MX6_IOMUXC_BASE_ADDR + 0x518) > +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 (MX6_IOMUXC_BASE_ADDR + 0x50c) > +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 (MX6_IOMUXC_BASE_ADDR + 0x5b8) > +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 (MX6_IOMUXC_BASE_ADDR + 0x5c0) > + > +static inline u32 reg32_read(u32 reg) > +{ > + return readl(reg); > +} > + > +static inline void reg32_write(u32 reg, u32 val) > +{ > + writel(val, reg); > +} what is the diffrence? > + > +static inline void reg32setbit(u32 reg, int bit) > +{ > + u32 val; > + > + val = readl(reg); > + val |= 1 << bit; > + writel(val, reg); > +} > + > +static inline void reg32clrbit(u32 reg, int bit) > +{ > + u32 val; > + > + val = readl(reg); > + val &= ~(1 << bit); > + writel(val, reg); > +} it will be good to have a generic helper > + > +int mmdc_do_write_level_calibration(void) > +{ > + u32 esdmisc_val, zq_val; > + int errorcount = 0; > + u32 val; > + u32 ddr_mr1 = 0x4; > + > + /* disable DDR logic power down timer */ > + val = readl((MMDC_P0_IPS_BASE_ADDR + MDPDC_OFFSET)); > + val &= 0xffff00ff; > + writel(val, (MMDC_P0_IPS_BASE_ADDR + MDPDC_OFFSET)), > + > + /* disable Adopt power down timer */ > + val = readl((MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET)); > + val |= 0x1; > + writel(val, (MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET)); reg32setbit here > + > + debug("Start write leveling calibration \n"); pr_debug can we drop the magic value everywhere? > + > + /* > + * disable auto refresh and ZQ calibration > + * before proceeding with Write Leveling calibration > + */ > + esdmisc_val = readl(MMDC_P0_IPS_BASE_ADDR + MDREF_OFFSET); > + writel(0x0000C000, (MMDC_P0_IPS_BASE_ADDR + MDREF_OFFSET)); > + zq_val = readl(MMDC_P0_IPS_BASE_ADDR + MPZQHWCTRL_OFFSET); > + writel(zq_val & ~(0x3), (MMDC_P0_IPS_BASE_ADDR + MPZQHWCTRL_OFFSET)); > + > + /* > + * Configure the external DDR device to enter write leveling mode > + * through Load Mode Register command > + * Register setting: > + * Bits[31:16] MR1 value (0x0080 write leveling enable) > + * Bit[9] set WL_EN to enable MMDC DQS output > + * Bits[6:4] set CMD bits for Load Mode Register programming > + * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming > + */ > + writel(0x00808231, MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET); > + > + /* Activate automatic calibration by setting MPWLGCR[HW_WL_EN] */ > + writel(0x00000001, MMDC_P0_IPS_BASE_ADDR + MPWLGCR_OFFSET); > + > + /* Upon completion of this process the MMDC de-asserts the MPWLGCR[HW_WL_EN] */ > + while (readl(MMDC_P0_IPS_BASE_ADDR + MPWLGCR_OFFSET) & 0x00000001); > + > + /* check for any errors: check both PHYs for x64 configuration, if x32, check only PHY0 */ > + if ((readl(MMDC_P0_IPS_BASE_ADDR + MPWLGCR_OFFSET) & 0x00000F00) || > + (readl(MMDC_P1_IPS_BASE_ADDR + MPWLGCR_OFFSET) & 0x00000F00)) { > + errorcount++; > + } > + > + debug("Write leveling calibration completed\n"); > + > + /* > + * User should issue MRS command to exit write leveling mode > + * through Load Mode Register command > + * Register setting: > + * Bits[31:16] MR1 value "ddr_mr1" value from initialization > + * Bit[9] clear WL_EN to disable MMDC DQS output > + * Bits[6:4] set CMD bits for Load Mode Register programming > + * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming > + */ > + writel(((ddr_mr1 << 16)+0x8031), MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET); > + > + /* re-enable to auto refresh and zq cal */ > + writel(esdmisc_val, (MMDC_P0_IPS_BASE_ADDR + MDREF_OFFSET)); > + writel(zq_val, (MMDC_P0_IPS_BASE_ADDR + MPZQHWCTRL_OFFSET)); > + > + debug("MMDC_MPWLDECTRL0 after write level cal: 0x%08X\n", > + readl(MMDC_P0_IPS_BASE_ADDR + MPWLDECTRL0_OFFSET)); > + debug("MMDC_MPWLDECTRL1 after write level cal: 0x%08X\n", > + readl(MMDC_P0_IPS_BASE_ADDR + MPWLDECTRL1_OFFSET)); > + debug("MMDC_MPWLDECTRL0 after write level cal: 0x%08X\n", > + readl(MMDC_P1_IPS_BASE_ADDR + MPWLDECTRL0_OFFSET)); > + debug("MMDC_MPWLDECTRL1 after write level cal: 0x%08X\n", > + readl(MMDC_P1_IPS_BASE_ADDR + MPWLDECTRL1_OFFSET)); > + > + /* enable DDR logic power down timer */ > + val = readl((MMDC_P0_IPS_BASE_ADDR + MDPDC_OFFSET)); > + val |= 0x00005500; > + writel(val, (MMDC_P0_IPS_BASE_ADDR + MDPDC_OFFSET)); > + > + /* enable Adopt power down timer: */ > + val = readl(MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET); > + val &= 0xfffffff7; > + writel(val, (MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET)); > + > + /* clear CON_REQ */ > + writel(0, (MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET)); > + > + return 0; > +} > + > +static void modify_dg_result(int reg_st0, int reg_st1, int reg_ctrl) > +{ > + u32 dg_tmp_val, dg_dl_abs_offset, dg_hc_del, val_ctrl; > + > + /* > + * DQS gating absolute offset should be modified from reflecting (HW_DG_LOWx + HW_DG_UPx)/2 > + * to reflecting (HW_DG_UPx - 0x80) > + */ > + > + val_ctrl = reg32_read(reg_ctrl); > + val_ctrl &= 0xf0000000; > + > + dg_tmp_val = ((reg32_read(reg_st0) & 0x07ff0000) >> 16) - 0xc0; > + dg_dl_abs_offset = dg_tmp_val & 0x7f; > + dg_hc_del = (dg_tmp_val & 0x780) << 1; > + > + val_ctrl |= dg_dl_abs_offset + dg_hc_del; > + > + dg_tmp_val = ((reg32_read(reg_st1) & 0x07ff0000) >> 16) - 0xc0; > + dg_dl_abs_offset = dg_tmp_val & 0x7f; > + dg_hc_del = (dg_tmp_val & 0x780) << 1; > + > + val_ctrl |= (dg_dl_abs_offset + dg_hc_del) << 16; > + > + reg32_write(reg_ctrl, val_ctrl); > +} > + > +static void mmdc_precharge_all(int cs0_enable, int cs1_enable) > +{ > + /* > + * Issue the Precharge-All command to the DDR device for both chip selects > + * Note, CON_REQ bit should also remain set > + * If only using one chip select, then precharge only the desired chip select > + */ > + if (cs0_enable) > + reg32_write((MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET), 0x04008050); > + if (cs1_enable) > + reg32_write((MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET), 0x04008058); > +} > + > +static void mmdc_force_delay_measurement(int data_bus_size) > +{ > + reg32_write(MMDC_P0_IPS_BASE_ADDR + MPMUR_OFFSET, 0x800); > + > + if (data_bus_size == 0x2) > + reg32_write(MMDC_P1_IPS_BASE_ADDR + MPMUR_OFFSET, 0x800); > +} > + > +static void mmdc_reset_read_data_fifos(void) > +{ > + /* > + * Reset the read data FIFOs (two resets); only need to issue reset to PHY0 since in x64 > + * mode, the reset will also go to PHY1 > + * read data FIFOs reset1 > + */ > + reg32_write((MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET), > + reg32_read((MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET)) | 0x80000000); > + > + while (reg32_read((MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET)) & 0x80000000); > + > + /* read data FIFOs reset2 */ > + reg32_write((MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET), > + reg32_read((MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET)) | 0x80000000); > + > + while (reg32_read((MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET)) & 0x80000000); > +} > + > +int mmdc_do_dqs_calibration(void) > +{ > + u32 esdmisc_val; > + int g_error_write_cal; > + int temp_ref; > + int cs0_enable_initial; > + int cs1_enable_initial; > + int PDDWord = 0x00ffff00; > + int errorcount = 0; > + int cs0_enable; > + int cs1_enable; > + int data_bus_size; > + > + /* check to see which chip selects are enabled */ > + cs0_enable_initial = (reg32_read(MMDC_P0_IPS_BASE_ADDR + MDCTL_OFFSET) & 0x80000000) >> 31; > + cs1_enable_initial = (reg32_read(MMDC_P0_IPS_BASE_ADDR + MDCTL_OFFSET) & 0x40000000) >> 30; > + > + /* disable DDR logic power down timer */ > + reg32_write(MMDC_P0_IPS_BASE_ADDR + MDPDC_OFFSET, > + reg32_read((MMDC_P0_IPS_BASE_ADDR + MDPDC_OFFSET)) & 0xffff00ff); > + > + /* disable Adopt power down timer */ > + reg32_write(MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET, > + reg32_read((MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET)) | 0x1); > + > + /* set DQS pull ups */ > + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0) | 0x7000); > + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1) | 0x7000); > + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2) | 0x7000); > + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3) | 0x7000); > + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4) | 0x7000); > + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5) | 0x7000); > + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6) | 0x7000); > + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7) | 0x7000); > + > + esdmisc_val = reg32_read(MMDC_P0_IPS_BASE_ADDR + MDMISC_OFFSET); > + > + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MDMISC_OFFSET, 6); /* set RALAT to max */ > + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MDMISC_OFFSET, 7); > + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MDMISC_OFFSET, 8); > + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MDMISC_OFFSET, 16); /* set WALAT to max */ > + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MDMISC_OFFSET, 17); > + > + /* > + * disable auto refresh > + * before proceeding with calibration > + */ > + temp_ref = reg32_read(MMDC_P0_IPS_BASE_ADDR + MDREF_OFFSET); > + reg32_write(MMDC_P0_IPS_BASE_ADDR + MDREF_OFFSET, 0x0000C000); > + > + /* > + * per the ref manual, issue one refresh cycle MDSCR[CMD]= 0x2, > + * this also sets the CON_REQ bit. > + */ > + if (cs0_enable_initial) > + reg32_write(MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET, 0x00008020); > + if (cs1_enable_initial) > + reg32_write(MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET, 0x00008028); > + > + /* poll to make sure the con_ack bit was asserted */ > + while (!(reg32_read(MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET) & 0x00004000)) ; > + > + /* > + * check MDMISC register CALIB_PER_CS to see which CS calibration is > + * targeted to (under normal cases, it should be cleared as this is the > + * default value, indicating calibration is directed to CS0). Disable > + * the other chip select not being target for calibration to avoid any > + * potential issues This will get re-enabled at end of calibration. > + */ > + if ((reg32_read(MMDC_P0_IPS_BASE_ADDR + MDMISC_OFFSET) & 0x00100000) == 0) > + reg32clrbit(MMDC_P0_IPS_BASE_ADDR + MDCTL_OFFSET, 30); /* clear SDE_1 */ > + else > + reg32clrbit(MMDC_P0_IPS_BASE_ADDR + MDCTL_OFFSET, 31); /* clear SDE_0 */ > + > + /* > + * check to see which chip selects are now enabled for the remainder > + * of the calibration. > + */ > + cs0_enable = (reg32_read(MMDC_P0_IPS_BASE_ADDR + MDCTL_OFFSET) & 0x80000000) >> 31; > + cs1_enable = (reg32_read(MMDC_P0_IPS_BASE_ADDR + MDCTL_OFFSET) & 0x40000000) >> 30; > + > + /* check to see what is the data bus size */ > + data_bus_size = (reg32_read(MMDC_P0_IPS_BASE_ADDR + MDCTL_OFFSET) & 0x30000) >> 16; > + > + mmdc_precharge_all(cs0_enable, cs1_enable); > + > + /* Write the pre-defined value into MPPDCMPR1 */ > + reg32_write((MMDC_P0_IPS_BASE_ADDR + MPPDCMPR1_OFFSET), PDDWord); > + > + /* > + * Issue a write access to the external DDR device by setting the bit SW_DUMMY_WR (bit 0) > + * in the MPSWDAR0 and then poll this bit until it clears to indicate completion of the > + * write access. > + */ > + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET, 0); > + > + while (reg32_read(MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET) & 0x00000001); > + > + /* > + * Set the RD_DL_ABS_OFFSET# bits to their default values (will be calibrated later in > + * the read delay-line calibration) > + * Both PHYs for x64 configuration, if x32, do only PHY0 > + */ > + reg32_write(MMDC_P0_IPS_BASE_ADDR + MPRDDLCTL_OFFSET, 0x40404040); > + if (data_bus_size == 0x2) > + reg32_write(MMDC_P1_IPS_BASE_ADDR + MPRDDLCTL_OFFSET, 0x40404040); > + > + /* Force a measurement, for previous delay setup to take effect */ > + mmdc_force_delay_measurement(data_bus_size); > + > + /* > + * Read DQS Gating calibration > + */ > + > + debug("Starting DQS gating calibration...\n"); > + > + mmdc_reset_read_data_fifos(); > + > + /* > + * Start the automatic read DQS gating calibration process by asserting > + * MPDGCTRL0[HW_DG_EN] and MPDGCTRL0[DG_CMP_CYC] and then poll > + * MPDGCTRL0[HW_DG_EN]] until this bit clears to indicate completion. > + * Also, ensure that MPDGCTRL0[HW_DG_ERR] is clear to indicate no errors > + * were seen during calibration. Set bit 30: chooses option to wait 32 > + * cycles instead of 16 before comparing read data > + */ > + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET, 30); > + > + /* Set bit 28 to start automatic read DQS gating calibration */ > + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET, 28); > + > + /* > + * Poll for completion > + * MPDGCTRL0[HW_DG_EN] should be 0 > + */ > + while (reg32_read(MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET) & 0x10000000); > + > + /* > + * Check to see if any errors were encountered during calibration > + * (check MPDGCTRL0[HW_DG_ERR]) > + * check both PHYs for x64 configuration, if x32, check only PHY0 > + */ > + if (data_bus_size == 0x2) { > + if ((reg32_read(MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET) & 0x00001000) || > + (reg32_read(MMDC_P1_IPS_BASE_ADDR + MPDGCTRL0_OFFSET) & 0x00001000)) > + errorcount++; > + } else { > + if (reg32_read(MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET) & 0x00001000) > + errorcount++; > + } > + > + /* > + * DQS gating absolute offset should be modified from reflecting > + * (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80) > + */ > + modify_dg_result(MMDC_P0_IPS_BASE_ADDR + MPDGHWST0_OFFSET, > + MMDC_P0_IPS_BASE_ADDR + MPDGHWST1_OFFSET, > + MMDC_P0_IPS_BASE_ADDR + MPDGCTRL0_OFFSET); > + > + modify_dg_result(MMDC_P0_IPS_BASE_ADDR + MPDGHWST2_OFFSET, > + MMDC_P0_IPS_BASE_ADDR + MPDGHWST3_OFFSET, > + MMDC_P0_IPS_BASE_ADDR + MPDGCTRL1_OFFSET); > + > + if (data_bus_size == 0x2) { > + modify_dg_result(MMDC_P1_IPS_BASE_ADDR + MPDGHWST0_OFFSET, > + MMDC_P1_IPS_BASE_ADDR + MPDGHWST1_OFFSET, > + MMDC_P1_IPS_BASE_ADDR + MPDGCTRL0_OFFSET); > + modify_dg_result(MMDC_P1_IPS_BASE_ADDR + MPDGHWST2_OFFSET, > + MMDC_P1_IPS_BASE_ADDR + MPDGHWST3_OFFSET, > + MMDC_P1_IPS_BASE_ADDR + MPDGCTRL1_OFFSET); > + } > + > + debug("DQS gating calibration completed.\n"); > + > + /* > + * Read delay Calibration > + */ > + > + debug("Starting read calibration...\n"); > + > + mmdc_reset_read_data_fifos(); > + > + mmdc_precharge_all(cs0_enable, cs1_enable); > + > + /* > + * Read delay-line calibration > + * Start the automatic read calibration process by asserting MPRDDLHWCTL[ HW_RD_DL_EN] > + */ > + reg32_write(MMDC_P0_IPS_BASE_ADDR + MPRDDLHWCTL_OFFSET, 0x00000030); > + > + /* > + * poll for completion > + * MMDC indicates that the write data calibration had finished by setting > + * MPRDDLHWCTL[HW_RD_DL_EN] = 0 > + * Also, ensure that no error bits were set > + */ > + while (reg32_read(MMDC_P0_IPS_BASE_ADDR + MPRDDLHWCTL_OFFSET) & 0x00000010) ; > + > + /* check both PHYs for x64 configuration, if x32, check only PHY0 */ > + if (data_bus_size == 0x2) { > + if ((reg32_read(MMDC_P0_IPS_BASE_ADDR + MPRDDLHWCTL_OFFSET) & 0x0000000f) || > + (reg32_read(MMDC_P1_IPS_BASE_ADDR + MPRDDLHWCTL_OFFSET) & 0x0000000f)) { > + errorcount++; > + } > + } else { > + if (reg32_read(MMDC_P0_IPS_BASE_ADDR + MPRDDLHWCTL_OFFSET) & 0x0000000f) { > + errorcount++; > + } > + } > + > + debug("Read calibration completed\n"); > + > + /* > + * Write delay Calibration > + */ > + > + debug("Starting write calibration...\n"); > + > + mmdc_reset_read_data_fifos(); > + > + mmdc_precharge_all(cs0_enable, cs1_enable); > + > + /* > + * Set the WR_DL_ABS_OFFSET# bits to their default values > + * Both PHYs for x64 configuration, if x32, do only PHY0 > + */ > + reg32_write(MMDC_P0_IPS_BASE_ADDR + MPWRDLCTL_OFFSET, 0x40404040); > + if (data_bus_size == 0x2) > + reg32_write(MMDC_P1_IPS_BASE_ADDR + MPWRDLCTL_OFFSET, 0x40404040); > + > + mmdc_force_delay_measurement(data_bus_size); > + > + /* Start the automatic write calibration process by asserting MPWRDLHWCTL0[HW_WR_DL_EN] */ > + reg32_write(MMDC_P0_IPS_BASE_ADDR + MPWRDLHWCTL_OFFSET, 0x00000030); > + > + /* > + * poll for completion > + * MMDC indicates that the write data calibration had finished by setting > + * MPWRDLHWCTL[HW_WR_DL_EN] = 0 > + * Also, ensure that no error bits were set > + */ > + while (reg32_read(MMDC_P0_IPS_BASE_ADDR + MPWRDLHWCTL_OFFSET) & 0x00000010) ; > + > + /* check both PHYs for x64 configuration, if x32, check only PHY0 */ > + if (data_bus_size == 0x2) { > + if ((reg32_read(MMDC_P0_IPS_BASE_ADDR + MPWRDLHWCTL_OFFSET) & 0x0000000f) || > + (reg32_read(MMDC_P1_IPS_BASE_ADDR + MPWRDLHWCTL_OFFSET) & 0x0000000f)) { > + errorcount++; > + g_error_write_cal = 1; // set the g_error_write_cal > + } > + } else { > + if (reg32_read(MMDC_P0_IPS_BASE_ADDR + MPWRDLHWCTL_OFFSET) & 0x0000000f) { > + errorcount++; > + g_error_write_cal = 1; // set the g_error_write_cal > + } > + } > + > + debug("Write calibration completed\n"); > + > + mmdc_reset_read_data_fifos(); > + > + debug("\n"); > + > + /* enable DDR logic power down timer */ > + reg32_write(MMDC_P0_IPS_BASE_ADDR + MDPDC_OFFSET, > + reg32_read(MMDC_P0_IPS_BASE_ADDR + MDPDC_OFFSET) | 0x00005500); > + > + /* enable Adopt power down timer */ > + reg32_write(MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET, > + reg32_read(MMDC_P0_IPS_BASE_ADDR + MAPSR_OFFSET) & 0xfffffff7); > + > + /* restore MDMISC value (RALAT, WALAT) */ > + reg32_write(MMDC_P1_IPS_BASE_ADDR + MDMISC_OFFSET, esdmisc_val); > + > + /* clear DQS pull ups */ > + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0) & 0xffff0fff); > + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1) & 0xffff0fff); > + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2) & 0xffff0fff); > + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3) & 0xffff0fff); > + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4) & 0xffff0fff); > + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5) & 0xffff0fff); > + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6) & 0xffff0fff); > + reg32_write(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7, reg32_read(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7) & 0xffff0fff); > + > + /* re-enable SDE (chip selects) if they were set initially */ > + if (cs1_enable_initial == 1) > + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MDCTL_OFFSET, 30); /* set SDE_1 */ > + > + if (cs0_enable_initial == 1) > + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MDCTL_OFFSET, 31); /* set SDE_0 */ > + > + /* re-enable to auto refresh */ > + reg32_write(MMDC_P0_IPS_BASE_ADDR + MDREF_OFFSET, temp_ref); > + > + /* clear the MDSCR (including the con_req bit) */ > + reg32_write(MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET, 0x0); /* CS0 */ > + > + /* poll to make sure the con_ack bit is clear */ > + while (reg32_read(MMDC_P0_IPS_BASE_ADDR + MDSCR_OFFSET) & 0x00004000) ; > + > + debug("MMDC registers updated from calibration \n"); > + debug("\nRead DQS Gating calibration\n"); > + debug("MPDGCTRL0 PHY0 (0x021b083c) = 0x%08X\n", reg32_read(0x021b083c)); > + debug("MPDGCTRL1 PHY0 (0x021b0840) = 0x%08X\n", reg32_read(0x021b0840)); > + debug("MPDGCTRL0 PHY1 (0x021b483c) = 0x%08X\n", reg32_read(0x021b483c)); > + debug("MPDGCTRL1 PHY1 (0x021b4840) = 0x%08X\n", reg32_read(0x021b4840)); > + debug("\nRead calibration\n"); > + debug("MPRDDLCTL PHY0 (0x021b0848) = 0x%08X\n", reg32_read(0x021b0848)); > + debug("MPRDDLCTL PHY1 (0x021b4848) = 0x%08X\n", reg32_read(0x021b4848)); > + debug("\nWrite calibration\n"); > + debug("MPWRDLCTL PHY0 (0x021b0850) = 0x%08X\n", reg32_read(0x021b0850)); > + debug("MPWRDLCTL PHY1 (0x021b4850) = 0x%08X\n", reg32_read(0x021b4850)); > + debug("\n"); > + /* > + * registers below are for debugging purposes > + * these print out the upper and lower boundaries captured during read DQS gating calibration > + */ > + debug("Status registers, upper and lower bounds, for read DQS gating. \n"); > + debug("MPDGHWST0 PHY0 (0x021b087c) = 0x%08X\n", reg32_read(0x021b087c)); > + debug("MPDGHWST1 PHY0 (0x021b0880) = 0x%08X\n", reg32_read(0x021b0880)); > + debug("MPDGHWST2 PHY0 (0x021b0884) = 0x%08X\n", reg32_read(0x021b0884)); > + debug("MPDGHWST3 PHY0 (0x021b0888) = 0x%08X\n", reg32_read(0x021b0888)); > + debug("MPDGHWST0 PHY1 (0x021b487c) = 0x%08X\n", reg32_read(0x021b487c)); > + debug("MPDGHWST1 PHY1 (0x021b4880) = 0x%08X\n", reg32_read(0x021b4880)); > + debug("MPDGHWST2 PHY1 (0x021b4884) = 0x%08X\n", reg32_read(0x021b4884)); > + debug("MPDGHWST3 PHY1 (0x021b4888) = 0x%08X\n", reg32_read(0x021b4888)); > + > + return errorcount; > +} > + > +#ifdef MMDC_SOFTWARE_CALIBRATION > + > +static void mmdc_set_dqs(u32 value) > +{ > + value |= value << 8 | value << 16 | value << 24; > + > + reg32_write(MMDC_P0_IPS_BASE_ADDR + MPRDDLCTL_OFFSET, value); > + > + if (data_bus_size == 0x2) > + reg32_write(MMDC_P1_IPS_BASE_ADDR + MPRDDLCTL_OFFSET, value); > +} > + > +static void mmdc_set_wr_delay(u32 value) > +{ > + value |= value << 8 | value << 16 | value << 24; > + > + reg32_write(MMDC_P0_IPS_BASE_ADDR + MPWRDLCTL_OFFSET, value); > + > + if (data_bus_size == 0x2) > + reg32_write(MMDC_P1_IPS_BASE_ADDR + MPWRDLCTL_OFFSET, value); > +} > + > +static void mmdc_issue_write_access(void __iomem *base) > +{ > + /* > + * Issue a write access to the external DDR device by setting the bit SW_DUMMY_WR (bit 0) > + * in the MPSWDAR0 and then poll this bit until it clears to indicate completion of the > + * write access. > + */ > + > + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET, 0); > + > + while (reg32_read(MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET) & 0x00000001); > +} > + > +static void mmdc_issue_read_access(void __iomem *base) > +{ > + /* > + * Issue a write access to the external DDR device by setting the bit SW_DUMMY_WR (bit 0) > + * in the MPSWDAR0 and then poll this bit until it clears to indicate completion of the > + * write access. > + */ > + > + reg32setbit(MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET, 1); > + > + while (reg32_read(MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET) & 0x00000002); > +} > + > +static int total_lower[2] = { 0x0, 0x0 }; > +static int total_upper[2] = { 0xff, 0xff }; > + > +static int mmdc_is_valid(void __iomem *base, int delay, int rd) > +{ > + u32 val; > + > + if (rd) > + mmdc_set_dqs(delay); > + else > + mmdc_set_wr_delay(delay); > + > + mmdc_force_delay_measurement(); > + > + mdelay(1); > + > + if (!rd) > + mmdc_issue_write_access(base); > + > + mmdc_issue_read_access(base); > + > + val = readl(base + MPSWDAR_OFFSET); > + > + if ((val & 0x3c) == 0x3c) > + return 1; > + else > + return 0; > +#ifdef MMDC_SOFWARE_CALIB_COMPARE_RESULTS > + if ((val & 0x3c) == 0x3c) { > + if (lower < 0) > + lower = i; > + } > + > + if ((val & 0x3c) != 0x3c) { > + if (lower > 0 && upper < 0) > + upper = i; > + } > + > + debug("0x%02x: compare: 0x%08x ", i, readl(MMDC_P0_IPS_BASE_ADDR + MPSWDAR_OFFSET)); > + for (j = 0; j < 8; j++) { > + debug("0x%08x ", readl(MMDC_P0_IPS_BASE_ADDR + 0x898 + j * 4)); > + } > + debug("\n"); > +#endif > +} > + > +static void mmdc_sw_read_calib(int ch, u32 wr_value) > +{ > + int rd = 1; > + void __iomem *base; > + int i; > + int lower = 0x0, upper = 0x7f; > + > + if (ch) > + base = (void *)MMDC_P1_IPS_BASE_ADDR; > + else > + base = (void *)MMDC_P0_IPS_BASE_ADDR; > + > + /* 1. Precharge */ > + mmdc_precharge_all(cs0_enable, cs1_enable); > + > + /* 2. Configure pre-defined value */ > + reg32_write(MMDC_P0_IPS_BASE_ADDR + MPPDCMPR1_OFFSET, wr_value); > + > + /* 3. Issue write access */ > + mmdc_issue_write_access(base); > + > + for (i = 0; i < 100; i++) { > + if (mmdc_is_valid(base, 0x40, rd)) { > + goto middle_passed; > + } > + } > + > + debug("ch: %d value: 0x%08x middle test failed\n", ch, wr_value); > + return; > + > +middle_passed: > + for (i = 0x40; i < 0x7f; i++) { > + if (!mmdc_is_valid(base, i, rd)) { > + upper = i; > + break; > + } > + } > + > + for (i = 0; i < 100; i++) { > + if (mmdc_is_valid(base, 0x40, rd)) { > + goto go_on; > + } > + } > + > + debug("ch: %d value: 0x%08x middle test 1 failed\n", ch, wr_value); > + return; > + > +go_on: > + for (i = 0x40; i >= 0; i--) { > + if (!mmdc_is_valid(base, i, rd)) { > + lower = i; > + break; > + } > + } > + > + if (lower > total_lower[ch]) > + total_lower[ch] = lower; > + > + if (upper < total_upper[ch]) > + total_upper[ch] = upper; > + > + debug("ch: %d value: 0x%08x lower: %-3d upper: %-3d\n", ch, wr_value, lower, upper); > +} > + > +static void mmdc_sw_write_calib(int ch, u32 wr_value) > +{ > + int rd = 0; > + void __iomem *base; > + int i; > + int lower = 0x0, upper = 0x7f; > + > + if (ch) > + base = (void *)MMDC_P1_IPS_BASE_ADDR; > + else > + base = (void *)MMDC_P0_IPS_BASE_ADDR; > + > + /* 1. Precharge */ > + mmdc_precharge_all(cs0_enable, cs1_enable); > + > + /* 2. Configure pre-defined value */ > + reg32_write(MMDC_P0_IPS_BASE_ADDR + MPPDCMPR1_OFFSET, wr_value); > + > + /* 3. Issue write access */ > + mmdc_issue_write_access(base); > + > + for (i = 0; i < 100; i++) { > + if (mmdc_is_valid(base, 0x40, rd)) { > + goto middle_passed; > + } > + } > + > + debug("ch: %d value: 0x%08x middle test failed\n", ch, wr_value); > + return; > + > +middle_passed: > + for (i = 0x40; i < 0x7f; i++) { > + if (!mmdc_is_valid(base, i, rd)) { > + upper = i; > + break; > + } > + } > + > + for (i = 0; i < 100; i++) { > + if (mmdc_is_valid(base, 0x40, rd)) { > + goto go_on; > + } > + } > + > + debug("ch: %d value: 0x%08x middle test 1 failed\n", ch, wr_value); > + return; > + > +go_on: > + for (i = 0x40; i >= 0; i--) { > + if (!mmdc_is_valid(base, i, rd)) { > + lower = i; > + break; > + } > + } > + > + if (lower > total_lower[ch]) > + total_lower[ch] = lower; > + > + if (upper < total_upper[ch]) > + total_upper[ch] = upper; > + > + debug("ch: %d value: 0x%08x lower: %-3d upper: %-3d\n", ch, wr_value, lower, upper); > +} > + > +int mmdc_do_software_calibration(void) > +{ > + u32 s; > + int ch; > + > + for (ch = 0; ch < 2; ch++) { > + mmdc_sw_read_calib(ch, 0x00000055); > + mmdc_sw_read_calib(ch, 0x00005500); > + mmdc_sw_read_calib(ch, 0x00550000); > + mmdc_sw_read_calib(ch, 0x55000000); > + mmdc_sw_read_calib(ch, 0x00ffff00); > + mmdc_sw_read_calib(ch, 0xff0000ff); > + mmdc_sw_read_calib(ch, 0x55aaaa55); > + mmdc_sw_read_calib(ch, 0xaa5555aa); > + > + for (s = 1; s; s <<= 1) > + mmdc_sw_read_calib(ch, s); > + } > + > + printk("ch0 total lower: %d upper: %d avg: 0x%02x\n", > + total_lower[0], total_upper[0], > + (total_lower[0] + total_upper[0]) / 2); > + printk("ch1 total lower: %d upper: %d avg: 0x%02x\n", > + total_lower[1], total_upper[1], > + (total_lower[1] + total_upper[1]) / 2); > + > + mmdc_set_dqs(0x40); > + > + total_lower[0] = 0; > + total_lower[1] = 0; > + total_upper[0] = 0xff; > + total_upper[1] = 0xff; > + > + for (ch = 0; ch < 2; ch++) { > + mmdc_sw_write_calib(ch, 0x00000055); > + mmdc_sw_write_calib(ch, 0x00005500); > + mmdc_sw_write_calib(ch, 0x00550000); > + mmdc_sw_write_calib(ch, 0x55000000); > + mmdc_sw_write_calib(ch, 0x00ffff00); > + mmdc_sw_write_calib(ch, 0xff0000ff); > + mmdc_sw_write_calib(ch, 0x55aaaa55); > + mmdc_sw_write_calib(ch, 0xaa5555aa); > + > + for (s = 1; s; s <<= 1) > + mmdc_sw_write_calib(ch, s); > + } > + > + printk("ch0 total lower: %d upper: %d avg: 0x%02x\n", > + total_lower[0], total_upper[0], > + (total_lower[0] + total_upper[0]) / 2); > + printk("ch1 total lower: %d upper: %d avg: 0x%02x\n", > + total_lower[1], total_upper[1], > + (total_lower[1] + total_upper[1]) / 2); > + > + return 0; > +} > + > +#endif /* MMDC_SOFTWARE_CALIBRATION */ > diff --git a/arch/arm/mach-imx/include/mach/imx6-mmdc.h b/arch/arm/mach-imx/include/mach/imx6-mmdc.h > new file mode 100644 > index 0000000..4ad939e > --- /dev/null > +++ b/arch/arm/mach-imx/include/mach/imx6-mmdc.h > @@ -0,0 +1,7 @@ > +#ifndef __MACH_MMDC_H > +#define __MACH_MMDC_H > + > +int mmdc_do_write_level_calibration(void); > +int mmdc_do_dqs_calibration(void); > + > +#endif /* __MACH_MMDC_H */ > -- > 1.8.2.rc2 > > > _______________________________________________ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 2/3] Add DMO RealQ7 board support 2013-03-08 12:08 [PATCH] Add DataModul Realq7 board support Sascha Hauer 2013-03-08 12:08 ` [PATCH 1/3] ARM i.MX6: Add mmdc calibration support Sascha Hauer @ 2013-03-08 12:08 ` Sascha Hauer 2013-03-08 12:51 ` Jean-Christophe PLAGNIOL-VILLARD 2013-03-08 12:08 ` [PATCH 3/3] Add DMO RealQ7 defconfig Sascha Hauer 2 siblings, 1 reply; 14+ messages in thread From: Sascha Hauer @ 2013-03-08 12:08 UTC (permalink / raw) To: barebox Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- arch/arm/Makefile | 1 + arch/arm/boards/dmo-mx6-realq7/Makefile | 2 + arch/arm/boards/dmo-mx6-realq7/board.c | 404 +++++++++++++++++++++++ arch/arm/boards/dmo-mx6-realq7/config.h | 4 + arch/arm/boards/dmo-mx6-realq7/env/init/hostname | 8 + arch/arm/boards/dmo-mx6-realq7/flash_header.c | 40 +++ arch/arm/boards/dmo-mx6-realq7/lowlevel.c | 146 ++++++++ arch/arm/mach-imx/Kconfig | 6 + arch/arm/mach-imx/include/mach/devices-imx6.h | 20 ++ 9 files changed, 631 insertions(+) create mode 100644 arch/arm/boards/dmo-mx6-realq7/Makefile create mode 100644 arch/arm/boards/dmo-mx6-realq7/board.c create mode 100644 arch/arm/boards/dmo-mx6-realq7/config.h create mode 100644 arch/arm/boards/dmo-mx6-realq7/env/init/hostname create mode 100644 arch/arm/boards/dmo-mx6-realq7/flash_header.c create mode 100644 arch/arm/boards/dmo-mx6-realq7/lowlevel.c diff --git a/arch/arm/Makefile b/arch/arm/Makefile index b98d6b8..aaf07ac 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -162,6 +162,7 @@ board-$(CONFIG_MACH_TX53) := karo-tx53 board-$(CONFIG_MACH_GUF_VINCELL) := guf-vincell board-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) := efika-mx-smartbook board-$(CONFIG_MACH_SABRESD) := freescale-mx6-sabresd +board-$(CONFIG_MACH_REALQ7) := dmo-mx6-realq7 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) diff --git a/arch/arm/boards/dmo-mx6-realq7/Makefile b/arch/arm/boards/dmo-mx6-realq7/Makefile new file mode 100644 index 0000000..e143009 --- /dev/null +++ b/arch/arm/boards/dmo-mx6-realq7/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o flash_header.o lowlevel.o +pbl-y += flash_header.o lowlevel.o diff --git a/arch/arm/boards/dmo-mx6-realq7/board.c b/arch/arm/boards/dmo-mx6-realq7/board.c new file mode 100644 index 0000000..eda4bca --- /dev/null +++ b/arch/arm/boards/dmo-mx6-realq7/board.c @@ -0,0 +1,404 @@ +/* + * Copyright (C) 2012 Steffen Trumtrar, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation. + * + */ + +#include <common.h> +#include <init.h> +#include <environment.h> +#include <mach/imx6-regs.h> +#include <asm/armlinux.h> +#include <fec.h> +#include <generated/mach-types.h> +#include <partition.h> +#include <spi/spi.h> +#include <sizes.h> +#include <gpio.h> +#include <mci.h> +#include <mfd/stmpe-i2c.h> + +#include <asm/io.h> +#include <asm/mmu.h> + +#include <mach/devices-imx6.h> +#include <mach/iomux-mx6.h> +#include <mach/imx6-mmdc.h> +#include <mach/imx6-regs.h> +#include <mach/generic.h> +#include <mach/imx6.h> +#include <mach/bbu.h> +#include <mach/spi.h> + +static iomux_v3_cfg_t realq7_pads[] = { + MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC, + MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD, + MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS, + MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD, + MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS, + MX6Q_PAD_KEY_ROW2__CAN1_RXCAN, + MX6Q_PAD_GPIO_7__CAN1_TXCAN, + MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0, + MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1, + MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10, + MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11, + MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12, + MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13, + MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14, + MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15, + MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2, + MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3, + MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4, + MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5, + MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6, + MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7, + MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8, + MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9, + MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK, + MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL, + MX6Q_PAD_EIM_OE__ECSPI2_MISO, + MX6Q_PAD_EIM_CS1__ECSPI2_MOSI, + MX6Q_PAD_EIM_CS0__ECSPI2_SCLK, + MX6Q_PAD_EIM_D24__ECSPI2_SS2, + MX6Q_PAD_EIM_D25__ECSPI2_SS3, + MX6Q_PAD_SD1_DAT0__ECSPI5_MISO, + MX6Q_PAD_SD1_CMD__ECSPI5_MOSI, + MX6Q_PAD_SD1_CLK__ECSPI5_SCLK, + MX6Q_PAD_SD2_DAT3__GPIO_1_12, + MX6Q_PAD_ENET_MDC__ENET_MDC, + MX6Q_PAD_ENET_MDIO__ENET_MDIO, + /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII = 0x80000, done in flash_header.c */ + MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0, + MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1, + MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2, + MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3, + MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL, + MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC, + MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK, + MX6Q_PAD_GPIO_0__GPIO_1_0, + MX6Q_PAD_GPIO_2__GPIO_1_2, + MX6Q_PAD_ENET_CRS_DV__GPIO_1_25, + MX6Q_PAD_ENET_RXD0__GPIO_1_27, + MX6Q_PAD_ENET_TX_EN__GPIO_1_28, + MX6Q_PAD_GPIO_3__GPIO_1_3, + MX6Q_PAD_GPIO_4__GPIO_1_4, + MX6Q_PAD_GPIO_5__GPIO_1_5, + MX6Q_PAD_GPIO_8__GPIO_1_8, + MX6Q_PAD_GPIO_9__GPIO_1_9, + MX6Q_PAD_NANDF_D0__GPIO_2_0, + MX6Q_PAD_NANDF_D1__GPIO_2_1, + MX6Q_PAD_NANDF_D2__GPIO_2_2, + MX6Q_PAD_EIM_A17__GPIO_2_21, + MX6Q_PAD_EIM_A16__GPIO_2_22, + MX6Q_PAD_EIM_LBA__GPIO_2_27, + MX6Q_PAD_NANDF_D3__GPIO_2_3, + MX6Q_PAD_NANDF_D4__GPIO_2_4, + MX6Q_PAD_NANDF_D5__GPIO_2_5, + MX6Q_PAD_NANDF_D6__GPIO_2_6, + MX6Q_PAD_NANDF_D7__GPIO_2_7, + MX6Q_PAD_EIM_DA10__GPIO_3_10, + MX6Q_PAD_EIM_DA11__GPIO_3_11, + MX6Q_PAD_EIM_DA12__GPIO_3_12, + MX6Q_PAD_EIM_DA13__GPIO_3_13, + MX6Q_PAD_EIM_DA14__GPIO_3_14, + MX6Q_PAD_EIM_DA15__GPIO_3_15, + MX6Q_PAD_EIM_D16__GPIO_3_16, + MX6Q_PAD_EIM_D18__GPIO_3_18, + MX6Q_PAD_EIM_D19__GPIO_3_19, + MX6Q_PAD_EIM_D20__GPIO_3_20, + MX6Q_PAD_EIM_D23__GPIO_3_23, + MX6Q_PAD_EIM_D29__GPIO_3_29, + MX6Q_PAD_EIM_D30__GPIO_3_30, + MX6Q_PAD_EIM_DA8__GPIO_3_8, + MX6Q_PAD_EIM_DA9__GPIO_3_9, + MX6Q_PAD_KEY_COL2__GPIO_4_10, + MX6Q_PAD_KEY_COL4__GPIO_4_14, + MX6Q_PAD_KEY_ROW4__GPIO_4_15, + MX6Q_PAD_GPIO_19__GPIO_4_5, + MX6Q_PAD_KEY_COL0__GPIO_4_6, + MX6Q_PAD_KEY_ROW0__GPIO_4_7, + MX6Q_PAD_KEY_COL1__GPIO_4_8, + MX6Q_PAD_KEY_ROW1__GPIO_4_9, + MX6Q_PAD_EIM_WAIT__GPIO_5_0, + MX6Q_PAD_EIM_A25__GPIO_5_2, + MX6Q_PAD_EIM_A24__GPIO_5_4, + MX6Q_PAD_EIM_BCLK__GPIO_6_31, + MX6Q_PAD_SD3_DAT5__GPIO_7_0, + MX6Q_PAD_SD3_DAT4__GPIO_7_1, + MX6Q_PAD_GPIO_17__GPIO_7_12, + MX6Q_PAD_GPIO_18__GPIO_7_13, + MX6Q_PAD_SD3_RST__GPIO_7_8, + MX6Q_PAD_EIM_D21__I2C1_SCL, + MX6Q_PAD_EIM_D28__I2C1_SDA, + MX6Q_PAD_EIM_EB2__I2C2_SCL, + MX6Q_PAD_KEY_ROW3__I2C2_SDA, + MX6Q_PAD_EIM_D17__I2C3_SCL, + MX6Q_PAD_GPIO_6__I2C3_SDA, + MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, + MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15, + MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2, + MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3, + MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4, + MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, + MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, + MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, + MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, + MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, + MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, + MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, + MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, + MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, + MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, + MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, + MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, + MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, + MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, + MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, + MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, + MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, + MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, + MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, + MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, + MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, + MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, + MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, + MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, + MX6Q_PAD_SD1_DAT2__PWM2_PWMO, + MX6Q_PAD_SD1_DAT1__PWM3_PWMO, + MX6Q_PAD_GPIO_16__SJC_DE_B, + MX6Q_PAD_KEY_COL3__SPDIF_IN1, + MX6Q_PAD_EIM_D22__SPDIF_OUT1, + MX6Q_PAD_SD3_DAT6__UART1_RXD, + MX6Q_PAD_SD3_DAT7__UART1_TXD, + MX6Q_PAD_EIM_D27__UART2_RXD, + MX6Q_PAD_EIM_D26__UART2_TXD, + MX6Q_PAD_EIM_D31__GPIO_3_31, + MX6Q_PAD_SD3_CLK__USDHC3_CLK, + MX6Q_PAD_SD3_CMD__USDHC3_CMD, + MX6Q_PAD_SD3_DAT0__USDHC3_DAT0, + MX6Q_PAD_SD3_DAT1__USDHC3_DAT1, + MX6Q_PAD_SD3_DAT2__USDHC3_DAT2, + MX6Q_PAD_SD3_DAT3__USDHC3_DAT3, + MX6Q_PAD_SD4_CLK__USDHC4_CLK, + MX6Q_PAD_SD4_CMD__USDHC4_CMD, + MX6Q_PAD_SD4_DAT0__USDHC4_DAT0, + MX6Q_PAD_SD4_DAT1__USDHC4_DAT1, + MX6Q_PAD_SD4_DAT2__USDHC4_DAT2, + MX6Q_PAD_SD4_DAT3__USDHC4_DAT3, + MX6Q_PAD_SD4_DAT4__USDHC4_DAT4, + MX6Q_PAD_SD4_DAT5__USDHC4_DAT5, + MX6Q_PAD_SD4_DAT6__USDHC4_DAT6, + MX6Q_PAD_SD4_DAT7__USDHC4_DAT7, + MX6Q_PAD_NANDF_ALE__USDHC4_RST, + MX6Q_PAD_NANDF_CS1__GPIO_6_14, + MX6Q_PAD_NANDF_CS2__GPIO_6_15, +}; + +static iomux_v3_cfg_t realq7_pads_enet[] = { + MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC, + MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0, + MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1, + MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2, + MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3, + MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL, +}; + +#define RQ7_GPIO_ENET_PHYADD2 IMX_GPIO_NR(6, 30) +#define RQ7_GPIO_ENET_MODE0 IMX_GPIO_NR(6, 25) +#define RQ7_GPIO_ENET_MODE1 IMX_GPIO_NR(6, 27) +#define RQ7_GPIO_ENET_MODE2 IMX_GPIO_NR(6, 28) +#define RQ7_GPIO_ENET_MODE3 IMX_GPIO_NR(6, 29) +#define RQ7_GPIO_ENET_EN_CLK125 IMX_GPIO_NR(6, 24) +#define RQ7_GPIO_SD3_CD IMX_GPIO_NR(6, 14) +#define RQ7_GPIO_SD3_WP IMX_GPIO_NR(6, 15) + +static iomux_v3_cfg_t realq7_pads_gpio[] = { + MX6Q_PAD_RGMII_RXC__GPIO_6_30, + MX6Q_PAD_RGMII_RD0__GPIO_6_25, + MX6Q_PAD_RGMII_RD1__GPIO_6_27, + MX6Q_PAD_RGMII_RD2__GPIO_6_28, + MX6Q_PAD_RGMII_RD3__GPIO_6_29, + MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24, +}; + +static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val) +{ + phy_write(dev, 0x0d, device); + phy_write(dev, 0x0e, reg); + phy_write(dev, 0x0d, (1 << 14) | device); + phy_write(dev, 0x0e, val); +} + +static void mx6_rgmii_rework(struct phy_device *dev) +{ + /* + * min rx data delay, max rx/tx clock delay, + * min rx/tx control delay + */ + mmd_write_reg(dev, 2, 4, 0); + mmd_write_reg(dev, 2, 5, 0); + mmd_write_reg(dev, 2, 8, 0x003ff); +} + +static struct fec_platform_data fec_info = { + .xcv_type = RGMII, + .phy_init = mx6_rgmii_rework, + .phy_addr = -1, +}; + +static void realq7_enet_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(realq7_pads_gpio, ARRAY_SIZE(realq7_pads_gpio)); + gpio_direction_output(RQ7_GPIO_ENET_PHYADD2, 0); + gpio_direction_output(RQ7_GPIO_ENET_MODE0, 1); + gpio_direction_output(RQ7_GPIO_ENET_MODE1, 1); + gpio_direction_output(RQ7_GPIO_ENET_MODE2, 1); + gpio_direction_output(RQ7_GPIO_ENET_MODE3, 1); + gpio_direction_output(RQ7_GPIO_ENET_EN_CLK125, 1); + + gpio_direction_output(25, 0); + mdelay(50); + + gpio_direction_output(25, 1); + mdelay(50); + + mxc_iomux_v3_setup_multiple_pads(realq7_pads_enet, ARRAY_SIZE(realq7_pads_enet)); + + imx6_add_fec(&fec_info); +} + +static int realq7_mem_init(void) +{ + arm_add_mem_device("ram0", 0x10000000, SZ_2G); + + return 0; +} +mem_initcall(realq7_mem_init); + +static int realq7_spi_cs[] = { IMX_GPIO_NR(1, 12), }; + +static struct spi_imx_master realq7_spi_0_data = { + .chipselect = realq7_spi_cs, + .num_chipselect = ARRAY_SIZE(realq7_spi_cs), +}; + +static const struct spi_board_info realq7_spi_board_info[] = { + { + .name = "m25p80", + .max_speed_hz = 40000000, + .bus_num = 4, + .chip_select = 0, + } +}; + +static struct esdhc_platform_data realq7_emmc_data = { + .cd_type = ESDHC_CD_PERMANENT, + .caps = MMC_MODE_8BIT, + .devname = "emmc", +}; + +static struct stmpe_platform_data stmpe1_pdata = { + .gpio_base = 224, + .blocks = STMPE_BLOCK_GPIO, +}; + +static struct stmpe_platform_data stmpe2_pdata = { + .gpio_base = 240, + .blocks = STMPE_BLOCK_GPIO, +}; + +static struct i2c_board_info realq7_i2c2_devices[] = { + { + I2C_BOARD_INFO("stmpe-i2c", 0x40), + .platform_data = &stmpe1_pdata, + }, { + I2C_BOARD_INFO("stmpe-i2c", 0x44), + .platform_data = &stmpe2_pdata, + }, +}; + +static int realq7_devices_init(void) +{ + imx6_add_mmc2(NULL); + imx6_add_mmc3(&realq7_emmc_data); + + realq7_enet_init(); + + i2c_register_board_info(1, realq7_i2c2_devices, + ARRAY_SIZE(realq7_i2c2_devices)); + + imx6_add_i2c0(NULL); + imx6_add_i2c1(NULL); + imx6_add_i2c2(NULL); + + spi_register_board_info(realq7_spi_board_info, + ARRAY_SIZE(realq7_spi_board_info)); + imx6_add_spi4(&realq7_spi_0_data); + + imx6_add_sata(); + + armlinux_set_bootparams((void *)0x10000100); + armlinux_set_architecture(3769); + + imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0", + BBU_HANDLER_FLAG_DEFAULT, NULL, 0, 0x00907000); + imx6_bbu_internal_mmc_register_handler("mmc", "/dev/disk0", + 0, NULL, 0, 0x00907000); + + return 0; +} +device_initcall(realq7_devices_init); + +static int realq7_env_init(void) +{ + char *source_str = NULL; + + switch (imx_bootsource()) { + case bootsource_mmc: + if (!IS_ENABLED(CONFIG_MCI_STARTUP)) + setenv("mci0.probe", "1"); + devfs_add_partition("disk0", 0, SZ_1M, DEVFS_PARTITION_FIXED, "self0"); + devfs_add_partition("disk0", SZ_1M, SZ_1M, DEVFS_PARTITION_FIXED, "env0"); + source_str = "SD/MMC"; + break; + case bootsource_spi: + devfs_add_partition("m25p0", 0, SZ_256K, DEVFS_PARTITION_FIXED, "self0"); + devfs_add_partition("m25p0", SZ_256K, SZ_256K, DEVFS_PARTITION_FIXED, "env0"); + source_str = "SPI flash"; + break; + default: + printf("unknown Bootsource, no persistent environment\n"); + break; + } + + if (source_str) + printf("Using environment from %s\n", source_str); + + return 0; +} +late_initcall(realq7_env_init); + +static int realq7_console_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(realq7_pads, ARRAY_SIZE(realq7_pads)); + + imx6_init_lowlevel(); + + imx6_add_uart1(); + + return 0; +} +console_initcall(realq7_console_init); diff --git a/arch/arm/boards/dmo-mx6-realq7/config.h b/arch/arm/boards/dmo-mx6-realq7/config.h new file mode 100644 index 0000000..ca15136 --- /dev/null +++ b/arch/arm/boards/dmo-mx6-realq7/config.h @@ -0,0 +1,4 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/dmo-mx6-realq7/env/init/hostname b/arch/arm/boards/dmo-mx6-realq7/env/init/hostname new file mode 100644 index 0000000..863960d --- /dev/null +++ b/arch/arm/boards/dmo-mx6-realq7/env/init/hostname @@ -0,0 +1,8 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "hostname" + exit +fi + +global.hostname=realq7 diff --git a/arch/arm/boards/dmo-mx6-realq7/flash_header.c b/arch/arm/boards/dmo-mx6-realq7/flash_header.c new file mode 100644 index 0000000..acd4298 --- /dev/null +++ b/arch/arm/boards/dmo-mx6-realq7/flash_header.c @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <asm/byteorder.h> +#include <mach/imx-flash-header.h> +#include <mach/imx6-regs.h> +#include <asm/barebox-arm-head.h> + +void __naked __flash_header_start go(void) +{ + barebox_arm_head(); +} + +#define APP_DEST 0x00907000 + +struct imx_flash_header_v2 __flash_header_section flash_header = { + .header.tag = IVT_HEADER_TAG, + .header.length = cpu_to_be16(32), + .header.version = IVT_VERSION, + .entry = APP_DEST + 0x2000, + .dcd_ptr = 0, + .boot_data_ptr = APP_DEST + FLASH_HEADER_OFFSET + offsetof(struct imx_flash_header_v2, boot_data), + .self = APP_DEST + FLASH_HEADER_OFFSET, + + .boot_data.start = APP_DEST, + .boot_data.size = 192 * 1024, +}; diff --git a/arch/arm/boards/dmo-mx6-realq7/lowlevel.c b/arch/arm/boards/dmo-mx6-realq7/lowlevel.c new file mode 100644 index 0000000..65823ca --- /dev/null +++ b/arch/arm/boards/dmo-mx6-realq7/lowlevel.c @@ -0,0 +1,146 @@ +#include <common.h> +#include <sizes.h> +#include <io.h> +#include <asm/sections.h> +#include <asm/mmu.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/imx6-mmdc.h> + +static inline void reg32_write(u32 reg, u32 val) +{ + writel(val, reg); +} + +static void sdram_init(void) +{ + reg32_write(0x021b0000, 0x0); + reg32_write(0x020c4068, 0xffffffff); + reg32_write(0x020c406c, 0xffffffff); + reg32_write(0x020c4070, 0xffffffff); + reg32_write(0x020c4074, 0xffffffff); + reg32_write(0x020c4078, 0xffffffff); + reg32_write(0x020c407c, 0xffffffff); + reg32_write(0x020c4080, 0xffffffff); + reg32_write(0x020c4084, 0xffffffff); + reg32_write(0x020e0798, 0x000C0000); + reg32_write(0x020e0758, 0x00000000); + reg32_write(0x020e0588, 0x00000030); + reg32_write(0x020e0594, 0x00000030); + reg32_write(0x020e056c, 0x00000030); + reg32_write(0x020e0578, 0x00000030); + reg32_write(0x020e074c, 0x00000030); + reg32_write(0x020e057c, 0x00000030); + reg32_write(0x020e058c, 0x00000000); + reg32_write(0x020e059c, 0x00000030); + reg32_write(0x020e05a0, 0x00000030); + reg32_write(0x020e078c, 0x00000030); + reg32_write(0x020e0750, 0x00020000); + reg32_write(0x020e05a8, 0x00000038); + reg32_write(0x020e05b0, 0x00000038); + reg32_write(0x020e0524, 0x00000038); + reg32_write(0x020e051c, 0x00000038); + reg32_write(0x020e0518, 0x00000038); + reg32_write(0x020e050c, 0x00000038); + reg32_write(0x020e05b8, 0x00000038); + reg32_write(0x020e05c0, 0x00000038); + reg32_write(0x020e0774, 0x00020000); + reg32_write(0x020e0784, 0x00000030); + reg32_write(0x020e0788, 0x00000030); + reg32_write(0x020e0794, 0x00000030); + reg32_write(0x020e079c, 0x00000030); + reg32_write(0x020e07a0, 0x00000030); + reg32_write(0x020e07a4, 0x00000030); + reg32_write(0x020e07a8, 0x00000030); + reg32_write(0x020e0748, 0x00000030); + reg32_write(0x020e05ac, 0x00000030); + reg32_write(0x020e05b4, 0x00000030); + reg32_write(0x020e0528, 0x00000030); + reg32_write(0x020e0520, 0x00000030); + reg32_write(0x020e0514, 0x00000030); + reg32_write(0x020e0510, 0x00000030); + reg32_write(0x020e05bc, 0x00000030); + reg32_write(0x020e05c4, 0x00000030); + reg32_write(0x021b0800, 0xa1390003); + reg32_write(0x021b080c, 0x0059005C); + reg32_write(0x021b0810, 0x00590056); + reg32_write(0x021b480c, 0x002E0049); + reg32_write(0x021b4810, 0x001B0033); + reg32_write(0x021b083c, 0x434F035B); + reg32_write(0x021b0840, 0x033F033F); + reg32_write(0x021b483c, 0x4337033D); + reg32_write(0x021b4840, 0x03210275); + reg32_write(0x021b0848, 0x4C454344); + reg32_write(0x021b4848, 0x463F3E4A); + reg32_write(0x021b0850, 0x46314742); + reg32_write(0x021b4850, 0x4D2A4B39); + reg32_write(0x021b081c, 0x33333333); + reg32_write(0x021b0820, 0x33333333); + reg32_write(0x021b0824, 0x33333333); + reg32_write(0x021b0828, 0x33333333); + reg32_write(0x021b481c, 0x33333333); + reg32_write(0x021b4820, 0x33333333); + reg32_write(0x021b4824, 0x33333333); + reg32_write(0x021b4828, 0x33333333); + reg32_write(0x021b08b8, 0x00000800); + reg32_write(0x021b48b8, 0x00000800); + reg32_write(0x021b0004, 0x00020036); + reg32_write(0x021b0008, 0x09555050); + reg32_write(0x021b000c, 0x8A8F7934); + reg32_write(0x021b0010, 0xDB568E65); + reg32_write(0x021b0014, 0x01FF00DB); + reg32_write(0x021b0018, 0x00000740); + reg32_write(0x021b001c, 0x00008000); + reg32_write(0x021b002c, 0x000026d2); + reg32_write(0x021b0030, 0x008F0E21); + reg32_write(0x021b0040, 0x00000047); + reg32_write(0x021b0400, 0x11420000); + reg32_write(0x021b4400, 0x11420000); + reg32_write(0x021b0000, 0x841A0000); + reg32_write(0x021b001c, 0x04108032); + reg32_write(0x021b001c, 0x00008033); + reg32_write(0x021b001c, 0x00048031); + reg32_write(0x021b001c, 0x09308030); + reg32_write(0x021b001c, 0x04008040); + reg32_write(0x021b001c, 0x0410803A); + reg32_write(0x021b001c, 0x0000803B); + reg32_write(0x021b001c, 0x00048039); + reg32_write(0x021b001c, 0x09308038); + reg32_write(0x021b001c, 0x04008048); + reg32_write(0x021b0020, 0x00005800); + reg32_write(0x021b0818, 0x00011117); + reg32_write(0x021b4818, 0x00011117); + reg32_write(0x021b0004, 0x00025576); + reg32_write(0x021b0404, 0x00011006); + reg32_write(0x021b001c, 0x00000000); + + /* Enable UART for lowlevel debugging purposes. Can be removed later */ + reg32_write(0x020e00bc, 0x4); + reg32_write(0x020e00c0, 0x4); + reg32_write(0x020e0928, 0x1); + reg32_write(0x021e8080, 0x00000000); + reg32_write(0x021e8084, 0x00004027); + reg32_write(0x021e8088, 0x00000704); + reg32_write(0x021e8090, 0x00000a81); + reg32_write(0x021e809c, 0x0000002b); + reg32_write(0x021e80b0, 0x00013880); + reg32_write(0x021e80a4, 0x0000047f); + reg32_write(0x021e80a8, 0x0000c34f); + reg32_write(0x021e8080, 0x00000001); +} + +void __naked barebox_arm_reset_vector(void) +{ + arm_cpu_lowlevel_init(); + + arm_setup_stack(0x00940000 - 8); + + if (get_pc() < 0x10000000) { + sdram_init(); + + mmdc_do_write_level_calibration(); + mmdc_do_dqs_calibration(); + } + + barebox_arm_entry(0x10000000, SZ_2G, 0); +} diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 1308f3c..d908d5c 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -31,6 +31,7 @@ config ARCH_TEXT_BASE default 0x7fc00000 if MACH_GUF_VINCELL default 0x97f00000 if MACH_EFIKA_MX_SMARTBOOK default 0x17800000 if MACH_SABRESD + default 0x4fc00000 if MACH_REALQ7 config BOARDINFO default "Eukrea CPUIMX25" if MACH_EUKREA_CPUIMX25 @@ -61,6 +62,7 @@ config BOARDINFO default "Ka-Ro tx53" if MACH_TX53 default "Garz+Fricke Vincell" if MACH_GUF_VINCELL default "SabreSD" if MACH_SABRESD + default "DataModul i.MX6Q Real Qseven" if MACH_REALQ7 choice prompt "Select boot mode" @@ -496,6 +498,10 @@ config MACH_SABRELITE config MACH_SABRESD bool "Freescale i.MX6 SabreSD" +config MACH_REALQ7 + bool "DataModul i.MX6Q Real Qseven Board" + select HAVE_DEFAULT_ENVIRONMENT_NEW + endchoice endif diff --git a/arch/arm/mach-imx/include/mach/devices-imx6.h b/arch/arm/mach-imx/include/mach/devices-imx6.h index a9c7e8d..b6b538a 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx6.h +++ b/arch/arm/mach-imx/include/mach/devices-imx6.h @@ -50,6 +50,26 @@ static inline struct device_d *imx6_add_spi0(struct spi_imx_master *pdata) return imx_add_spi((void *)MX6_ECSPI1_BASE_ADDR, 0, pdata); } +static inline struct device_d *imx6_add_spi1(struct spi_imx_master *pdata) +{ + return imx_add_spi((void *)MX6_ECSPI2_BASE_ADDR, 1, pdata); +} + +static inline struct device_d *imx6_add_spi2(struct spi_imx_master *pdata) +{ + return imx_add_spi((void *)MX6_ECSPI3_BASE_ADDR, 2, pdata); +} + +static inline struct device_d *imx6_add_spi3(struct spi_imx_master *pdata) +{ + return imx_add_spi((void *)MX6_ECSPI4_BASE_ADDR, 3, pdata); +} + +static inline struct device_d *imx6_add_spi4(struct spi_imx_master *pdata) +{ + return imx_add_spi((void *)MX6_ECSPI5_BASE_ADDR, 4, pdata); +} + static inline struct device_d *imx6_add_i2c0(struct i2c_platform_data *pdata) { return imx_add_i2c((void *)MX6_I2C1_BASE_ADDR, 0, pdata); -- 1.8.2.rc2 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/3] Add DMO RealQ7 board support 2013-03-08 12:08 ` [PATCH 2/3] Add DMO RealQ7 board support Sascha Hauer @ 2013-03-08 12:51 ` Jean-Christophe PLAGNIOL-VILLARD 2013-03-08 13:07 ` Sascha Hauer 0 siblings, 1 reply; 14+ messages in thread From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-03-08 12:51 UTC (permalink / raw) To: Sascha Hauer; +Cc: barebox > + > +static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val) > +{ > + phy_write(dev, 0x0d, device); > + phy_write(dev, 0x0e, reg); > + phy_write(dev, 0x0d, (1 << 14) | device); > + phy_write(dev, 0x0e, val); > +} > + > +static void mx6_rgmii_rework(struct phy_device *dev) > +{ > + /* > + * min rx data delay, max rx/tx clock delay, > + * min rx/tx control delay > + */ > + mmd_write_reg(dev, 2, 4, 0); > + mmd_write_reg(dev, 2, 5, 0); > + mmd_write_reg(dev, 2, 8, 0x003ff); > +} > + > +static struct fec_platform_data fec_info = { > + .xcv_type = RGMII, > + .phy_init = mx6_rgmii_rework, > + .phy_addr = -1, use phy_fix_up as done on sama5d3xek the phy_init need do be dropped now > +}; > + > +static void realq7_enet_init(void) > +{ > + mxc_iomux_v3_setup_multiple_pads(realq7_pads_gpio, ARRAY_SIZE(realq7_pads_gpio)); > + gpio_direction_output(RQ7_GPIO_ENET_PHYADD2, 0); > + gpio_direction_output(RQ7_GPIO_ENET_MODE0, 1); > + gpio_direction_output(RQ7_GPIO_ENET_MODE1, 1); > + gpio_direction_output(RQ7_GPIO_ENET_MODE2, 1); > + gpio_direction_output(RQ7_GPIO_ENET_MODE3, 1); > + gpio_direction_output(RQ7_GPIO_ENET_EN_CLK125, 1); > + > + gpio_direction_output(25, 0); > + mdelay(50); > + > + gpio_direction_output(25, 1); > + mdelay(50); > + > + mxc_iomux_v3_setup_multiple_pads(realq7_pads_enet, ARRAY_SIZE(realq7_pads_enet)); > + > + imx6_add_fec(&fec_info); > +} > + > +static int realq7_mem_init(void) > +{ > + arm_add_mem_device("ram0", 0x10000000, SZ_2G); > + > + return 0; > +} > +mem_initcall(realq7_mem_init); > + > +static int realq7_spi_cs[] = { IMX_GPIO_NR(1, 12), }; > + > +static struct spi_imx_master realq7_spi_0_data = { > + .chipselect = realq7_spi_cs, > + .num_chipselect = ARRAY_SIZE(realq7_spi_cs), > +}; > + > +static const struct spi_board_info realq7_spi_board_info[] = { > + { > + .name = "m25p80", > + .max_speed_hz = 40000000, > + .bus_num = 4, > + .chip_select = 0, > + } > +}; > + > +static struct esdhc_platform_data realq7_emmc_data = { > + .cd_type = ESDHC_CD_PERMANENT, > + .caps = MMC_MODE_8BIT, > + .devname = "emmc", > +}; we was discussion of symlink on devfs my idea was to use it here instead of the devname > + > +static struct stmpe_platform_data stmpe1_pdata = { > + .gpio_base = 224, > + .blocks = STMPE_BLOCK_GPIO, > +}; > + > +static struct stmpe_platform_data stmpe2_pdata = { > + .gpio_base = 240, > + .blocks = STMPE_BLOCK_GPIO, > +}; > + > +static struct i2c_board_info realq7_i2c2_devices[] = { > + { > + I2C_BOARD_INFO("stmpe-i2c", 0x40), > + .platform_data = &stmpe1_pdata, > + }, { > + I2C_BOARD_INFO("stmpe-i2c", 0x44), > + .platform_data = &stmpe2_pdata, > + }, > +}; > + > +static int realq7_devices_init(void) > +{ > + imx6_add_mmc2(NULL); > + imx6_add_mmc3(&realq7_emmc_data); > + > + realq7_enet_init(); > + > + i2c_register_board_info(1, realq7_i2c2_devices, > + ARRAY_SIZE(realq7_i2c2_devices)); > + > + imx6_add_i2c0(NULL); > + imx6_add_i2c1(NULL); > + imx6_add_i2c2(NULL); > + > + spi_register_board_info(realq7_spi_board_info, > + ARRAY_SIZE(realq7_spi_board_info)); > + imx6_add_spi4(&realq7_spi_0_data); > + > + imx6_add_sata(); > + > + armlinux_set_bootparams((void *)0x10000100); > + armlinux_set_architecture(3769); why a magic instead of a macro? > + > + imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0", > + BBU_HANDLER_FLAG_DEFAULT, NULL, 0, 0x00907000); > + imx6_bbu_internal_mmc_register_handler("mmc", "/dev/disk0", > + 0, NULL, 0, 0x00907000); > + > + return 0; > +} > +device_initcall(realq7_devices_init); > + > +static int realq7_env_init(void) > +{ > + char *source_str = NULL; > + > + switch (imx_bootsource()) { > + case bootsource_mmc: > + if (!IS_ENABLED(CONFIG_MCI_STARTUP)) > + setenv("mci0.probe", "1"); > + devfs_add_partition("disk0", 0, SZ_1M, DEVFS_PARTITION_FIXED, "self0"); > + devfs_add_partition("disk0", SZ_1M, SZ_1M, DEVFS_PARTITION_FIXED, "env0"); > + source_str = "SD/MMC"; > + break; > + case bootsource_spi: > + devfs_add_partition("m25p0", 0, SZ_256K, DEVFS_PARTITION_FIXED, "self0"); > + devfs_add_partition("m25p0", SZ_256K, SZ_256K, DEVFS_PARTITION_FIXED, "env0"); > + source_str = "SPI flash"; > + break; > + default: > + printf("unknown Bootsource, no persistent environment\n"); > + break; > + } > + > + if (source_str) > + printf("Using environment from %s\n", source_str); > + > + return 0; > +} > +late_initcall(realq7_env_init); > + > +static int realq7_console_init(void) > +{ > + mxc_iomux_v3_setup_multiple_pads(realq7_pads, ARRAY_SIZE(realq7_pads)); > + > + imx6_init_lowlevel(); > + > + imx6_add_uart1(); > + > + return 0; > +} > +console_initcall(realq7_console_init); > diff --git a/arch/arm/boards/dmo-mx6-realq7/config.h b/arch/arm/boards/dmo-mx6-realq7/config.h > new file mode 100644 > index 0000000..ca15136 > --- /dev/null > +++ b/arch/arm/boards/dmo-mx6-realq7/config.h > @@ -0,0 +1,4 @@ > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +#endif /* __CONFIG_H */ > diff --git a/arch/arm/boards/dmo-mx6-realq7/env/init/hostname b/arch/arm/boards/dmo-mx6-realq7/env/init/hostname > new file mode 100644 > index 0000000..863960d > --- /dev/null > +++ b/arch/arm/boards/dmo-mx6-realq7/env/init/hostname > @@ -0,0 +1,8 @@ > +#!/bin/sh > + > +if [ "$1" = menu ]; then > + init-menu-add-entry "$0" "hostname" > + exit > +fi > + > +global.hostname=realq7 in config-board? > diff --git a/arch/arm/boards/dmo-mx6-realq7/flash_header.c b/arch/arm/boards/dmo-mx6-realq7/flash_header.c > new file mode 100644 > index 0000000..acd4298 > --- /dev/null > +++ b/arch/arm/boards/dmo-mx6-realq7/flash_header.c > @@ -0,0 +1,40 @@ > +/* > + * Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de> > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + */ > + > +#include <common.h> > +#include <asm/byteorder.h> > +#include <mach/imx-flash-header.h> > +#include <mach/imx6-regs.h> > +#include <asm/barebox-arm-head.h> > + > +void __naked __flash_header_start go(void) > +{ > + barebox_arm_head(); > +} > + > +#define APP_DEST 0x00907000 > + > +struct imx_flash_header_v2 __flash_header_section flash_header = { > + .header.tag = IVT_HEADER_TAG, > + .header.length = cpu_to_be16(32), > + .header.version = IVT_VERSION, > + .entry = APP_DEST + 0x2000, > + .dcd_ptr = 0, > + .boot_data_ptr = APP_DEST + FLASH_HEADER_OFFSET + offsetof(struct imx_flash_header_v2, boot_data), > + .self = APP_DEST + FLASH_HEADER_OFFSET, > + > + .boot_data.start = APP_DEST, > + .boot_data.size = 192 * 1024, barebox_image_size > +}; > diff --git a/arch/arm/boards/dmo-mx6-realq7/lowlevel.c b/arch/arm/boards/dmo-mx6-realq7/lowlevel.c > new file mode 100644 > index 0000000..65823ca > --- /dev/null > +++ b/arch/arm/boards/dmo-mx6-realq7/lowlevel.c > @@ -0,0 +1,146 @@ > +#include <common.h> > +#include <sizes.h> > +#include <io.h> > +#include <asm/sections.h> > +#include <asm/mmu.h> > +#include <asm/barebox-arm-head.h> > +#include <asm/barebox-arm.h> > +#include <mach/imx6-mmdc.h> > + > +static inline void reg32_write(u32 reg, u32 val) > +{ > + writel(val, reg); > +} > + > +static void sdram_init(void) > +{ > + reg32_write(0x021b0000, 0x0); > + reg32_write(0x020c4068, 0xffffffff); > + reg32_write(0x020c406c, 0xffffffff); > + reg32_write(0x020c4070, 0xffffffff); > + reg32_write(0x020c4074, 0xffffffff); > + reg32_write(0x020c4078, 0xffffffff); > + reg32_write(0x020c407c, 0xffffffff); > + reg32_write(0x020c4080, 0xffffffff); > + reg32_write(0x020c4084, 0xffffffff); > + reg32_write(0x020e0798, 0x000C0000); > + reg32_write(0x020e0758, 0x00000000); > + reg32_write(0x020e0588, 0x00000030); > + reg32_write(0x020e0594, 0x00000030); > + reg32_write(0x020e056c, 0x00000030); > + reg32_write(0x020e0578, 0x00000030); > + reg32_write(0x020e074c, 0x00000030); > + reg32_write(0x020e057c, 0x00000030); > + reg32_write(0x020e058c, 0x00000000); > + reg32_write(0x020e059c, 0x00000030); > + reg32_write(0x020e05a0, 0x00000030); > + reg32_write(0x020e078c, 0x00000030); > + reg32_write(0x020e0750, 0x00020000); > + reg32_write(0x020e05a8, 0x00000038); > + reg32_write(0x020e05b0, 0x00000038); > + reg32_write(0x020e0524, 0x00000038); > + reg32_write(0x020e051c, 0x00000038); > + reg32_write(0x020e0518, 0x00000038); > + reg32_write(0x020e050c, 0x00000038); > + reg32_write(0x020e05b8, 0x00000038); > + reg32_write(0x020e05c0, 0x00000038); > + reg32_write(0x020e0774, 0x00020000); > + reg32_write(0x020e0784, 0x00000030); > + reg32_write(0x020e0788, 0x00000030); > + reg32_write(0x020e0794, 0x00000030); > + reg32_write(0x020e079c, 0x00000030); > + reg32_write(0x020e07a0, 0x00000030); > + reg32_write(0x020e07a4, 0x00000030); > + reg32_write(0x020e07a8, 0x00000030); > + reg32_write(0x020e0748, 0x00000030); > + reg32_write(0x020e05ac, 0x00000030); > + reg32_write(0x020e05b4, 0x00000030); > + reg32_write(0x020e0528, 0x00000030); > + reg32_write(0x020e0520, 0x00000030); > + reg32_write(0x020e0514, 0x00000030); > + reg32_write(0x020e0510, 0x00000030); > + reg32_write(0x020e05bc, 0x00000030); > + reg32_write(0x020e05c4, 0x00000030); > + reg32_write(0x021b0800, 0xa1390003); > + reg32_write(0x021b080c, 0x0059005C); > + reg32_write(0x021b0810, 0x00590056); > + reg32_write(0x021b480c, 0x002E0049); > + reg32_write(0x021b4810, 0x001B0033); > + reg32_write(0x021b083c, 0x434F035B); > + reg32_write(0x021b0840, 0x033F033F); > + reg32_write(0x021b483c, 0x4337033D); > + reg32_write(0x021b4840, 0x03210275); > + reg32_write(0x021b0848, 0x4C454344); > + reg32_write(0x021b4848, 0x463F3E4A); > + reg32_write(0x021b0850, 0x46314742); > + reg32_write(0x021b4850, 0x4D2A4B39); > + reg32_write(0x021b081c, 0x33333333); > + reg32_write(0x021b0820, 0x33333333); > + reg32_write(0x021b0824, 0x33333333); > + reg32_write(0x021b0828, 0x33333333); > + reg32_write(0x021b481c, 0x33333333); > + reg32_write(0x021b4820, 0x33333333); > + reg32_write(0x021b4824, 0x33333333); > + reg32_write(0x021b4828, 0x33333333); > + reg32_write(0x021b08b8, 0x00000800); > + reg32_write(0x021b48b8, 0x00000800); > + reg32_write(0x021b0004, 0x00020036); > + reg32_write(0x021b0008, 0x09555050); > + reg32_write(0x021b000c, 0x8A8F7934); > + reg32_write(0x021b0010, 0xDB568E65); > + reg32_write(0x021b0014, 0x01FF00DB); > + reg32_write(0x021b0018, 0x00000740); > + reg32_write(0x021b001c, 0x00008000); > + reg32_write(0x021b002c, 0x000026d2); > + reg32_write(0x021b0030, 0x008F0E21); > + reg32_write(0x021b0040, 0x00000047); > + reg32_write(0x021b0400, 0x11420000); > + reg32_write(0x021b4400, 0x11420000); > + reg32_write(0x021b0000, 0x841A0000); > + reg32_write(0x021b001c, 0x04108032); > + reg32_write(0x021b001c, 0x00008033); > + reg32_write(0x021b001c, 0x00048031); > + reg32_write(0x021b001c, 0x09308030); > + reg32_write(0x021b001c, 0x04008040); > + reg32_write(0x021b001c, 0x0410803A); > + reg32_write(0x021b001c, 0x0000803B); > + reg32_write(0x021b001c, 0x00048039); > + reg32_write(0x021b001c, 0x09308038); > + reg32_write(0x021b001c, 0x04008048); > + reg32_write(0x021b0020, 0x00005800); > + reg32_write(0x021b0818, 0x00011117); > + reg32_write(0x021b4818, 0x00011117); > + reg32_write(0x021b0004, 0x00025576); > + reg32_write(0x021b0404, 0x00011006); > + reg32_write(0x021b001c, 0x00000000); > + > + /* Enable UART for lowlevel debugging purposes. Can be removed later */ > + reg32_write(0x020e00bc, 0x4); > + reg32_write(0x020e00c0, 0x4); > + reg32_write(0x020e0928, 0x1); > + reg32_write(0x021e8080, 0x00000000); > + reg32_write(0x021e8084, 0x00004027); > + reg32_write(0x021e8088, 0x00000704); > + reg32_write(0x021e8090, 0x00000a81); > + reg32_write(0x021e809c, 0x0000002b); > + reg32_write(0x021e80b0, 0x00013880); > + reg32_write(0x021e80a4, 0x0000047f); > + reg32_write(0x021e80a8, 0x0000c34f); > + reg32_write(0x021e8080, 0x00000001); can we have not all of those magic? > +} > + > +void __naked barebox_arm_reset_vector(void) > +{ > + arm_cpu_lowlevel_init(); > + > + arm_setup_stack(0x00940000 - 8); > + > + if (get_pc() < 0x10000000) { > + sdram_init(); > + > + mmdc_do_write_level_calibration(); > + mmdc_do_dqs_calibration(); > + } > + > + barebox_arm_entry(0x10000000, SZ_2G, 0); > +} > diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig > index 1308f3c..d908d5c 100644 > --- a/arch/arm/mach-imx/Kconfig > +++ b/arch/arm/mach-imx/Kconfig > @@ -31,6 +31,7 @@ config ARCH_TEXT_BASE > default 0x7fc00000 if MACH_GUF_VINCELL > default 0x97f00000 if MACH_EFIKA_MX_SMARTBOOK > default 0x17800000 if MACH_SABRESD > + default 0x4fc00000 if MACH_REALQ7 > > config BOARDINFO > default "Eukrea CPUIMX25" if MACH_EUKREA_CPUIMX25 > @@ -61,6 +62,7 @@ config BOARDINFO > default "Ka-Ro tx53" if MACH_TX53 > default "Garz+Fricke Vincell" if MACH_GUF_VINCELL > default "SabreSD" if MACH_SABRESD > + default "DataModul i.MX6Q Real Qseven" if MACH_REALQ7 > > choice > prompt "Select boot mode" > @@ -496,6 +498,10 @@ config MACH_SABRELITE > config MACH_SABRESD > bool "Freescale i.MX6 SabreSD" > > +config MACH_REALQ7 > + bool "DataModul i.MX6Q Real Qseven Board" > + select HAVE_DEFAULT_ENVIRONMENT_NEW > + > endchoice > > endif > diff --git a/arch/arm/mach-imx/include/mach/devices-imx6.h b/arch/arm/mach-imx/include/mach/devices-imx6.h > index a9c7e8d..b6b538a 100644 > --- a/arch/arm/mach-imx/include/mach/devices-imx6.h > +++ b/arch/arm/mach-imx/include/mach/devices-imx6.h > @@ -50,6 +50,26 @@ static inline struct device_d *imx6_add_spi0(struct spi_imx_master *pdata) > return imx_add_spi((void *)MX6_ECSPI1_BASE_ADDR, 0, pdata); > } > > +static inline struct device_d *imx6_add_spi1(struct spi_imx_master *pdata) > +{ > + return imx_add_spi((void *)MX6_ECSPI2_BASE_ADDR, 1, pdata); > +} > + > +static inline struct device_d *imx6_add_spi2(struct spi_imx_master *pdata) > +{ > + return imx_add_spi((void *)MX6_ECSPI3_BASE_ADDR, 2, pdata); > +} > + > +static inline struct device_d *imx6_add_spi3(struct spi_imx_master *pdata) > +{ > + return imx_add_spi((void *)MX6_ECSPI4_BASE_ADDR, 3, pdata); > +} > + > +static inline struct device_d *imx6_add_spi4(struct spi_imx_master *pdata) > +{ > + return imx_add_spi((void *)MX6_ECSPI5_BASE_ADDR, 4, pdata); > +} > + > static inline struct device_d *imx6_add_i2c0(struct i2c_platform_data *pdata) > { > return imx_add_i2c((void *)MX6_I2C1_BASE_ADDR, 0, pdata); > -- > 1.8.2.rc2 > > > _______________________________________________ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/3] Add DMO RealQ7 board support 2013-03-08 12:51 ` Jean-Christophe PLAGNIOL-VILLARD @ 2013-03-08 13:07 ` Sascha Hauer 2013-03-08 14:48 ` Jean-Christophe PLAGNIOL-VILLARD 0 siblings, 1 reply; 14+ messages in thread From: Sascha Hauer @ 2013-03-08 13:07 UTC (permalink / raw) To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox On Fri, Mar 08, 2013 at 01:51:38PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote: > > + > > +static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val) > > +{ > > + phy_write(dev, 0x0d, device); > > + phy_write(dev, 0x0e, reg); > > + phy_write(dev, 0x0d, (1 << 14) | device); > > + phy_write(dev, 0x0e, val); > > +} > > + > > +static void mx6_rgmii_rework(struct phy_device *dev) > > +{ > > + /* > > + * min rx data delay, max rx/tx clock delay, > > + * min rx/tx control delay > > + */ > > + mmd_write_reg(dev, 2, 4, 0); > > + mmd_write_reg(dev, 2, 5, 0); > > + mmd_write_reg(dev, 2, 8, 0x003ff); > > +} > > + > > +static struct fec_platform_data fec_info = { > > + .xcv_type = RGMII, > > + .phy_init = mx6_rgmii_rework, > > + .phy_addr = -1, > use phy_fix_up as done on sama5d3xek > > the phy_init need do be dropped now > > +}; > > + > > +static void realq7_enet_init(void) > > +{ > > + mxc_iomux_v3_setup_multiple_pads(realq7_pads_gpio, ARRAY_SIZE(realq7_pads_gpio)); > > + gpio_direction_output(RQ7_GPIO_ENET_PHYADD2, 0); > > + gpio_direction_output(RQ7_GPIO_ENET_MODE0, 1); > > + gpio_direction_output(RQ7_GPIO_ENET_MODE1, 1); > > + gpio_direction_output(RQ7_GPIO_ENET_MODE2, 1); > > + gpio_direction_output(RQ7_GPIO_ENET_MODE3, 1); > > + gpio_direction_output(RQ7_GPIO_ENET_EN_CLK125, 1); > > + > > + gpio_direction_output(25, 0); > > + mdelay(50); > > + > > + gpio_direction_output(25, 1); > > + mdelay(50); > > + > > + mxc_iomux_v3_setup_multiple_pads(realq7_pads_enet, ARRAY_SIZE(realq7_pads_enet)); > > + > > + imx6_add_fec(&fec_info); > > +} > > + > > +static int realq7_mem_init(void) > > +{ > > + arm_add_mem_device("ram0", 0x10000000, SZ_2G); > > + > > + return 0; > > +} > > +mem_initcall(realq7_mem_init); > > + > > +static int realq7_spi_cs[] = { IMX_GPIO_NR(1, 12), }; > > + > > +static struct spi_imx_master realq7_spi_0_data = { > > + .chipselect = realq7_spi_cs, > > + .num_chipselect = ARRAY_SIZE(realq7_spi_cs), > > +}; > > + > > +static const struct spi_board_info realq7_spi_board_info[] = { > > + { > > + .name = "m25p80", > > + .max_speed_hz = 40000000, > > + .bus_num = 4, > > + .chip_select = 0, > > + } > > +}; > > + > > +static struct esdhc_platform_data realq7_emmc_data = { > > + .cd_type = ESDHC_CD_PERMANENT, > > + .caps = MMC_MODE_8BIT, > > + .devname = "emmc", > > +}; > we was discussion of symlink on devfs my idea was to use it here instead of > the devname The sysfs symlink support alone does not fix this. Who should create the link? > > + > > + armlinux_set_bootparams((void *)0x10000100); > > + armlinux_set_architecture(3769); > why a magic instead of a macro? Can be dropped. It's devicetree only, so we don't need an architecture id. I doubt there is one even registered. Sascha > > +++ b/arch/arm/boards/dmo-mx6-realq7/env/init/hostname > > @@ -0,0 +1,8 @@ > > +#!/bin/sh > > + > > +if [ "$1" = menu ]; then > > + init-menu-add-entry "$0" "hostname" > > + exit > > +fi > > + > > +global.hostname=realq7 > in config-board? ok. > > + > > + .boot_data.start = APP_DEST, > > + .boot_data.size = 192 * 1024, > barebox_image_size ok. This btw will not work with CONFIG_RELOCATABLE as is since the linker cannot generate this value then. > > + reg32_write(0x021e80a4, 0x0000047f); > > + reg32_write(0x021e80a8, 0x0000c34f); > > + reg32_write(0x021e8080, 0x00000001); > can we have not all of those magic? No, I won't do the decoding now. This time can be invested better. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/3] Add DMO RealQ7 board support 2013-03-08 13:07 ` Sascha Hauer @ 2013-03-08 14:48 ` Jean-Christophe PLAGNIOL-VILLARD 2013-03-08 15:06 ` Sascha Hauer 0 siblings, 1 reply; 14+ messages in thread From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-03-08 14:48 UTC (permalink / raw) To: Sascha Hauer; +Cc: barebox On 14:07 Fri 08 Mar , Sascha Hauer wrote: > On Fri, Mar 08, 2013 at 01:51:38PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote: > > > + > > > +static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val) > > > +{ > > > + phy_write(dev, 0x0d, device); > > > + phy_write(dev, 0x0e, reg); > > > + phy_write(dev, 0x0d, (1 << 14) | device); > > > + phy_write(dev, 0x0e, val); > > > +} > > > + > > > +static void mx6_rgmii_rework(struct phy_device *dev) > > > +{ > > > + /* > > > + * min rx data delay, max rx/tx clock delay, > > > + * min rx/tx control delay > > > + */ > > > + mmd_write_reg(dev, 2, 4, 0); > > > + mmd_write_reg(dev, 2, 5, 0); > > > + mmd_write_reg(dev, 2, 8, 0x003ff); > > > +} > > > + > > > +static struct fec_platform_data fec_info = { > > > + .xcv_type = RGMII, > > > + .phy_init = mx6_rgmii_rework, > > > + .phy_addr = -1, > > use phy_fix_up as done on sama5d3xek > > > > the phy_init need do be dropped now > > > +}; > > > + > > > +static void realq7_enet_init(void) > > > +{ > > > + mxc_iomux_v3_setup_multiple_pads(realq7_pads_gpio, ARRAY_SIZE(realq7_pads_gpio)); > > > + gpio_direction_output(RQ7_GPIO_ENET_PHYADD2, 0); > > > + gpio_direction_output(RQ7_GPIO_ENET_MODE0, 1); > > > + gpio_direction_output(RQ7_GPIO_ENET_MODE1, 1); > > > + gpio_direction_output(RQ7_GPIO_ENET_MODE2, 1); > > > + gpio_direction_output(RQ7_GPIO_ENET_MODE3, 1); > > > + gpio_direction_output(RQ7_GPIO_ENET_EN_CLK125, 1); > > > + > > > + gpio_direction_output(25, 0); > > > + mdelay(50); > > > + > > > + gpio_direction_output(25, 1); > > > + mdelay(50); > > > + > > > + mxc_iomux_v3_setup_multiple_pads(realq7_pads_enet, ARRAY_SIZE(realq7_pads_enet)); > > > + > > > + imx6_add_fec(&fec_info); > > > +} > > > + > > > +static int realq7_mem_init(void) > > > +{ > > > + arm_add_mem_device("ram0", 0x10000000, SZ_2G); > > > + > > > + return 0; > > > +} > > > +mem_initcall(realq7_mem_init); > > > + > > > +static int realq7_spi_cs[] = { IMX_GPIO_NR(1, 12), }; > > > + > > > +static struct spi_imx_master realq7_spi_0_data = { > > > + .chipselect = realq7_spi_cs, > > > + .num_chipselect = ARRAY_SIZE(realq7_spi_cs), > > > +}; > > > + > > > +static const struct spi_board_info realq7_spi_board_info[] = { > > > + { > > > + .name = "m25p80", > > > + .max_speed_hz = 40000000, > > > + .bus_num = 4, > > > + .chip_select = 0, > > > + } > > > +}; > > > + > > > +static struct esdhc_platform_data realq7_emmc_data = { > > > + .cd_type = ESDHC_CD_PERMANENT, > > > + .caps = MMC_MODE_8BIT, > > > + .devname = "emmc", > > > +}; > > we was discussion of symlink on devfs my idea was to use it here instead of > > the devname > > The sysfs symlink support alone does not fix this. Who should create the > link? yes I was thinking the mci core create the symlink > > > > + > > > + armlinux_set_bootparams((void *)0x10000100); > > > + armlinux_set_architecture(3769); > > why a magic instead of a macro? > > Can be dropped. It's devicetree only, so we don't need an architecture > id. I doubt there is one even registered. > > Sascha > > > > +++ b/arch/arm/boards/dmo-mx6-realq7/env/init/hostname > > > @@ -0,0 +1,8 @@ > > > +#!/bin/sh > > > + > > > +if [ "$1" = menu ]; then > > > + init-menu-add-entry "$0" "hostname" > > > + exit > > > +fi > > > + > > > +global.hostname=realq7 > > in config-board? > > ok. > > > > + > > > + .boot_data.start = APP_DEST, > > > + .boot_data.size = 192 * 1024, > > barebox_image_size > > ok. This btw will not work with CONFIG_RELOCATABLE as is since the > linker cannot generate this value then. why? otherwise we need to update it via ld as done in the kernel as example > > > > + reg32_write(0x021e80a4, 0x0000047f); > > > + reg32_write(0x021e80a8, 0x0000c34f); > > > + reg32_write(0x021e8080, 0x00000001); > > can we have not all of those magic? > > No, I won't do the decoding now. This time can be invested better. > > Sascha > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/3] Add DMO RealQ7 board support 2013-03-08 14:48 ` Jean-Christophe PLAGNIOL-VILLARD @ 2013-03-08 15:06 ` Sascha Hauer 2013-03-08 15:46 ` Jean-Christophe PLAGNIOL-VILLARD 0 siblings, 1 reply; 14+ messages in thread From: Sascha Hauer @ 2013-03-08 15:06 UTC (permalink / raw) To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox On Fri, Mar 08, 2013 at 03:48:43PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote: > > > > + .boot_data.size = 192 * 1024, > > > barebox_image_size > > > > ok. This btw will not work with CONFIG_RELOCATABLE as is since the > > linker cannot generate this value then. > why? Absolute values will be zero when you link with -pie. They get fixed during relocation. The image size is a relative value, when doing a .word __barebox_image_end - start in assembly it works correctly, but doing the same in C does not work. > > otherwise we need to update it via ld as done in the kernel as example Can you give me a pointer what the kernel does? Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/3] Add DMO RealQ7 board support 2013-03-08 15:06 ` Sascha Hauer @ 2013-03-08 15:46 ` Jean-Christophe PLAGNIOL-VILLARD 2013-03-08 16:23 ` Jean-Christophe PLAGNIOL-VILLARD 2013-03-09 19:03 ` Sascha Hauer 0 siblings, 2 replies; 14+ messages in thread From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-03-08 15:46 UTC (permalink / raw) To: Sascha Hauer; +Cc: barebox On 16:06 Fri 08 Mar , Sascha Hauer wrote: > On Fri, Mar 08, 2013 at 03:48:43PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote: > > > > > + .boot_data.size = 192 * 1024, > > > > barebox_image_size > > > > > > ok. This btw will not work with CONFIG_RELOCATABLE as is since the > > > linker cannot generate this value then. > > why? > > Absolute values will be zero when you link with -pie. They get fixed > during relocation. > > The image size is a relative value, when doing a > > .word __barebox_image_end - start > > in assembly it works correctly, but doing the same in C does not work. > > > > > otherwise we need to update it via ld as done in the kernel as example > > Can you give me a pointer what the kernel does? we create the symbol at compilation via --defsym arch/arm/boot/compressed/Makefile Best Regards, J. > > Sascha > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/3] Add DMO RealQ7 board support 2013-03-08 15:46 ` Jean-Christophe PLAGNIOL-VILLARD @ 2013-03-08 16:23 ` Jean-Christophe PLAGNIOL-VILLARD 2013-03-09 19:03 ` Sascha Hauer 1 sibling, 0 replies; 14+ messages in thread From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-03-08 16:23 UTC (permalink / raw) To: Sascha Hauer; +Cc: barebox On 16:46 Fri 08 Mar , Jean-Christophe PLAGNIOL-VILLARD wrote: > On 16:06 Fri 08 Mar , Sascha Hauer wrote: > > On Fri, Mar 08, 2013 at 03:48:43PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote: > > > > > > + .boot_data.size = 192 * 1024, > > > > > barebox_image_size > > > > > > > > ok. This btw will not work with CONFIG_RELOCATABLE as is since the > > > > linker cannot generate this value then. > > > why? > > > > Absolute values will be zero when you link with -pie. They get fixed > > during relocation. > > > > The image size is a relative value, when doing a > > > > .word __barebox_image_end - start > > > > in assembly it works correctly, but doing the same in C does not work. so put a value in asm and this will be resolve by the linker at compilation time not runtime Best Regards, J. _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/3] Add DMO RealQ7 board support 2013-03-08 15:46 ` Jean-Christophe PLAGNIOL-VILLARD 2013-03-08 16:23 ` Jean-Christophe PLAGNIOL-VILLARD @ 2013-03-09 19:03 ` Sascha Hauer 1 sibling, 0 replies; 14+ messages in thread From: Sascha Hauer @ 2013-03-09 19:03 UTC (permalink / raw) To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox On Fri, Mar 08, 2013 at 04:46:11PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote: > On 16:06 Fri 08 Mar , Sascha Hauer wrote: > > On Fri, Mar 08, 2013 at 03:48:43PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote: > > > > > > + .boot_data.size = 192 * 1024, > > > > > barebox_image_size > > > > > > > > ok. This btw will not work with CONFIG_RELOCATABLE as is since the > > > > linker cannot generate this value then. > > > why? > > > > Absolute values will be zero when you link with -pie. They get fixed > > during relocation. > > > > The image size is a relative value, when doing a > > > > .word __barebox_image_end - start > > > > in assembly it works correctly, but doing the same in C does not work. > > > > > > > > otherwise we need to update it via ld as done in the kernel as example > > > > Can you give me a pointer what the kernel does? > > we create the symbol at compilation > via --defsym It just turned out --defsym also does not work together with -pie. The value in the image is still 0x0. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 3/3] Add DMO RealQ7 defconfig 2013-03-08 12:08 [PATCH] Add DataModul Realq7 board support Sascha Hauer 2013-03-08 12:08 ` [PATCH 1/3] ARM i.MX6: Add mmdc calibration support Sascha Hauer 2013-03-08 12:08 ` [PATCH 2/3] Add DMO RealQ7 board support Sascha Hauer @ 2013-03-08 12:08 ` Sascha Hauer 2 siblings, 0 replies; 14+ messages in thread From: Sascha Hauer @ 2013-03-08 12:08 UTC (permalink / raw) To: barebox Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- arch/arm/configs/dmo-realq7_defconfig | 91 +++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 arch/arm/configs/dmo-realq7_defconfig diff --git a/arch/arm/configs/dmo-realq7_defconfig b/arch/arm/configs/dmo-realq7_defconfig new file mode 100644 index 0000000..d063e97 --- /dev/null +++ b/arch/arm/configs/dmo-realq7_defconfig @@ -0,0 +1,91 @@ +CONFIG_ARCH_IMX=y +CONFIG_ARCH_IMX6=y +CONFIG_MACH_REALQ7=y +CONFIG_IMX_IIM=y +CONFIG_IMX_IIM_FUSE_BLOW=y +CONFIG_THUMB2_BAREBOX=y +CONFIG_CMD_ARM_MMUINFO=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_PBL_IMAGE=y +CONFIG_MMU=y +CONFIG_TEXT_BASE=0x8fc00000 +CONFIG_MALLOC_SIZE=0x40000000 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_LONGHELP=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/dmo-mx6-realq7/env" +CONFIG_RESET_SOURCE=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_LN=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_OFTREE_PROBE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SPI=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_CLK=y +CONFIG_CMD_WD=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_NET_RESOLV=y +CONFIG_DRIVER_NET_FEC_IMX=y +CONFIG_DRIVER_SPI_IMX=y +CONFIG_I2C=y +CONFIG_I2C_IMX=y +CONFIG_MTD=y +CONFIG_MTD_M25P80=y +CONFIG_DISK_AHCI=y +CONFIG_DISK_AHCI_IMX=y +CONFIG_MCI=y +CONFIG_MCI_IMX_ESDHC=y +CONFIG_MFD_STMPE=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_IMX=y +CONFIG_GPIO_STMPE=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y -- 1.8.2.rc2 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2013-03-09 19:03 UTC | newest] Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2013-03-08 12:08 [PATCH] Add DataModul Realq7 board support Sascha Hauer 2013-03-08 12:08 ` [PATCH 1/3] ARM i.MX6: Add mmdc calibration support Sascha Hauer 2013-03-08 12:17 ` Alexander Shiyan 2013-03-08 14:00 ` Sascha Hauer 2013-03-08 12:46 ` Jean-Christophe PLAGNIOL-VILLARD 2013-03-08 12:08 ` [PATCH 2/3] Add DMO RealQ7 board support Sascha Hauer 2013-03-08 12:51 ` Jean-Christophe PLAGNIOL-VILLARD 2013-03-08 13:07 ` Sascha Hauer 2013-03-08 14:48 ` Jean-Christophe PLAGNIOL-VILLARD 2013-03-08 15:06 ` Sascha Hauer 2013-03-08 15:46 ` Jean-Christophe PLAGNIOL-VILLARD 2013-03-08 16:23 ` Jean-Christophe PLAGNIOL-VILLARD 2013-03-09 19:03 ` Sascha Hauer 2013-03-08 12:08 ` [PATCH 3/3] Add DMO RealQ7 defconfig Sascha Hauer
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox