Re: [PATCH] ARM: Add support for IXP4xx CPU and for Goramo Multilink router platform.

[Sascha Hauer <s.hauer@pengutronix.de>]

On Sat, Mar 30, 2013 at 12:26:47PM +0100, Krzysztof Halasa wrote:
> Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>

The npe driver and the network driver should really be a separate patch.
Some more comments inline.

> 
> +static struct eth_plat_info eth_pinfo[2] = {

Why not use dynamically sized arrays?

> diff --git a/arch/arm/lib/barebox.lds.S b/arch/arm/lib/barebox.lds.S
> index 10c63bf..b40b24b 100644
> --- a/arch/arm/lib/barebox.lds.S
> +++ b/arch/arm/lib/barebox.lds.S
> @@ -40,6 +40,9 @@ SECTIONS
>  		_stext = .;
>  		_text = .;
>  		*(.text_entry*)
> +#ifdef CONFIG_MACH_GORAMO_MLR
> +		. = 0x0080; /* config space at 0x40 - 0x7F */
> +#endif

Please use PRE_IMAGE. We do not want to have such stuff in the generic
linker script.

> +#ifdef CONFIG_DRIVER_SERIAL_NS16550
> +
> +/**
> + * @brief UART port register read function for IXP4XX
> + *
> + * @param base base address of UART
> + * @param reg_idx register index
> + *
> + * @return character read from register
> + */
> +unsigned int ixp4xx_uart_read(unsigned long base, unsigned char reg_idx)
> +{
> +	return readb(4 * reg_idx + 3 /* big-endian */ + (uint8_t *)base);
> +}
> +EXPORT_SYMBOL(ixp4xx_uart_read);
> +
> +/**
> + * @brief UART port register write function for IXP4XX
> + *
> + * @param val value to write
> + * @param base base address of UART
> + * @param reg_idx register index
> + *
> + * @return void
> + */
> +void ixp4xx_uart_write(unsigned int val, unsigned long base, unsigned char reg_idx)
> +{
> +	writeb(val, 4 * reg_idx + 3 /* big-endian */ + (uint8_t *)base);
> +}
> +EXPORT_SYMBOL(ixp4xx_uart_write);
> +
> +
> +static struct NS16550_plat serial_plat = {
> +	.clock = 14745600,
> +	.f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
> +	.reg_read = ixp4xx_uart_read,
> +	.reg_write = ixp4xx_uart_write,
> +};
> +
> +/**
> + * @brief UART serial port initialization
> + *
> + * @return result of device registration
> + */
> +static int ixp4xx_console_init(void)
> +{
> +	/* Register the serial port */
> +	add_ns16550_device(0, (u32)IXP4XX_UART1_BASE, 1024, IORESOURCE_MEM_8BIT, &serial_plat);
> +	return 0;
> +}
> +
> +console_initcall(ixp4xx_console_init);
> +
> +#endif /* CONFIG_DRIVER_SERIAL_NS16550 */
> diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h
> new file mode 100644
> index 0000000..3de021e
> --- /dev/null
> +++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h
> @@ -0,0 +1,70 @@
> +/*
> + * arch/arm/mach-ixp4xx/include/mach/cpu.h
> + *
> + * IXP4XX cpu type detection
> + *
> + * Copyright (C) 2007 MontaVista Software, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#ifndef __ASM_ARCH_CPU_H__
> +#define __ASM_ARCH_CPU_H__
> +
> +#include <linux/types.h>
> +
> +/* Processor id value in CP15 Register 0 */
> +#define IXP42X_PROCESSOR_ID_VALUE 0x690541c0 /* including unused 0x690541Ex */
> +#define IXP42X_PROCESSOR_ID_MASK  0xffffffc0
> +
> +#define IXP43X_PROCESSOR_ID_VALUE 0x69054040
> +#define IXP43X_PROCESSOR_ID_MASK  0xfffffff0
> +
> +#define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */
> +#define IXP46X_PROCESSOR_ID_MASK  0xfffffff0
> +
> +#define cpu_is_ixp42x_rev_a0() ((read_cpuid_id() & (IXP42X_PROCESSOR_ID_MASK | 0xF)) == \
> +				IXP42X_PROCESSOR_ID_VALUE)
> +#define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \
> +			 IXP42X_PROCESSOR_ID_VALUE)
> +#define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \
> +			 IXP43X_PROCESSOR_ID_VALUE)
> +#define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \
> +			 IXP46X_PROCESSOR_ID_VALUE)
> +
> +/*
> + * The CPU ID never changes at run time, so we might as well tell the
> + * compiler that it's constant.  Use this function to read the CPU ID
> + * rather than directly reading processor_id or read_cpuid() directly.
> + */
> +static inline u32 __attribute_const__ read_cpuid_id(void)
> +{
> +	u32 val;
> +	asm("mrc p15, 0, %0, c0, c0, 0" : "=r" (val) : : "cc");
> +
> +	return val;
> +}

We already have this function. Please do not duplicate.

> +
> +static inline u32 ixp4xx_read_feature_bits(void)
> +{
> +	u32 val = ~IXP4XX_EXP_CFG2;
> +
> +	if (cpu_is_ixp42x_rev_a0())
> +		return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
> +					       IXP4XX_FEATURE_AES);
> +	if (cpu_is_ixp42x())
> +		return val & IXP42X_FEATURE_MASK;
> +	if (cpu_is_ixp43x())
> +		return val & IXP43X_FEATURE_MASK;
> +	return val & IXP46X_FEATURE_MASK;
> +}
> +
> +static inline void ixp4xx_write_feature_bits(u32 value)
> +{
> +	IXP4XX_EXP_CFG2 = ~value;
> +}
> +
> +#endif  /* _ASM_ARCH_CPU_H */
> diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-head.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-head.h
> new file mode 100644
> index 0000000..b3d357f
> --- /dev/null
> +++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-head.h
> @@ -0,0 +1,16 @@
> +#include <mach/ixp4xx-regs.h>
> +#include <asm/barebox-arm-head.h>
> +
> +.macro	ixp4xx_cpu_lowlevel_init
> +
> +	arm_cpu_lowlevel_init r0
> +
> +	add pc, #(0x50000000 - 4) /* jump to ROM area */
> +
> +	mov r0, #(IXP4XX_EXP_CFG0 & 0xFFFF0000)
> +	orr r0, #(IXP4XX_EXP_CFG0 & 0x0000FFFF)
> +	ldr r1, [r0]
> +	and r1, r1, #~0x80000000 /* unmap EXP bus from 0x0 */
> +	str r1, [r0]
> +
> +.endm

[...]

> +
> +static struct npe npe_tab[NPE_COUNT] = {
> +	{
> +		.regs = (struct npe_regs *)IXP4XX_NPEA_BASE,
> +		.id = 0,
> +		.name = "NPE-A",
> +	}, {
> +		.regs = (struct npe_regs *)IXP4XX_NPEB_BASE,
> +		.id = 1,
> +		.name = "NPE-B",
> +	}, {
> +		.regs = (struct npe_regs *)IXP4XX_NPEC_BASE,
> +		.id = 2,
> +		.name = "NPE-C",
> +	}
> +};

#define NPE_COUNT ARRAY_SIZE(npe_tab)?

Sascha

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