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Date: Mon, 6 May 2013 16:07:56 +0200
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Errors-To: barebox-bounces+u.kleine-koenig=pengutronix.de@lists.infradead.org
Subject: Re: [PATCH 4/7] arm: initial support for Marvell Armada 370/XP SoCs
To: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Lior Amsalem <alior@marvell.com>, barebox@lists.infradead.org, Ezequiel Garcia <ezequiel.garcia@free-electrons.com>, Willy Tarreau <w@1wt.eu>
On 16:09 Mon 06 May , Thomas Petazzoni wrote:
> Sascha, Jean-Christophe,
>
> I have one question below regarding the SoC code.
>
> On Fri, 3 May 2013 18:51:08 +0200, Thomas Petazzoni wrote:
> > +static inline void mvebu_memory_find(unsigned long *phys_base,
> > + unsigned long *phys_size)
> > +{
> > + void __iomem *sdram_win = IOMEM(MVEBU_SDRAM_WIN_BASE);
> > + int cs;
>
>
> Here...
>
> > + *phys_base = ~0;
> > + *phys_size = 0;
> > +
> > + for (cs = 0; cs < 4; cs++) {
> > + uint32_t base = readl(sdram_win + DDR_BASE_CS_OFF(cs));
> > + uint32_t ctrl = readl(sdram_win + DDR_SIZE_CS_OFF(cs));
>
> ... here ...
>
>
> > +#if defined(CONFIG_ARCH_ARMADA_370)
> > +static int mvebu_init_clocks(void)
> > +{
> > + uint32_t val;
> > + unsigned int rate;
> > + void __iomem *sar = IOMEM(MVEBU_SAR_BASE) + SAR_LOW_REG_OFF;
> > +
> > + val = readl(sar);
>
> ... and here, I'm directly poking at physical addresses, but it seems
> like Barebox can run with the MMU enabled. Should I be mapping those
> registers before accessing them? I see that drivers use
> dev_request_mem_region(), but this clock and memory code isn't (yet?) a
> driver per-se.
no as only the ddr is cached but the dev_request_mem_region track who request
what yes please create a device/drivers as you will be able to probe a dt
(even builtin) in this case
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