[RFC only] ARM: i.MX: Fix SDRAM size detect

[RFC only] ARM: i.MX: Fix SDRAM size detect

[Alexander Shiyan]

This is a trying to fix problem described in:
http://lists.infradead.org/pipermail/barebox/2013-April/014182.html

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
---
 arch/arm/mach-imx/esdctl.c | 13 ++-----------
 arch/arm/mach-imx/imx51.c  | 21 +++++++++++++++++++++
 2 files changed, 23 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index cb57d45..bde02fd 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -345,7 +345,7 @@ static int imx_esdctl_init(void)
 	return platform_driver_register(&imx_serial_driver);
 }
 
-mem_initcall(imx_esdctl_init);
+//mem_initcall(imx_esdctl_init);
 
 /*
  * The i.MX SoCs usually have two SDRAM chipselects. The following
@@ -435,16 +435,7 @@ void __naked __noreturn imx35_barebox_entry(uint32_t boarddata)
 
 void __naked __noreturn imx51_barebox_entry(uint32_t boarddata)
 {
-	unsigned long base;
-	unsigned long size;
-
-	base = MX51_CSD0_BASE_ADDR;
-
-	size = imx_v3_sdram_size((void *)MX51_ESDCTL_BASE_ADDR, 0);
-	if (size == SZ_256M)
-		size += imx_v3_sdram_size((void *)MX51_ESDCTL_BASE_ADDR, 1);
-
-	barebox_arm_entry(base, size, boarddata);
+	barebox_arm_entry(MX51_CSD0_BASE_ADDR, SZ_128M, boarddata);
 }
 
 void __naked __noreturn imx53_barebox_entry(uint32_t boarddata)
diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c
index 54d99a4..6593b7d 100644
--- a/arch/arm/mach-imx/imx51.c
+++ b/arch/arm/mach-imx/imx51.c
@@ -21,6 +21,8 @@
 #include <mach/revision.h>
 #include <mach/clock-imx51_53.h>
 #include <mach/generic.h>
+#include <mach/esdctl.h>
+#include <asm/memory.h>
 
 #define SI_REV 0x48
 
@@ -76,6 +78,25 @@ static int imx51_init(void)
 }
 postcore_initcall(imx51_init);
 
+static int imx51_memory_init(void)
+{
+	void __iomem *esdctl = IOMEM(MX51_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
+	unsigned long add, size = SZ_128M;
+
+	add = get_ram_size((ulong *)(MX51_CSD0_BASE_ADDR + SZ_128M), SZ_128M);
+	if (add) {
+		size += add;
+		if (readl(esdctl) & ESDCTL0_SDE)
+			size += get_ram_size((ulong *)MX51_CSD1_BASE_ADDR, SZ_256M);
+
+	}
+
+	arm_add_mem_device("ram0", MX51_CSD0_BASE_ADDR, size);
+
+	return 0;
+}
+mem_initcall(imx51_memory_init);
+
 /*
  * Saves the boot source media into the $bootsource environment variable
  *
-- 
1.8.1.5


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Re: [RFC only] ARM: i.MX: Fix SDRAM size detect

[Sascha Hauer]

On Fri, Apr 26, 2013 at 02:21:54PM +0400, Alexander Shiyan wrote:
> This is a trying to fix problem described in:
> http://lists.infradead.org/pipermail/barebox/2013-April/014182.html

Sorry, can you explain what the problem is and how this patch fixes
that?
How I understood it the problem was that your board had the second chip
select enabled without having sdram connected there leading to a wrong
size detection.

>  void __naked __noreturn imx51_barebox_entry(uint32_t boarddata)
>  {
> -	unsigned long base;
> -	unsigned long size;
> -
> -	base = MX51_CSD0_BASE_ADDR;
> -
> -	size = imx_v3_sdram_size((void *)MX51_ESDCTL_BASE_ADDR, 0);
> -	if (size == SZ_256M)
> -		size += imx_v3_sdram_size((void *)MX51_ESDCTL_BASE_ADDR, 1);
> -
> -	barebox_arm_entry(base, size, boarddata);
> +	barebox_arm_entry(MX51_CSD0_BASE_ADDR, SZ_128M, boarddata);
>  }

Here SDRAM size detection is disabled completely and instead 128Mib is
assumed.

>  
> +static int imx51_memory_init(void)
> +{
> +	void __iomem *esdctl = IOMEM(MX51_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
> +	unsigned long add, size = SZ_128M;
> +
> +	add = get_ram_size((ulong *)(MX51_CSD0_BASE_ADDR + SZ_128M), SZ_128M);

Ok, I think the intention here is to test whether we actually have more
than 128Mib. This won't work. get_ram_size works by detecting where in
memory we have mirrored regions. So in case you have 128Mib of real
memory you will detect 128Mib above not knowing that you test the
mirrored region of your actual memory.

> +	if (add) {
> +		size += add;
> +		if (readl(esdctl) & ESDCTL0_SDE)
> +			size += get_ram_size((ulong *)MX51_CSD1_BASE_ADDR, SZ_256M);
> +
> +	}
> +
> +	arm_add_mem_device("ram0", MX51_CSD0_BASE_ADDR, size);

With this patch you imply that imx_v3_sdram_size does not work which was
never mentioned in the thread you reference.

Can you please post:

- Which values the sdram controller is programmed with
- How much memory you really have
- what barebox detects

Sascha

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Re[2]: [RFC only] ARM: i.MX: Fix SDRAM size detect

[Alexander Shiyan]

> On Fri, Apr 26, 2013 at 02:21:54PM +0400, Alexander Shiyan wrote:
> > This is a trying to fix problem described in:
> > http://lists.infradead.org/pipermail/barebox/2013-April/014182.html
> 
> Sorry, can you explain what the problem is and how this patch fixes
> that?
> How I understood it the problem was that your board had the second chip
> select enabled without having sdram connected there leading to a wrong
> size detection.
...
> > +	arm_add_mem_device("ram0", MX51_CSD0_BASE_ADDR, size);
> 
> With this patch you imply that imx_v3_sdram_size does not work which was
> never mentioned in the thread you reference.
> 
> Can you please post:
> 
> - Which values the sdram controller is programmed with
> - How much memory you really have
> - what barebox detects

Values for ESDCTL is programmed by DCD-data from flash_header.
Currently both channels are enabled and configured to 256M.
Barebox is NOT detect size of memory, it just a read back these values.
At least on every i.MX51 this is not works correctly. In any words:
How much we specify in flash_header, this is our "detected" size.
I have a two modules (256M and 512M), barebox works when I
manually disable second SDRAM bank and of course say me
256M on both modules.

In the patch I am just choose 128M as safe size, then add additional
banks. Of course this is wrong if we have repeated memory and/or
holes, but I cannot see any other way at now...

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Re: [RFC only] ARM: i.MX: Fix SDRAM size detect

[Sascha Hauer]

On Fri, Apr 26, 2013 at 03:12:56PM +0400, Alexander Shiyan wrote:
> > On Fri, Apr 26, 2013 at 02:21:54PM +0400, Alexander Shiyan wrote:
> > > This is a trying to fix problem described in:
> > > http://lists.infradead.org/pipermail/barebox/2013-April/014182.html
> > 
> > Sorry, can you explain what the problem is and how this patch fixes
> > that?
> > How I understood it the problem was that your board had the second chip
> > select enabled without having sdram connected there leading to a wrong
> > size detection.
> ...
> > > +	arm_add_mem_device("ram0", MX51_CSD0_BASE_ADDR, size);
> > 
> > With this patch you imply that imx_v3_sdram_size does not work which was
> > never mentioned in the thread you reference.
> > 
> > Can you please post:
> > 
> > - Which values the sdram controller is programmed with
> > - How much memory you really have
> > - what barebox detects
> 
> Values for ESDCTL is programmed by DCD-data from flash_header.

Yes, that happens on most i.MX using DCD data

> Currently both channels are enabled and configured to 256M.
> Barebox is NOT detect size of memory, it just a read back these values.

Yes.

> At least on every i.MX51 this is not works correctly. In any words:
> How much we specify in flash_header, this is our "detected" size.

Yes.

> I have a two modules (256M and 512M),

How is the layout? for 256M do you have a single chipselect with 256M or
two chipselects with 128M each?

Can you please post the output of:

md 0x83fd9000+0x10

Sascha

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Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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Re[2]: [RFC only] ARM: i.MX: Fix SDRAM size detect

[Alexander Shiyan]

> > > On Fri, Apr 26, 2013 at 02:21:54PM +0400, Alexander Shiyan wrote:
> > > > This is a trying to fix problem described in:
> > > > http://lists.infradead.org/pipermail/barebox/2013-April/014182.html
> > > 
> > > Sorry, can you explain what the problem is and how this patch fixes
> > > that?
> > > How I understood it the problem was that your board had the second chip
> > > select enabled without having sdram connected there leading to a wrong
> > > size detection.
> > ...
> > > > +	arm_add_mem_device("ram0", MX51_CSD0_BASE_ADDR, size);
> > > 
> > > With this patch you imply that imx_v3_sdram_size does not work which was
> > > never mentioned in the thread you reference.
> > > 
> > > Can you please post:
> > > 
> > > - Which values the sdram controller is programmed with
> > > - How much memory you really have
> > > - what barebox detects
> > 
> > Values for ESDCTL is programmed by DCD-data from flash_header.
> 
> Yes, that happens on most i.MX using DCD data
> 
> > Currently both channels are enabled and configured to 256M.
> > Barebox is NOT detect size of memory, it just a read back these values.
> 
> Yes.
> 
> > At least on every i.MX51 this is not works correctly. In any words:
> > How much we specify in flash_header, this is our "detected" size.
> 
> Yes.
> 
> > I have a two modules (256M and 512M),
> 
> How is the layout? for 256M do you have a single chipselect with 256M or
> two chipselects with 128M each?

Single chipselect on 256M module. I.e. second is unused.

> Can you please post the output of:
> 
> md 0x83fd9000+0x10

Values exactly same as in flash_header. 
barebox@ConnectCore i.MX51:/ md 0x83fd9000+0x10
83fd9000: b2a20000 3f3584ab b2a20000 3f3584ab                ......5?......5?

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[PATCH] Fix ccxmx51 SDRAM size detection

[Sascha Hauer]

Hi Alexander,

The following hopefully fixes your boards. I'm not that happy with
the solution, but I can't think of something better.

Sorry for the inconvenience.

Sascha


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[PATCH 1/2] ARM: i.MX: Allow disabling SDRAM autodetection

[Sascha Hauer]

Some boards setup more memory than they actually have. The real memory
size can then be detected later for example by reading a board id.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-imx/esdctl.c              | 14 ++++++++++++++
 arch/arm/mach-imx/include/mach/esdctl.h |  1 +
 2 files changed, 15 insertions(+)

diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index cb57d45..e2025b3 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -39,6 +39,17 @@ struct imx_esdctl_data {
 	void (*add_mem)(void *esdctlbase, struct imx_esdctl_data *);
 };
 
+static int imx_esdctl_disabled;
+
+/*
+ * Boards can disable SDRAM detection if it doesn't work for them. In
+ * this case arm_add_mem_device has to be called by board code.
+ */
+void imx_esdctl_disable(void)
+{
+	imx_esdctl_disabled = 1;
+}
+
 /*
  * v1 - found on i.MX1
  */
@@ -239,6 +250,9 @@ static int imx_esdctl_probe(struct device_d *dev)
 	if (!base)
 		return -ENOMEM;
 
+	if (imx_esdctl_disabled)
+		return 0;
+
 	data->add_mem(base, data);
 
 	return 0;
diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h
index 26436d9..b7219d9 100644
--- a/arch/arm/mach-imx/include/mach/esdctl.h
+++ b/arch/arm/mach-imx/include/mach/esdctl.h
@@ -136,6 +136,7 @@ void __naked __noreturn imx35_barebox_entry(uint32_t boarddata);
 void __naked __noreturn imx51_barebox_entry(uint32_t boarddata);
 void __naked __noreturn imx53_barebox_entry(uint32_t boarddata);
 void __naked __noreturn imx6_barebox_entry(uint32_t boarddata);
+void imx_esdctl_disable(void);
 #endif
 
 #endif /* __MACH_ESDCTL_V2_H */
-- 
1.8.2.rc2


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[PATCH 2/2] ARM: i.MX: ccxmx51: detect SDRAM size by board id

[Sascha Hauer]

This partly reverts:

commit 697e02b74fddd80527e8ababba10239c83dba029
Author: Alexander Shiyan <shc_work@mail.ru>
Date:   Tue Jan 22 15:08:31 2013 +0400

    ARM: ccmx51: Remove SDRAM size settings

    This patch removes SDRAM memory size setting from board due
    to auto detect last one by ESDCTL.

    Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
    Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

The board originally configured the SDRAM controller for the
maximum size and detected the usable SDRAM size by reading the
board id. This became broken after switching to automatic SDRAM
size detection by reading back ESDCTL values.

This patch brings back the old behaviour.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/ccxmx51/ccxmx51.c  | 55 ++++++++++++++++++++++++--------------
 arch/arm/boards/ccxmx51/ccxmx51.h  |  1 +
 arch/arm/boards/ccxmx51/lowlevel.c |  4 ++-
 3 files changed, 39 insertions(+), 21 deletions(-)

diff --git a/arch/arm/boards/ccxmx51/ccxmx51.c b/arch/arm/boards/ccxmx51/ccxmx51.c
index a14c9bc..d20cb3b 100644
--- a/arch/arm/boards/ccxmx51/ccxmx51.c
+++ b/arch/arm/boards/ccxmx51/ccxmx51.c
@@ -46,30 +46,31 @@
 #include <mach/clock-imx51_53.h>
 #include <mach/imx5.h>
 #include <mach/revision.h>
+#include <mach/esdctl.h>
 
 #include "ccxmx51.h"
 
 static struct ccxmx51_ident ccxmx51_ids[] = {
-/* 0x00 */	{ "Unknown",						0, 0, 0, 0 },
-/* 0x01 */	{ "Not supported",					0, 0, 0, 0 },
-/* 0x02 */	{ "i.MX515@800MHz, Wireless, PHY, Ext. Eth, Accel",	0, 1, 1, 1 },
-/* 0x03 */	{ "i.MX515@800MHz, PHY, Ext. Eth, Accel",		0, 1, 1, 0 },
-/* 0x04 */	{ "i.MX515@600MHz, Wireless, PHY, Ext. Eth, Accel",	1, 1, 1, 1 },
-/* 0x05 */	{ "i.MX515@600MHz, PHY, Ext. Eth, Accel",		1, 1, 1, 0 },
-/* 0x06 */	{ "i.MX515@800MHz, Wireless, PHY, Accel",		0, 1, 0, 1 },
-/* 0x07 */	{ "i.MX515@800MHz, PHY, Accel",				0, 1, 0, 0 },
-/* 0x08 */	{ "i.MX515@800MHz, Wireless, PHY, Accel",		0, 1, 0, 1 },
-/* 0x09 */	{ "i.MX515@800MHz, PHY, Accel",				0, 1, 0, 0 },
-/* 0x0a */	{ "i.MX515@600MHz, Wireless, PHY, Accel",		1, 1, 0, 1 },
-/* 0x0b */	{ "i.MX515@600MHz, PHY, Accel",				1, 1, 0, 0 },
-/* 0x0c */	{ "i.MX515@800MHz, Wireless, PHY, Accel",		0, 1, 0, 1 },
-/* 0x0d */	{ "i.MX512@800MHz",					0, 0, 0, 0 },
-/* 0x0e */	{ "i.MX515@800MHz, Wireless, PHY, Accel",		0, 1, 0, 1 },
-/* 0x0f */	{ "i.MX515@600MHz, PHY, Accel",				1, 1, 0, 0 },
-/* 0x10 */	{ "i.MX515@600MHz, Wireless, PHY, Accel",		1, 1, 0, 1 },
-/* 0x11 */	{ "i.MX515@800MHz, PHY, Accel",				0, 1, 0, 0 },
-/* 0x12 */	{ "i.MX515@600MHz, Wireless, PHY, Accel",		1, 1, 0, 1 },
-/* 0x13 */	{ "i.MX515@800MHz, PHY, Accel",				0, 1, 0, 0 },
+/* 0x00 */	{ "Unknown",						0,       0, 0, 0, 0 },
+/* 0x01 */	{ "Not supported",					0,       0, 0, 0, 0 },
+/* 0x02 */	{ "i.MX515@800MHz, Wireless, PHY, Ext. Eth, Accel",	SZ_512M, 0, 1, 1, 1 },
+/* 0x03 */	{ "i.MX515@800MHz, PHY, Ext. Eth, Accel",		SZ_512M, 0, 1, 1, 0 },
+/* 0x04 */	{ "i.MX515@600MHz, Wireless, PHY, Ext. Eth, Accel",	SZ_512M, 1, 1, 1, 1 },
+/* 0x05 */	{ "i.MX515@600MHz, PHY, Ext. Eth, Accel",		SZ_512M, 1, 1, 1, 0 },
+/* 0x06 */	{ "i.MX515@800MHz, Wireless, PHY, Accel",		SZ_512M, 0, 1, 0, 1 },
+/* 0x07 */	{ "i.MX515@800MHz, PHY, Accel",				SZ_512M, 0, 1, 0, 0 },
+/* 0x08 */	{ "i.MX515@800MHz, Wireless, PHY, Accel",		SZ_256M, 0, 1, 0, 1 },
+/* 0x09 */	{ "i.MX515@800MHz, PHY, Accel",				SZ_256M, 0, 1, 0, 0 },
+/* 0x0a */	{ "i.MX515@600MHz, Wireless, PHY, Accel",		SZ_256M, 1, 1, 0, 1 },
+/* 0x0b */	{ "i.MX515@600MHz, PHY, Accel",				SZ_256M, 1, 1, 0, 0 },
+/* 0x0c */	{ "i.MX515@800MHz, Wireless, PHY, Accel",		SZ_128M, 0, 1, 0, 1 },
+/* 0x0d */	{ "i.MX512@800MHz",					SZ_128M, 0, 0, 0, 0 },
+/* 0x0e */	{ "i.MX515@800MHz, Wireless, PHY, Accel",		SZ_512M, 0, 1, 0, 1 },
+/* 0x0f */	{ "i.MX515@600MHz, PHY, Accel",				SZ_128M, 1, 1, 0, 0 },
+/* 0x10 */	{ "i.MX515@600MHz, Wireless, PHY, Accel",		SZ_128M, 1, 1, 0, 1 },
+/* 0x11 */	{ "i.MX515@800MHz, PHY, Accel",				SZ_128M, 0, 1, 0, 0 },
+/* 0x12 */	{ "i.MX515@600MHz, Wireless, PHY, Accel",		SZ_512M, 1, 1, 0, 1 },
+/* 0x13 */	{ "i.MX515@800MHz, PHY, Accel",				SZ_512M, 0, 1, 0, 0 },
 };
 
 struct ccxmx51_ident *ccxmx51_id;
@@ -338,6 +339,18 @@ static int ccxmx51_power_init(void)
 	return 0;
 }
 
+/*
+ * On this board the SDRAM is always configured for 512Mib. The real
+ * size is determined by the board id read from the IIM module.
+ */
+static int ccxm51_sdram_fixup(void)
+{
+	imx_esdctl_disable();
+
+	return 0;
+}
+postcore_initcall(ccxm51_sdram_fixup);
+
 static int ccxmx51_devices_init(void)
 {
 	u8 hwid[6];
@@ -367,6 +380,8 @@ static int ccxmx51_devices_init(void)
 			break;
 		}
 		printf("Module Serial : %c%d\n", manloc, ((hwid[2] & 0x3f) << 24) | (hwid[3] << 16) | (hwid[4] << 8) | hwid[5]);
+		if ((ccxmx51_id->mem_sz - SZ_128M) > 0)
+			arm_add_mem_device("ram1", MX51_CSD0_BASE_ADDR + SZ_128M, ccxmx51_id->mem_sz - SZ_128M);
 	}
 
 	imx51_add_uart1();
diff --git a/arch/arm/boards/ccxmx51/ccxmx51.h b/arch/arm/boards/ccxmx51/ccxmx51.h
index ef40b7f..3feacac 100644
--- a/arch/arm/boards/ccxmx51/ccxmx51.h
+++ b/arch/arm/boards/ccxmx51/ccxmx51.h
@@ -23,6 +23,7 @@ struct ccxmx51_hwid {
 
 struct ccxmx51_ident {
 	const char	*id_string;
+	const int	mem_sz;
 	const char	industrial;
 	const char	eth0;
 	const char	eth1;
diff --git a/arch/arm/boards/ccxmx51/lowlevel.c b/arch/arm/boards/ccxmx51/lowlevel.c
index 3e6a0ee..9519b77 100644
--- a/arch/arm/boards/ccxmx51/lowlevel.c
+++ b/arch/arm/boards/ccxmx51/lowlevel.c
@@ -1,9 +1,11 @@
 #include <common.h>
 #include <mach/esdctl.h>
+#include <asm/barebox-arm.h>
 #include <asm/barebox-arm-head.h>
+#include <mach/imx51-regs.h>
 
 void __naked barebox_arm_reset_vector(void)
 {
 	arm_cpu_lowlevel_init();
-	imx51_barebox_entry(0);
+	barebox_arm_entry(MX51_CSD0_BASE_ADDR, SZ_128M, 0);
 }
-- 
1.8.2.rc2


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Re: [PATCH] Fix ccxmx51 SDRAM size detection

[Alexander Shiyan]

> The following hopefully fixes your boards. I'm not that happy with
> the solution, but I can't think of something better.
> 
> Sorry for the inconvenience.

Yes, patchset is may help here. I can test this in a few days.
Unfortunately, some other boards can have an option
for different memory size, so I will try to create non-destructive
(and safe) algorithg to test memory as replacement of get_mem_size.
Thanks.

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Re: [PATCH 2/2] ARM: i.MX: ccxmx51: detect SDRAM size by board id

[Alexander Shiyan]

> This partly reverts:
> 
> commit 697e02b74fddd80527e8ababba10239c83dba029
> Author: Alexander Shiyan <shc_work@mail.ru>
> Date:   Tue Jan 22 15:08:31 2013 +0400
> 
>     ARM: ccmx51: Remove SDRAM size settings
> 
>     This patch removes SDRAM memory size setting from board due
>     to auto detect last one by ESDCTL.
> 
>     Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
>     Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> 
> The board originally configured the SDRAM controller for the
> maximum size and detected the usable SDRAM size by reading the
> board id. This became broken after switching to automatic SDRAM
> size detection by reading back ESDCTL values.
> 
> This patch brings back the old behaviour.

Please, apply both to git.
Thanks.

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Re: [PATCH 2/2] ARM: i.MX: ccxmx51: detect SDRAM size by board id

[Jean-Christophe PLAGNIOL-VILLARD]

>  static int ccxmx51_devices_init(void)
>  {
>  	u8 hwid[6];
> @@ -367,6 +380,8 @@ static int ccxmx51_devices_init(void)
>  			break;
>  		}
>  		printf("Module Serial : %c%d\n", manloc, ((hwid[2] & 0x3f) << 24) | (hwid[3] << 16) | (hwid[4] << 8) | hwid[5]);
> +		if ((ccxmx51_id->mem_sz - SZ_128M) > 0)
> +			arm_add_mem_device("ram1", MX51_CSD0_BASE_ADDR + SZ_128M, ccxmx51_id->mem_sz - SZ_128M);
>  	}
>  
>  	imx51_add_uart1();
> diff --git a/arch/arm/boards/ccxmx51/ccxmx51.h b/arch/arm/boards/ccxmx51/ccxmx51.h
> index ef40b7f..3feacac 100644
> --- a/arch/arm/boards/ccxmx51/ccxmx51.h
> +++ b/arch/arm/boards/ccxmx51/ccxmx51.h
> @@ -23,6 +23,7 @@ struct ccxmx51_hwid {
>  
>  struct ccxmx51_ident {
>  	const char	*id_string;
> +	const int	mem_sz;
>  	const char	industrial;
>  	const char	eth0;
>  	const char	eth1;
> diff --git a/arch/arm/boards/ccxmx51/lowlevel.c b/arch/arm/boards/ccxmx51/lowlevel.c
> index 3e6a0ee..9519b77 100644
> --- a/arch/arm/boards/ccxmx51/lowlevel.c
> +++ b/arch/arm/boards/ccxmx51/lowlevel.c
> @@ -1,9 +1,11 @@
>  #include <common.h>
>  #include <mach/esdctl.h>
> +#include <asm/barebox-arm.h>
>  #include <asm/barebox-arm-head.h>
> +#include <mach/imx51-regs.h>
>  
>  void __naked barebox_arm_reset_vector(void)
>  {
>  	arm_cpu_lowlevel_init();
> -	imx51_barebox_entry(0);
> +	barebox_arm_entry(MX51_CSD0_BASE_ADDR, SZ_128M, 0);

can we fix the ddr ctrl here by detecting the hw earlier
>  }
> -- 
> 1.8.2.rc2
> 
> 
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Re[2]: [PATCH 2/2] ARM: i.MX: ccxmx51: detect SDRAM size by board id

[Alexander Shiyan]

...
> >  void __naked barebox_arm_reset_vector(void)
> >  {
> >  	arm_cpu_lowlevel_init();
> > -	imx51_barebox_entry(0);
> > +	barebox_arm_entry(MX51_CSD0_BASE_ADDR, SZ_128M, 0);
> 
> can we fix the ddr ctrl here by detecting the hw earlier

IIM is needed for detection. So it not possible.

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Re: [PATCH 2/2] ARM: i.MX: ccxmx51: detect SDRAM size by board id

[Jean-Christophe PLAGNIOL-VILLARD]

On 16:46 Tue 07 May     , Alexander Shiyan wrote:
> ...
> > >  void __naked barebox_arm_reset_vector(void)
> > >  {
> > >  	arm_cpu_lowlevel_init();
> > > -	imx51_barebox_entry(0);
> > > +	barebox_arm_entry(MX51_CSD0_BASE_ADDR, SZ_128M, 0);
> > 
> > can we fix the ddr ctrl here by detecting the hw earlier
> 
> IIM is needed for detection. So it not possible.
IIM is just register to read

Best REgards,
J.

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Re: [PATCH 2/2] ARM: i.MX: ccxmx51: detect SDRAM size by board id

[Sascha Hauer]

On Tue, May 07, 2013 at 03:45:04PM +0400, Alexander Shiyan wrote:
> > This partly reverts:
> > 
> > commit 697e02b74fddd80527e8ababba10239c83dba029
> > Author: Alexander Shiyan <shc_work@mail.ru>
> > Date:   Tue Jan 22 15:08:31 2013 +0400
> > 
> >     ARM: ccmx51: Remove SDRAM size settings
> > 
> >     This patch removes SDRAM memory size setting from board due
> >     to auto detect last one by ESDCTL.
> > 
> >     Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
> >     Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > 
> > The board originally configured the SDRAM controller for the
> > maximum size and detected the usable SDRAM size by reading the
> > board id. This became broken after switching to automatic SDRAM
> > size detection by reading back ESDCTL values.
> > 
> > This patch brings back the old behaviour.
> 
> Please, apply both to git.

Did that.

Sascha


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