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* [PATCH] omap4: set voltage according to mpu freq
@ 2013-05-28 11:51 Jan Weitzel
  2013-05-30  9:39 ` Sascha Hauer
  0 siblings, 1 reply; 7+ messages in thread
From: Jan Weitzel @ 2013-05-28 11:51 UTC (permalink / raw)
  To: barebox

For OMAP4460 omap4_scale_vcores must set the voltage according to mpu freq.

OPP100  700MHz 1210mV
OPPTB   920MHz 1320mV
OPPNT  1200MHz 1380mV

Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
---
 arch/arm/boards/archosg9/lowlevel.c             |    2 +-
 arch/arm/boards/panda/lowlevel.c                |    2 +-
 arch/arm/boards/pcm049/lowlevel.c               |    2 +-
 arch/arm/boards/phycard-a-xl2/lowlevel.c        |    2 +-
 arch/arm/mach-omap/include/mach/omap4-silicon.h |    2 +-
 arch/arm/mach-omap/omap4_generic.c              |    6 +++---
 6 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boards/archosg9/lowlevel.c b/arch/arm/boards/archosg9/lowlevel.c
index 0334693..0fae6da 100644
--- a/arch/arm/boards/archosg9/lowlevel.c
+++ b/arch/arm/boards/archosg9/lowlevel.c
@@ -49,7 +49,7 @@ static noinline void archosg9_init_lowlevel(void)
 	set_muxconf_regs();
 
 	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
-	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
+	omap4_scale_vcores(TPS62361_VSEL0_GPIO, 1380);
 
 	/* Enable all clocks */
 	omap4_enable_all_clocks();
diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c
index ed1dc6f..591ff2f 100644
--- a/arch/arm/boards/panda/lowlevel.c
+++ b/arch/arm/boards/panda/lowlevel.c
@@ -70,7 +70,7 @@ static void noinline panda_init_lowlevel(void)
 	omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core);
 
 	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
-	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
+	omap4_scale_vcores(TPS62361_VSEL0_GPIO, 1210);
 }
 
 void barebox_arm_reset_vector(void)
diff --git a/arch/arm/boards/pcm049/lowlevel.c b/arch/arm/boards/pcm049/lowlevel.c
index 33519f7..8548868 100644
--- a/arch/arm/boards/pcm049/lowlevel.c
+++ b/arch/arm/boards/pcm049/lowlevel.c
@@ -109,7 +109,7 @@ static void noinline pcm049_init_lowlevel(void)
 #endif
 
 	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
-	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
+	omap4_scale_vcores(TPS62361_VSEL0_GPIO, 1320);
 
 	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
 
diff --git a/arch/arm/boards/phycard-a-xl2/lowlevel.c b/arch/arm/boards/phycard-a-xl2/lowlevel.c
index 07505ff..3750bae 100644
--- a/arch/arm/boards/phycard-a-xl2/lowlevel.c
+++ b/arch/arm/boards/phycard-a-xl2/lowlevel.c
@@ -58,7 +58,7 @@ static noinline void pcaaxl2_init_lowlevel(void)
 	omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
 
 	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
-	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
+	omap4_scale_vcores(TPS62361_VSEL0_GPIO, 1320);
 
 	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
 
diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
index 9e82435..5684a38 100644
--- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
+++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
@@ -211,7 +211,7 @@ struct dpll_param;
 void omap4_ddr_init(const struct ddr_regs *, const struct dpll_param *);
 void omap4_power_i2c_send(u32);
 unsigned int omap4_revision(void);
-noinline int omap4_scale_vcores(unsigned vsel0_pin);
+noinline int omap4_scale_vcores(unsigned vsel0_pin, unsigned volt_mv);
 
 #endif
 
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index 38993be..1eeaf30 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -511,7 +511,7 @@ static void __iomem *omap4_get_gpio_base(unsigned gpio)
 
 #define I2C_SLAVE 0x12
 
-noinline int omap4_scale_vcores(unsigned vsel0_pin)
+noinline int omap4_scale_vcores(unsigned vsel0_pin, unsigned volt_mv)
 {
 	void __iomem *base;
 	unsigned int rev = omap4_revision();
@@ -529,8 +529,8 @@ noinline int omap4_scale_vcores(unsigned vsel0_pin)
 		 * Setup SET1 and SET0 with right values so that kernel
 		 * can use either of them based on its needs.
 		 */
-		omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET0, 1430);
-		omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET1, 1430);
+		omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET0, volt_mv);
+		omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt_mv);
 
 		/*
 		 * Select SET1 in TPS62361:
-- 
1.7.0.4


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^ permalink raw reply	[flat|nested] 7+ messages in thread
* Re: [PATCH] omap4: set voltage according to mpu freq
  2013-05-28 11:51 [PATCH] omap4: set voltage according to mpu freq Jan Weitzel
@ 2013-05-30  9:39 ` Sascha Hauer
  2013-06-05  9:52   ` Jan Weitzel
  0 siblings, 1 reply; 7+ messages in thread
From: Sascha Hauer @ 2013-05-30  9:39 UTC (permalink / raw)
  To: Jan Weitzel; +Cc: barebox

On Tue, May 28, 2013 at 01:51:39PM +0200, Jan Weitzel wrote:
> For OMAP4460 omap4_scale_vcores must set the voltage according to mpu freq.
> 
> OPP100  700MHz 1210mV
> OPPTB   920MHz 1320mV
> OPPNT  1200MHz 1380mV
> 
> Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
> ---
>  arch/arm/boards/archosg9/lowlevel.c             |    2 +-
>  arch/arm/boards/panda/lowlevel.c                |    2 +-
>  arch/arm/boards/pcm049/lowlevel.c               |    2 +-
>  arch/arm/boards/phycard-a-xl2/lowlevel.c        |    2 +-
>  arch/arm/mach-omap/include/mach/omap4-silicon.h |    2 +-
>  arch/arm/mach-omap/omap4_generic.c              |    6 +++---
>  6 files changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm/boards/archosg9/lowlevel.c b/arch/arm/boards/archosg9/lowlevel.c
> index 0334693..0fae6da 100644
> --- a/arch/arm/boards/archosg9/lowlevel.c
> +++ b/arch/arm/boards/archosg9/lowlevel.c
> @@ -49,7 +49,7 @@ static noinline void archosg9_init_lowlevel(void)
>  	set_muxconf_regs();
>  
>  	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
> -	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
> +	omap4_scale_vcores(TPS62361_VSEL0_GPIO, 1380);
>  
>  	/* Enable all clocks */
>  	omap4_enable_all_clocks();
> diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c
> index ed1dc6f..591ff2f 100644
> --- a/arch/arm/boards/panda/lowlevel.c
> +++ b/arch/arm/boards/panda/lowlevel.c
> @@ -70,7 +70,7 @@ static void noinline panda_init_lowlevel(void)
>  	omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core);
>  
>  	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
> -	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
> +	omap4_scale_vcores(TPS62361_VSEL0_GPIO, 1210);
>  }
>  
>  void barebox_arm_reset_vector(void)
> diff --git a/arch/arm/boards/pcm049/lowlevel.c b/arch/arm/boards/pcm049/lowlevel.c
> index 33519f7..8548868 100644
> --- a/arch/arm/boards/pcm049/lowlevel.c
> +++ b/arch/arm/boards/pcm049/lowlevel.c
> @@ -109,7 +109,7 @@ static void noinline pcm049_init_lowlevel(void)
>  #endif
>  
>  	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
> -	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
> +	omap4_scale_vcores(TPS62361_VSEL0_GPIO, 1320);
>  
>  	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
>  
> diff --git a/arch/arm/boards/phycard-a-xl2/lowlevel.c b/arch/arm/boards/phycard-a-xl2/lowlevel.c
> index 07505ff..3750bae 100644
> --- a/arch/arm/boards/phycard-a-xl2/lowlevel.c
> +++ b/arch/arm/boards/phycard-a-xl2/lowlevel.c
> @@ -58,7 +58,7 @@ static noinline void pcaaxl2_init_lowlevel(void)
>  	omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
>  
>  	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
> -	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
> +	omap4_scale_vcores(TPS62361_VSEL0_GPIO, 1320);
>  
>  	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
>  
> diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
> index 9e82435..5684a38 100644
> --- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
> +++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
> @@ -211,7 +211,7 @@ struct dpll_param;
>  void omap4_ddr_init(const struct ddr_regs *, const struct dpll_param *);
>  void omap4_power_i2c_send(u32);
>  unsigned int omap4_revision(void);
> -noinline int omap4_scale_vcores(unsigned vsel0_pin);
> +noinline int omap4_scale_vcores(unsigned vsel0_pin, unsigned volt_mv);
>  
>  #endif
>  
> diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
> index 38993be..1eeaf30 100644
> --- a/arch/arm/mach-omap/omap4_generic.c
> +++ b/arch/arm/mach-omap/omap4_generic.c
> @@ -511,7 +511,7 @@ static void __iomem *omap4_get_gpio_base(unsigned gpio)
>  
>  #define I2C_SLAVE 0x12
>  
> -noinline int omap4_scale_vcores(unsigned vsel0_pin)
> +noinline int omap4_scale_vcores(unsigned vsel0_pin, unsigned volt_mv)
>  {
>  	void __iomem *base;
>  	unsigned int rev = omap4_revision();
> @@ -529,8 +529,8 @@ noinline int omap4_scale_vcores(unsigned vsel0_pin)
>  		 * Setup SET1 and SET0 with right values so that kernel
>  		 * can use either of them based on its needs.
>  		 */
> -		omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET0, 1430);
> -		omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET1, 1430);
> +		omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET0, volt_mv);
> +		omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt_mv);

This adds a parameter volt_mv which is written to some register, but
only on a omap4460.
This is all very nonobvious to me. I wonder if this setup could be
improved somehow to leave a better feeling? How about separating
omap4430 and omap4460 setup? Then maybe omap4430 wouldn't have to pass
a meaningles parameter to this function.

Sascha

-- 
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^ permalink raw reply	[flat|nested] 7+ messages in thread
* Re: [PATCH] omap4: set voltage according to mpu freq
  2013-05-30  9:39 ` Sascha Hauer
@ 2013-06-05  9:52   ` Jan Weitzel
  2013-06-06 12:47     ` [PATCH v2] " Jan Weitzel
  0 siblings, 1 reply; 7+ messages in thread
From: Jan Weitzel @ 2013-06-05  9:52 UTC (permalink / raw)
  To: Sascha Hauer; +Cc: barebox

Am Donnerstag, den 30.05.2013, 11:39 +0200 schrieb Sascha Hauer:
> On Tue, May 28, 2013 at 01:51:39PM +0200, Jan Weitzel wrote:
> > For OMAP4460 omap4_scale_vcores must set the voltage according to mpu freq.
> > 
> > OPP100  700MHz 1210mV
> > OPPTB   920MHz 1320mV
> > OPPNT  1200MHz 1380mV
> > 
> > Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
> > ---
> >  arch/arm/boards/archosg9/lowlevel.c             |    2 +-
> >  arch/arm/boards/panda/lowlevel.c                |    2 +-
> >  arch/arm/boards/pcm049/lowlevel.c               |    2 +-
> >  arch/arm/boards/phycard-a-xl2/lowlevel.c        |    2 +-
> >  arch/arm/mach-omap/include/mach/omap4-silicon.h |    2 +-
> >  arch/arm/mach-omap/omap4_generic.c              |    6 +++---
> >  6 files changed, 8 insertions(+), 8 deletions(-)
> > 
> > diff --git a/arch/arm/boards/archosg9/lowlevel.c b/arch/arm/boards/archosg9/lowlevel.c
> > index 0334693..0fae6da 100644
> > --- a/arch/arm/boards/archosg9/lowlevel.c
> > +++ b/arch/arm/boards/archosg9/lowlevel.c
> > @@ -49,7 +49,7 @@ static noinline void archosg9_init_lowlevel(void)
> >  	set_muxconf_regs();
> >  
> >  	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
> > -	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
> > +	omap4_scale_vcores(TPS62361_VSEL0_GPIO, 1380);
> >  
> >  	/* Enable all clocks */
> >  	omap4_enable_all_clocks();
> > diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c
> > index ed1dc6f..591ff2f 100644
> > --- a/arch/arm/boards/panda/lowlevel.c
> > +++ b/arch/arm/boards/panda/lowlevel.c
> > @@ -70,7 +70,7 @@ static void noinline panda_init_lowlevel(void)
> >  	omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core);
> >  
> >  	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
> > -	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
> > +	omap4_scale_vcores(TPS62361_VSEL0_GPIO, 1210);
> >  }
> >  
> >  void barebox_arm_reset_vector(void)
> > diff --git a/arch/arm/boards/pcm049/lowlevel.c b/arch/arm/boards/pcm049/lowlevel.c
> > index 33519f7..8548868 100644
> > --- a/arch/arm/boards/pcm049/lowlevel.c
> > +++ b/arch/arm/boards/pcm049/lowlevel.c
> > @@ -109,7 +109,7 @@ static void noinline pcm049_init_lowlevel(void)
> >  #endif
> >  
> >  	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
> > -	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
> > +	omap4_scale_vcores(TPS62361_VSEL0_GPIO, 1320);
> >  
> >  	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
> >  
> > diff --git a/arch/arm/boards/phycard-a-xl2/lowlevel.c b/arch/arm/boards/phycard-a-xl2/lowlevel.c
> > index 07505ff..3750bae 100644
> > --- a/arch/arm/boards/phycard-a-xl2/lowlevel.c
> > +++ b/arch/arm/boards/phycard-a-xl2/lowlevel.c
> > @@ -58,7 +58,7 @@ static noinline void pcaaxl2_init_lowlevel(void)
> >  	omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
> >  
> >  	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
> > -	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
> > +	omap4_scale_vcores(TPS62361_VSEL0_GPIO, 1320);
> >  
> >  	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
> >  
> > diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
> > index 9e82435..5684a38 100644
> > --- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
> > +++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
> > @@ -211,7 +211,7 @@ struct dpll_param;
> >  void omap4_ddr_init(const struct ddr_regs *, const struct dpll_param *);
> >  void omap4_power_i2c_send(u32);
> >  unsigned int omap4_revision(void);
> > -noinline int omap4_scale_vcores(unsigned vsel0_pin);
> > +noinline int omap4_scale_vcores(unsigned vsel0_pin, unsigned volt_mv);
> >  
> >  #endif
> >  
> > diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
> > index 38993be..1eeaf30 100644
> > --- a/arch/arm/mach-omap/omap4_generic.c
> > +++ b/arch/arm/mach-omap/omap4_generic.c
> > @@ -511,7 +511,7 @@ static void __iomem *omap4_get_gpio_base(unsigned gpio)
> >  
> >  #define I2C_SLAVE 0x12
> >  
> > -noinline int omap4_scale_vcores(unsigned vsel0_pin)
> > +noinline int omap4_scale_vcores(unsigned vsel0_pin, unsigned volt_mv)
> >  {
> >  	void __iomem *base;
> >  	unsigned int rev = omap4_revision();
> > @@ -529,8 +529,8 @@ noinline int omap4_scale_vcores(unsigned vsel0_pin)
> >  		 * Setup SET1 and SET0 with right values so that kernel
> >  		 * can use either of them based on its needs.
> >  		 */
> > -		omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET0, 1430);
> > -		omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET1, 1430);
> > +		omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET0, volt_mv);
> > +		omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt_mv);
> 
> This adds a parameter volt_mv which is written to some register, but
> only on a omap4460.
> This is all very nonobvious to me. I wonder if this setup could be
> improved somehow to leave a better feeling? How about separating
> omap4430 and omap4460 setup? Then maybe omap4430 wouldn't have to pass
> a meaningles parameter to this function.
The first parameter (gpio) is also meaningles, I send a patch which also
splits omap4_scale_vcores

Jan
> 
> Sascha
> 



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^ permalink raw reply	[flat|nested] 7+ messages in thread
* [PATCH v2] omap4: set voltage according to mpu freq
  2013-06-05  9:52   ` Jan Weitzel
@ 2013-06-06 12:47     ` Jan Weitzel
  2013-06-06 13:40       ` menon.nishanth
  0 siblings, 1 reply; 7+ messages in thread
From: Jan Weitzel @ 2013-06-06 12:47 UTC (permalink / raw)
  To: barebox

For OMAP4460 omap4_scale_vcores must set the voltage according to mpu freq.

OPP100  700MHz 1210mV
OPPTB   920MHz 1320mV
OPPNT  1200MHz 1380mV

Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
---
v2: split omap4_scale_vcores

 arch/arm/boards/archosg9/lowlevel.c             |    3 +-
 arch/arm/boards/panda/lowlevel.c                |    7 +-
 arch/arm/boards/pcm049/lowlevel.c               |    9 ++-
 arch/arm/boards/phycard-a-xl2/lowlevel.c        |    9 ++-
 arch/arm/mach-omap/include/mach/omap4-silicon.h |    3 +-
 arch/arm/mach-omap/omap4_generic.c              |   96 +++++++++++++----------
 6 files changed, 74 insertions(+), 53 deletions(-)

diff --git a/arch/arm/boards/archosg9/lowlevel.c b/arch/arm/boards/archosg9/lowlevel.c
index 0334693..49c1541 100644
--- a/arch/arm/boards/archosg9/lowlevel.c
+++ b/arch/arm/boards/archosg9/lowlevel.c
@@ -48,8 +48,7 @@ static noinline void archosg9_init_lowlevel(void)
 
 	set_muxconf_regs();
 
-	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
-	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
+	omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1380);
 
 	/* Enable all clocks */
 	omap4_enable_all_clocks();
diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c
index ed1dc6f..5d3490f 100644
--- a/arch/arm/boards/panda/lowlevel.c
+++ b/arch/arm/boards/panda/lowlevel.c
@@ -52,6 +52,7 @@ static void noinline panda_init_lowlevel(void)
 	struct dpll_param per = OMAP4_PER_DPLL_PARAM_38M4;
 	struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_38M4;
 	struct dpll_param usb = OMAP4_USB_DPLL_PARAM_38M4;
+	unsigned int rev = omap4_revision();
 
 	writel(CM_SYS_CLKSEL_38M4, CM_SYS_CLKSEL);
 
@@ -69,8 +70,10 @@ static void noinline panda_init_lowlevel(void)
 
 	omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core);
 
-	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
-	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
+	if (rev < OMAP4460_ES1_0)
+		omap4430_scale_vcores();
+	else
+		omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1210);
 }
 
 void barebox_arm_reset_vector(void)
diff --git a/arch/arm/boards/pcm049/lowlevel.c b/arch/arm/boards/pcm049/lowlevel.c
index c855bff..aa6502d 100644
--- a/arch/arm/boards/pcm049/lowlevel.c
+++ b/arch/arm/boards/pcm049/lowlevel.c
@@ -99,6 +99,7 @@ static void noinline pcm049_init_lowlevel(void)
 	struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2;
 	struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2;
 	struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2;
+	unsigned int rev = omap4_revision();
 
 	set_muxconf_regs();
 
@@ -108,13 +109,15 @@ static void noinline pcm049_init_lowlevel(void)
 	omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
 #endif
 
-	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
-	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
+	if (rev < OMAP4460_ES1_0)
+		omap4430_scale_vcores();
+	else
+		omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1320);
 
 	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
 
 	/* Configure all DPLL's */
-	if (omap4_revision() < OMAP4460_ES1_0)
+	if (rev < OMAP4460_ES1_0)
 		omap4_configure_mpu_dpll(&mpu44xx);
 	else
 		omap4_configure_mpu_dpll(&mpu4460);
diff --git a/arch/arm/boards/phycard-a-xl2/lowlevel.c b/arch/arm/boards/phycard-a-xl2/lowlevel.c
index 07505ff..86d7c51 100644
--- a/arch/arm/boards/phycard-a-xl2/lowlevel.c
+++ b/arch/arm/boards/phycard-a-xl2/lowlevel.c
@@ -52,18 +52,21 @@ static noinline void pcaaxl2_init_lowlevel(void)
 	struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2;
 	struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2;
 	struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2;
+	unsigned int rev = omap4_revision();
 
 	set_muxconf_regs();
 
 	omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
 
-	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
-	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
+	if (ref < OMAP4460_ES1_0)
+		omap4430_scale_vcores();
+	else
+		omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1320);
 
 	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
 
 	/* Configure all DPLL's at 100% OPP */
-	if (omap4_revision() < OMAP4460_ES1_0)
+	if (rev < OMAP4460_ES1_0)
 		omap4_configure_mpu_dpll(&mpu44xx);
 	else
 		omap4_configure_mpu_dpll(&mpu4460);
diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h
index 9e82435..ba48c30 100644
--- a/arch/arm/mach-omap/include/mach/omap4-silicon.h
+++ b/arch/arm/mach-omap/include/mach/omap4-silicon.h
@@ -211,7 +211,8 @@ struct dpll_param;
 void omap4_ddr_init(const struct ddr_regs *, const struct dpll_param *);
 void omap4_power_i2c_send(u32);
 unsigned int omap4_revision(void);
-noinline int omap4_scale_vcores(unsigned vsel0_pin);
+noinline int omap4430_scale_vcores(void);
+noinline int omap4460_scale_vcores(unsigned vsel0_pin, unsigned volt_mv);
 
 #endif
 
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index 3fd3a54..b5e166d 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -514,11 +514,9 @@ static void __iomem *omap4_get_gpio_base(unsigned gpio)
 
 #define I2C_SLAVE 0x12
 
-noinline int omap4_scale_vcores(unsigned vsel0_pin)
+noinline int omap4430_scale_vcores(void)
 {
-	void __iomem *base;
 	unsigned int rev = omap4_revision();
-	u32 val = 0;
 
 	/* For VC bypass only VCOREx_CGF_FORCE  is necessary and
 	 * VCOREx_CFG_VOLTAGE  changes can be discarded
@@ -526,50 +524,16 @@ noinline int omap4_scale_vcores(unsigned vsel0_pin)
 	writel(0, OMAP44XX_PRM_VC_CFG_I2C_MODE);
 	writel(0x6026, OMAP44XX_PRM_VC_CFG_I2C_CLK);
 
-	/* TPS - supplies vdd_mpu on 4460 */
-	if (rev >= OMAP4460_ES1_0) {
-		/*
-		 * Setup SET1 and SET0 with right values so that kernel
-		 * can use either of them based on its needs.
-		 */
-		omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET0, 1430);
-		omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET1, 1430);
-
-		/*
-		 * Select SET1 in TPS62361:
-		 * VSEL1 is grounded on board. So the following selects
-		 * VSEL1 = 0 and VSEL0 = 1
-		 */
-		base = omap4_get_gpio_base(vsel0_pin);
-
-		val = 1 << (vsel0_pin & GPIO_MASK);
-		writel(val, base + 0x190);
-
-		val =  readl(base + 0x134);
-		val &= ~(1 << (vsel0_pin & GPIO_MASK));
-		writel(val, base + 0x134);
-
-		val = 1 << (vsel0_pin & GPIO_MASK);
-		writel(val, base + 0x194);
-	}
-
-	/* set VCORE1 force VSEL */
-	/*
+	/* set VCORE1 force VSEL
 	 * 4430 : supplies vdd_mpu
 	 * Setting a high voltage for Nitro mode as smart reflex is not enabled.
 	 * We use the maximum possible value in the AVS range because the next
 	 * higher voltage in the discrete range (code >= 0b111010) is way too
 	 * high
-	 *
-	 * 4460 : supplies vdd_core
-	 *
 	 */
-	if (rev < OMAP4460_ES1_0)
-		/* 0x55: i2c addr, 3A: ~ 1430 mvolts*/
-		omap4_power_i2c_send((0x3A55 << 8) | I2C_SLAVE);
-	else
-		/* 0x55: i2c addr, 28: ~ 1200 mvolts*/
-		omap4_power_i2c_send((0x2855 << 8) | I2C_SLAVE);
+
+	/* 0x55: i2c addr, 3A: ~ 1430 mvolts*/
+	omap4_power_i2c_send((0x3A55 << 8) | I2C_SLAVE);
 
 	/* FIXME: set VCORE2 force VSEL, Check the reset value */
 	omap4_power_i2c_send((0x295B << 8) | I2C_SLAVE);
@@ -582,12 +546,60 @@ noinline int omap4_scale_vcores(unsigned vsel0_pin)
 	case OMAP4430_ES2_1:
 		omap4_power_i2c_send((0x2A61 << 8) | I2C_SLAVE);
 		break;
-	/* > OMAP4460_ES1_0 : VCORE3 not connected */
 	}
 
 	return 0;
 }
 
+noinline int omap4460_scale_vcores(unsigned vsel0_pin, unsigned volt_mv)
+{
+	void __iomem *base;
+	u32 val = 0;
+
+	/* For VC bypass only VCOREx_CGF_FORCE  is necessary and
+	 * VCOREx_CFG_VOLTAGE  changes can be discarded
+	 */
+	writel(0, OMAP44XX_PRM_VC_CFG_I2C_MODE);
+	writel(0x6026, OMAP44XX_PRM_VC_CFG_I2C_CLK);
+
+	/* TPS - supplies vdd_mpu on 4460
+	 * Setup SET1 and SET0 with right values so that kernel
+	 * can use either of them based on its needs.
+	 */
+
+	omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET0, volt_mv);
+	omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt_mv);
+
+	/*
+	 * Select SET1 in TPS62361:
+	 * VSEL1 is grounded on board. So the following selects
+	 * VSEL1 = 0 and VSEL0 = 1
+	 */
+	base = omap4_get_gpio_base(vsel0_pin);
+
+	val = 1 << (vsel0_pin & GPIO_MASK);
+	writel(val, base + 0x190);
+
+	val =  readl(base + 0x134);
+	val &= ~(1 << (vsel0_pin & GPIO_MASK));
+	writel(val, base + 0x134);
+
+	val = 1 << (vsel0_pin & GPIO_MASK);
+	writel(val, base + 0x194);
+
+	/* set VCORE1 force VSEL
+	 * 4460 : supplies vdd_core
+	 */
+
+	/* 0x55: i2c addr, 28: ~ 1200 mvolts*/
+	omap4_power_i2c_send((0x2855 << 8) | I2C_SLAVE);
+
+	/* FIXME: set VCORE2 force VSEL, Check the reset value */
+	omap4_power_i2c_send((0x295B << 8) | I2C_SLAVE);
+
+	return 0;
+}
+
 void omap4_do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
 {
 	int i;
-- 
1.7.0.4


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^ permalink raw reply	[flat|nested] 7+ messages in thread
* Re: [PATCH v2] omap4: set voltage according to mpu freq
  2013-06-06 12:47     ` [PATCH v2] " Jan Weitzel
@ 2013-06-06 13:40       ` menon.nishanth
  2013-06-08 13:21         ` Sascha Hauer
  0 siblings, 1 reply; 7+ messages in thread
From: menon.nishanth @ 2013-06-06 13:40 UTC (permalink / raw)
  To: Jan Weitzel; +Cc: U-Boot Version 2 (barebox)

On Thu, Jun 6, 2013 at 7:47 AM, Jan Weitzel <j.weitzel@phytec.de> wrote:
> +noinline int omap4460_scale_vcores(unsigned vsel0_pin, unsigned volt_mv)
> +{
> +       void __iomem *base;
> +       u32 val = 0;
> +
> +       /* For VC bypass only VCOREx_CGF_FORCE  is necessary and
> +        * VCOREx_CFG_VOLTAGE  changes can be discarded
> +        */
> +       writel(0, OMAP44XX_PRM_VC_CFG_I2C_MODE);
> +       writel(0x6026, OMAP44XX_PRM_VC_CFG_I2C_CLK);
> +
> +       /* TPS - supplies vdd_mpu on 4460
> +        * Setup SET1 and SET0 with right values so that kernel
> +        * can use either of them based on its needs.
> +        */
> +
> +       omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET0, volt_mv);
Just a nitpick - the general rule of TPS+OMAP4460 integration is *NOT*
to program SET0 register. this is intended to be at boot voltage
required to be used when reboot due to s/w controlled or h/w watchdog.
> +       omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt_mv);
> +
Regards,
Nishanth Menon

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^ permalink raw reply	[flat|nested] 7+ messages in thread
* Re: [PATCH v2] omap4: set voltage according to mpu freq
  2013-06-06 13:40       ` menon.nishanth
@ 2013-06-08 13:21         ` Sascha Hauer
  2013-06-12  7:16           ` Jan Weitzel
  0 siblings, 1 reply; 7+ messages in thread
From: Sascha Hauer @ 2013-06-08 13:21 UTC (permalink / raw)
  To: menon.nishanth; +Cc: U-Boot Version 2 (barebox)

On Thu, Jun 06, 2013 at 08:40:46AM -0500, menon.nishanth@gmail.com wrote:
> On Thu, Jun 6, 2013 at 7:47 AM, Jan Weitzel <j.weitzel@phytec.de> wrote:
> > +noinline int omap4460_scale_vcores(unsigned vsel0_pin, unsigned volt_mv)
> > +{
> > +       void __iomem *base;
> > +       u32 val = 0;
> > +
> > +       /* For VC bypass only VCOREx_CGF_FORCE  is necessary and
> > +        * VCOREx_CFG_VOLTAGE  changes can be discarded
> > +        */
> > +       writel(0, OMAP44XX_PRM_VC_CFG_I2C_MODE);
> > +       writel(0x6026, OMAP44XX_PRM_VC_CFG_I2C_CLK);
> > +
> > +       /* TPS - supplies vdd_mpu on 4460
> > +        * Setup SET1 and SET0 with right values so that kernel
> > +        * can use either of them based on its needs.
> > +        */
> > +
> > +       omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET0, volt_mv);
> Just a nitpick - the general rule of TPS+OMAP4460 integration is *NOT*
> to program SET0 register. this is intended to be at boot voltage
> required to be used when reboot due to s/w controlled or h/w watchdog.

So this line should simply be removed?

Ok, this line is only moved and not introduced in this patch, so it
should be fine to apply this patch and leave this for a separate patch.

Sascha

-- 
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^ permalink raw reply	[flat|nested] 7+ messages in thread
* Re: [PATCH v2] omap4: set voltage according to mpu freq
  2013-06-08 13:21         ` Sascha Hauer
@ 2013-06-12  7:16           ` Jan Weitzel
  0 siblings, 0 replies; 7+ messages in thread
From: Jan Weitzel @ 2013-06-12  7:16 UTC (permalink / raw)
  To: Sascha Hauer; +Cc: U-Boot Version 2 (barebox)

Am Samstag, den 08.06.2013, 15:21 +0200 schrieb Sascha Hauer:
> On Thu, Jun 06, 2013 at 08:40:46AM -0500, menon.nishanth@gmail.com wrote:
> > On Thu, Jun 6, 2013 at 7:47 AM, Jan Weitzel <j.weitzel@phytec.de> wrote:
> > > +noinline int omap4460_scale_vcores(unsigned vsel0_pin, unsigned volt_mv)
> > > +{
> > > +       void __iomem *base;
> > > +       u32 val = 0;
> > > +
> > > +       /* For VC bypass only VCOREx_CGF_FORCE  is necessary and
> > > +        * VCOREx_CFG_VOLTAGE  changes can be discarded
> > > +        */
> > > +       writel(0, OMAP44XX_PRM_VC_CFG_I2C_MODE);
> > > +       writel(0x6026, OMAP44XX_PRM_VC_CFG_I2C_CLK);
> > > +
> > > +       /* TPS - supplies vdd_mpu on 4460
> > > +        * Setup SET1 and SET0 with right values so that kernel
> > > +        * can use either of them based on its needs.
> > > +        */
> > > +
> > > +       omap4_do_scale_tps62361(TPS62361_REG_ADDR_SET0, volt_mv);
> > Just a nitpick - the general rule of TPS+OMAP4460 integration is *NOT*
> > to program SET0 register. this is intended to be at boot voltage
> > required to be used when reboot due to s/w controlled or h/w watchdog.
> 
> So this line should simply be removed?
> 
> Ok, this line is only moved and not introduced in this patch, so it
> should be fine to apply this patch and leave this for a separate patch.
I create a separate patch. I had the problem that our gpio module
(gpio6) goes low due to a reset at init time. Must fix this in kernel.

Jan
> 
> Sascha
> 



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^ permalink raw reply	[flat|nested] 7+ messages in thread
end of thread, other threads:[~2013-06-12  7:17 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-05-28 11:51 [PATCH] omap4: set voltage according to mpu freq Jan Weitzel
2013-05-30  9:39 ` Sascha Hauer
2013-06-05  9:52   ` Jan Weitzel
2013-06-06 12:47     ` [PATCH v2] " Jan Weitzel
2013-06-06 13:40       ` menon.nishanth
2013-06-08 13:21         ` Sascha Hauer
2013-06-12  7:16           ` Jan Weitzel

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