From: zzs <zzs213@126.com>
To: Sascha Hauer <s.hauer@pengutronix.de>
Cc: barebox <barebox@lists.infradead.org>
Subject: Re: bug in arm_cpu_lowlevel_init ??
Date: Thu, 27 Feb 2014 15:51:26 +0800 [thread overview]
Message-ID: <20140227075126.GB20720@greatfirst.com> (raw)
In-Reply-To: <20140227072727.GB17250@pengutronix.de>
>
> The lr (r14) register has different instances, one for each mode. It
> could be that once we switch to a different mode in arm_cpu_lowlevel_init
> we see another instance of r14. So to me the patch looks correct, we
> shouldn't rely on lr as return address but rather use another register
> for storing the address.
> The above only happens though when the CPU is not in SVC32 mode already.
> What first stage loader are you using? Could you analyze in which mode
> the CPU is when the loader jumps to barebox?
>
The first stage loader was written by myself longlong ago. So forgot the
details. I just look the code closer, Found the flowwing line just
before jumps to barebox.
asm ("msr CPSR_c, %0" : :"i"(ARM_MODE_SYS|I_BIT|F_BIT));
So it seems the cpu is in system mode when run barebox.
Your explanation is right.
--
Best Regards,
zzs
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next prev parent reply other threads:[~2014-02-27 7:52 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-27 6:15 zzs
2014-02-27 6:53 ` Alexander Shiyan
2014-02-27 7:53 ` zzs
2014-02-27 7:27 ` Sascha Hauer
2014-02-27 7:51 ` zzs [this message]
2014-02-27 8:01 ` Sascha Hauer
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