From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from metis.ext.pengutronix.de ([2001:6f8:1178:4:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wjok1-0004xl-V8 for barebox@lists.infradead.org; Mon, 12 May 2014 11:50:00 +0000 Date: Mon, 12 May 2014 13:49:36 +0200 From: Sascha Hauer Message-ID: <20140512114936.GG5858@pengutronix.de> References: <1399878486-16086-1-git-send-email-dev@lynxeye.de> <1399878486-16086-11-git-send-email-dev@lynxeye.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1399878486-16086-11-git-send-email-dev@lynxeye.de> List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "barebox" Errors-To: barebox-bounces+u.kleine-koenig=pengutronix.de@lists.infradead.org Subject: Re: [PATCH 10/25] i2c: add Tegra driver To: Lucas Stach Cc: barebox@lists.infradead.org On Mon, May 12, 2014 at 09:07:51AM +0200, Lucas Stach wrote: > Signed-off-by: Lucas Stach > --- > drivers/i2c/busses/Kconfig | 4 + > drivers/i2c/busses/Makefile | 1 + > drivers/i2c/busses/i2c-tegra.c | 708 +++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 713 insertions(+) > create mode 100644 drivers/i2c/busses/i2c-tegra.c > > diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig > index 68d9b46..370abb0 100644 > --- a/drivers/i2c/busses/Kconfig > +++ b/drivers/i2c/busses/Kconfig > @@ -20,6 +20,10 @@ config I2C_OMAP > bool "OMAP I2C Master driver" > depends on ARCH_OMAP > > +config I2C_TEGRA > + bool "Tegra I2C master driver" > + depends on ARCH_TEGRA > + > config I2C_VERSATILE > tristate "ARM Versatile/Realview I2C bus support" > depends on ARCH_VERSATILE > diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile > index a30f9b8..9823d1b 100644 > --- a/drivers/i2c/busses/Makefile > +++ b/drivers/i2c/busses/Makefile > @@ -1,4 +1,5 @@ > obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o > obj-$(CONFIG_I2C_IMX) += i2c-imx.o > obj-$(CONFIG_I2C_OMAP) += i2c-omap.o > +obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o > obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o > diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c > new file mode 100644 > index 0000000..1f27a97 > --- /dev/null > +++ b/drivers/i2c/busses/i2c-tegra.c > @@ -0,0 +1,708 @@ > +/* > + * Copyright (C) 2014 Lucas Stach > + * > + * Partly based on code Copyright (C) 2010 Google, Inc. > + * > + * This software is licensed under the terms of the GNU General Public > + * License version 2, as published by the Free Software Foundation, and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000)) > +#define BYTES_PER_FIFO_WORD 4 > + > +#define I2C_CNFG 0x000 > +#define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12 > +#define I2C_CNFG_PACKET_MODE_EN (1<<10) > +#define I2C_CNFG_NEW_MASTER_FSM (1<<11) > +#define I2C_STATUS 0x01C > +#define I2C_SL_CNFG 0x020 > +#define I2C_SL_CNFG_NACK (1<<1) > +#define I2C_SL_CNFG_NEWSL (1<<2) > +#define I2C_SL_ADDR1 0x02c > +#define I2C_SL_ADDR2 0x030 > +#define I2C_TX_FIFO 0x050 > +#define I2C_RX_FIFO 0x054 > +#define I2C_PACKET_TRANSFER_STATUS 0x058 > +#define I2C_FIFO_CONTROL 0x05c > +#define I2C_FIFO_CONTROL_TX_FLUSH (1<<1) > +#define I2C_FIFO_CONTROL_RX_FLUSH (1<<0) > +#define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5 > +#define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2 > +#define I2C_FIFO_STATUS 0x060 > +#define I2C_FIFO_STATUS_TX_MASK 0xF0 > +#define I2C_FIFO_STATUS_TX_SHIFT 4 > +#define I2C_FIFO_STATUS_RX_MASK 0x0F > +#define I2C_FIFO_STATUS_RX_SHIFT 0 > +#define I2C_INT_MASK 0x064 > +#define I2C_INT_STATUS 0x068 > +#define I2C_INT_PACKET_XFER_COMPLETE (1<<7) > +#define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6) > +#define I2C_INT_TX_FIFO_OVERFLOW (1<<5) > +#define I2C_INT_RX_FIFO_UNDERFLOW (1<<4) > +#define I2C_INT_NO_ACK (1<<3) > +#define I2C_INT_ARBITRATION_LOST (1<<2) > +#define I2C_INT_TX_FIFO_DATA_REQ (1<<1) > +#define I2C_INT_RX_FIFO_DATA_REQ (1<<0) > +#define I2C_CLK_DIVISOR 0x06c > +#define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16 > +#define I2C_CLK_MULTIPLIER_STD_FAST_MODE 8 > + > +#define DVC_CTRL_REG1 0x000 > +#define DVC_CTRL_REG1_INTR_EN (1<<10) > +#define DVC_CTRL_REG2 0x004 > +#define DVC_CTRL_REG3 0x008 > +#define DVC_CTRL_REG3_SW_PROG (1<<26) > +#define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30) > +#define DVC_STATUS 0x00c > +#define DVC_STATUS_I2C_DONE_INTR (1<<30) > + > +#define I2C_ERR_NONE 0x00 > +#define I2C_ERR_NO_ACK 0x01 > +#define I2C_ERR_ARBITRATION_LOST 0x02 > +#define I2C_ERR_UNKNOWN_INTERRUPT 0x04 > + > +#define PACKET_HEADER0_HEADER_SIZE_SHIFT 28 > +#define PACKET_HEADER0_PACKET_ID_SHIFT 16 > +#define PACKET_HEADER0_CONT_ID_SHIFT 12 > +#define PACKET_HEADER0_PROTOCOL_I2C (1<<4) > + > +#define I2C_HEADER_HIGHSPEED_MODE (1<<22) > +#define I2C_HEADER_CONT_ON_NAK (1<<21) > +#define I2C_HEADER_SEND_START_BYTE (1<<20) > +#define I2C_HEADER_READ (1<<19) > +#define I2C_HEADER_10BIT_ADDR (1<<18) > +#define I2C_HEADER_IE_ENABLE (1<<17) > +#define I2C_HEADER_REPEAT_START (1<<16) > +#define I2C_HEADER_CONTINUE_XFER (1<<15) > +#define I2C_HEADER_MASTER_ADDR_SHIFT 12 > +#define I2C_HEADER_SLAVE_ADDR_SHIFT 1 > +/* > + * msg_end_type: The bus control which need to be send at end of transfer. > + * @MSG_END_STOP: Send stop pulse at end of transfer. > + * @MSG_END_REPEAT_START: Send repeat start at end of transfer. > + * @MSG_END_CONTINUE: The following on message is coming and so do not send > + * stop or repeat start. > + */ > +enum msg_end_type { > + MSG_END_STOP, > + MSG_END_REPEAT_START, > + MSG_END_CONTINUE, > +}; > + > +/** > + * struct tegra_i2c_hw_feature : Different HW support on Tegra > + * @has_continue_xfer_support: Continue transfer supports. > + * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer > + * complete interrupt per packet basis. > + * @has_single_clk_source: The i2c controller has single clock source. Tegra30 > + * and earlier Socs has two clock sources i.e. div-clk and > + * fast-clk. > + * @clk_divisor_hs_mode: Clock divisor in HS mode. > + * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is > + * applicable if there is no fast clock source i.e. single clock > + * source. > + */ > + > +struct tegra_i2c_hw_feature { > + bool has_continue_xfer_support; > + bool has_per_pkt_xfer_complete_irq; > + bool has_single_clk_source; > + int clk_divisor_hs_mode; > + int clk_divisor_std_fast_mode; > +}; > + > +/** > + * struct tegra_i2c_dev - per device i2c context > + * @dev: device reference for power management > + * @hw: Tegra i2c hw feature. > + * @adapter: core i2c layer adapter information > + * @div_clk: clock reference for div clock of i2c controller. > + * @fast_clk: clock reference for fast clock of i2c controller. > + * @base: ioremapped registers cookie > + * @is_dvc: identifies the DVC i2c controller, has a different register layout > + * @msg_err: error code for completed message > + * @msg_buf: pointer to current message data > + * @msg_buf_remaining: size of unsent data in the message buffer > + * @msg_read: identifies read transfers > + * @bus_clk_rate: current i2c bus clock rate > + */ > +struct tegra_i2c_dev { > + struct device_d *dev; > + const struct tegra_i2c_hw_feature *hw; > + struct i2c_adapter adapter; > + struct clk *div_clk; > + struct clk *fast_clk; > + struct reset_control *rst; > + void __iomem *base; > + int is_dvc; > + int msg_err; > + u8 *msg_buf; > + size_t msg_buf_remaining; > + int msg_read; > + u32 bus_clk_rate; > +}; > +#define to_tegra_i2c_dev(a) container_of(a, struct tegra_i2c_dev, adapter) > + > +static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg) > +{ > + writel(val, i2c_dev->base + reg); > +} > + > +static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) > +{ > + return readl(i2c_dev->base + reg); > +} > + > +/* > + * i2c_writel and i2c_readl will offset the register if necessary to talk > + * to the I2C block inside the DVC block > + */ > +static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, > + unsigned long reg) > +{ > + if (i2c_dev->is_dvc) > + reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; > + return reg; > +} > + > +static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, > + unsigned long reg) > +{ > + writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); > + > + /* Read back register to make sure that register writes completed */ > + if (reg != I2C_TX_FIFO) > + readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); > +} > + > +static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) > +{ > + return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); > +} > + > +static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, > + unsigned long reg, int len) > +{ > + writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); > +} > + > +static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, > + unsigned long reg, int len) > +{ > + readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); > +} > + > +static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) > +{ > + uint64_t start = get_time_ns(); > + u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL); > + val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH; > + i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); > + > + while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) & > + (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) { > + if (is_timeout(start, SECOND)) { > + dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n"); > + return -ETIMEDOUT; > + } > + mdelay(1); > + } > + return 0; > +} > + > +static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) > +{ > + u32 val; > + int rx_fifo_avail; > + u8 *buf = i2c_dev->msg_buf; > + size_t buf_remaining = i2c_dev->msg_buf_remaining; > + int words_to_transfer; > + > + val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); > + rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >> > + I2C_FIFO_STATUS_RX_SHIFT; > + > + /* Rounds down to not include partial word at the end of buf */ > + words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; > + if (words_to_transfer > rx_fifo_avail) > + words_to_transfer = rx_fifo_avail; > + > + i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); > + > + buf += words_to_transfer * BYTES_PER_FIFO_WORD; > + buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; > + rx_fifo_avail -= words_to_transfer; > + > + /* > + * If there is a partial word at the end of buf, handle it manually to > + * prevent overwriting past the end of buf > + */ > + if (rx_fifo_avail > 0 && buf_remaining > 0) { > + BUG_ON(buf_remaining > 3); > + val = i2c_readl(i2c_dev, I2C_RX_FIFO); > + memcpy(buf, &val, buf_remaining); > + buf_remaining = 0; > + rx_fifo_avail--; > + } > + > + BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0); > + i2c_dev->msg_buf_remaining = buf_remaining; > + i2c_dev->msg_buf = buf; > + return 0; > +} > + > +static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) > +{ > + u32 val; > + int tx_fifo_avail; > + u8 *buf = i2c_dev->msg_buf; > + size_t buf_remaining = i2c_dev->msg_buf_remaining; > + int words_to_transfer; > + > + val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); > + tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >> > + I2C_FIFO_STATUS_TX_SHIFT; > + > + /* Rounds down to not include partial word at the end of buf */ > + words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; > + > + /* It's very common to have < 4 bytes, so optimize that case. */ > + if (words_to_transfer) { > + if (words_to_transfer > tx_fifo_avail) > + words_to_transfer = tx_fifo_avail; > + > + /* > + * Update state before writing to FIFO. If this casues us > + * to finish writing all bytes (AKA buf_remaining goes to 0) we > + * have a potential for an interrupt (PACKET_XFER_COMPLETE is > + * not maskable). We need to make sure that the isr sees > + * buf_remaining as 0 and doesn't call us back re-entrantly. > + */ > + buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; > + tx_fifo_avail -= words_to_transfer; > + i2c_dev->msg_buf_remaining = buf_remaining; > + i2c_dev->msg_buf = buf + > + words_to_transfer * BYTES_PER_FIFO_WORD; > + barrier(); > + > + i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); > + > + buf += words_to_transfer * BYTES_PER_FIFO_WORD; > + } > + > + /* > + * If there is a partial word at the end of buf, handle it manually to > + * prevent reading past the end of buf, which could cross a page > + * boundary and fault. > + */ > + if (tx_fifo_avail > 0 && buf_remaining > 0) { > + BUG_ON(buf_remaining > 3); > + memcpy(&val, buf, buf_remaining); > + > + /* Again update before writing to FIFO to make sure isr sees. */ > + i2c_dev->msg_buf_remaining = 0; > + i2c_dev->msg_buf = NULL; > + barrier(); > + > + i2c_writel(i2c_dev, val, I2C_TX_FIFO); > + } > + > + return 0; > +} > + > +/* > + * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) > + * block. This block is identical to the rest of the I2C blocks, except that > + * it only supports master mode, it has registers moved around, and it needs > + * some extra init to get it into I2C mode. The register moves are handled > + * by i2c_readl and i2c_writel > + */ > +static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) > +{ > + u32 val = 0; > + val = dvc_readl(i2c_dev, DVC_CTRL_REG3); > + val |= DVC_CTRL_REG3_SW_PROG; > + val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; > + dvc_writel(i2c_dev, val, DVC_CTRL_REG3); > + > + val = dvc_readl(i2c_dev, DVC_CTRL_REG1); > + val |= DVC_CTRL_REG1_INTR_EN; > + dvc_writel(i2c_dev, val, DVC_CTRL_REG1); > +} > + > +static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev) > +{ > + int ret; > + if (!i2c_dev->hw->has_single_clk_source) { > + ret = clk_enable(i2c_dev->fast_clk); > + if (ret < 0) { > + dev_err(i2c_dev->dev, > + "Enabling fast clk failed, err %d\n", ret); > + return ret; > + } > + } > + ret = clk_enable(i2c_dev->div_clk); > + if (ret < 0) { > + dev_err(i2c_dev->dev, > + "Enabling div clk failed, err %d\n", ret); > + clk_disable(i2c_dev->fast_clk); > + } > + return ret; > +} > + > +static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev) > +{ > + clk_disable(i2c_dev->div_clk); > + if (!i2c_dev->hw->has_single_clk_source) > + clk_disable(i2c_dev->fast_clk); > +} > + > +static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) > +{ > + u32 val; > + int err = 0; > + int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE; > + u32 clk_divisor; > + > + err = tegra_i2c_clock_enable(i2c_dev); > + if (err < 0) { > + dev_err(i2c_dev->dev, "Clock enable failed %d\n", err); > + return err; > + } > + > + reset_control_assert(i2c_dev->rst); > + udelay(2); > + reset_control_deassert(i2c_dev->rst); > + > + if (i2c_dev->is_dvc) > + tegra_dvc_init(i2c_dev); > + > + val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | > + (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); > + i2c_writel(i2c_dev, val, I2C_CNFG); > + i2c_writel(i2c_dev, 0, I2C_INT_MASK); > + > + clk_multiplier *= (i2c_dev->hw->clk_divisor_std_fast_mode + 1); > + clk_set_rate(i2c_dev->div_clk, i2c_dev->bus_clk_rate * clk_multiplier); > + > + /* Make sure clock divisor programmed correctly */ > + clk_divisor = i2c_dev->hw->clk_divisor_hs_mode; > + clk_divisor |= i2c_dev->hw->clk_divisor_std_fast_mode << > + I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT; > + i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); > + > + if (!i2c_dev->is_dvc) { > + u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); > + sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; > + i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); > + i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); > + i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); > + } > + > + val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT | > + 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT; > + i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); > + > + if (tegra_i2c_flush_fifos(i2c_dev)) > + err = -ETIMEDOUT; > + > + tegra_i2c_clock_disable(i2c_dev); > + > + return err; > +} > + > +static int tegra_i2c_wait_completion(struct tegra_i2c_dev *i2c_dev) > +{ > + u32 status; > + const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; > + uint64_t start = get_time_ns(); > + > + while (!is_timeout(start, SECOND)) { > + > + status = i2c_readl(i2c_dev, I2C_INT_STATUS); > + > + if (unlikely(status & status_err)) { > + if (status & I2C_INT_NO_ACK) > + i2c_dev->msg_err |= I2C_ERR_NO_ACK; > + if (status & I2C_INT_ARBITRATION_LOST) > + i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; > + goto err; > + } > + > + if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { > + if (i2c_dev->msg_buf_remaining) > + tegra_i2c_empty_rx_fifo(i2c_dev); > + else > + BUG(); > + } > + > + if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { > + if (i2c_dev->msg_buf_remaining) > + tegra_i2c_fill_tx_fifo(i2c_dev); > + } > + > + i2c_writel(i2c_dev, status, I2C_INT_STATUS); > + if (i2c_dev->is_dvc) > + dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, > + DVC_STATUS); > + > + if (status & I2C_INT_PACKET_XFER_COMPLETE) { > + BUG_ON(i2c_dev->msg_buf_remaining); > + return 0; > + } > + } > + return -ETIMEDOUT; > + > +err: > + i2c_writel(i2c_dev, status, I2C_INT_STATUS); > + if (i2c_dev->is_dvc) > + dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); > + > + return 0; > +} > + > +static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, > + struct i2c_msg *msg, enum msg_end_type end_state) > +{ > + u32 packet_header; > + int ret; > + > + tegra_i2c_flush_fifos(i2c_dev); > + > + if (msg->len == 0) > + return -EINVAL; > + > + i2c_dev->msg_buf = msg->buf; > + i2c_dev->msg_buf_remaining = msg->len; > + i2c_dev->msg_err = I2C_ERR_NONE; > + i2c_dev->msg_read = (msg->flags & I2C_M_RD); > + > + packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) | > + PACKET_HEADER0_PROTOCOL_I2C | > + (i2c_dev->adapter.nr << PACKET_HEADER0_CONT_ID_SHIFT) | > + (1 << PACKET_HEADER0_PACKET_ID_SHIFT); > + i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); > + > + packet_header = msg->len - 1; > + i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); > + > + packet_header = I2C_HEADER_IE_ENABLE; > + if (end_state == MSG_END_CONTINUE) > + packet_header |= I2C_HEADER_CONTINUE_XFER; > + else if (end_state == MSG_END_REPEAT_START) > + packet_header |= I2C_HEADER_REPEAT_START; > + if (msg->flags & I2C_M_TEN) { > + packet_header |= msg->addr; > + packet_header |= I2C_HEADER_10BIT_ADDR; > + } else { > + packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; > + } > + if (msg->flags & I2C_M_IGNORE_NAK) > + packet_header |= I2C_HEADER_CONT_ON_NAK; > + if (msg->flags & I2C_M_RD) > + packet_header |= I2C_HEADER_READ; > + i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); > + > + if (!(msg->flags & I2C_M_RD)) > + tegra_i2c_fill_tx_fifo(i2c_dev); > + > + ret = tegra_i2c_wait_completion(i2c_dev); > + if (ret) { > + dev_err(i2c_dev->dev, "i2c transfer timed out\n"); > + > + tegra_i2c_init(i2c_dev); > + return -ETIMEDOUT; > + } > + > + if (likely(i2c_dev->msg_err == I2C_ERR_NONE)) > + return 0; > + > + /* > + * NACK interrupt is generated before the I2C controller generates the > + * STOP condition on the bus. So wait for 2 clock periods before resetting > + * the controller so that STOP condition has been delivered properly. > + */ > + if (i2c_dev->msg_err == I2C_ERR_NO_ACK) > + udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); > + > + tegra_i2c_init(i2c_dev); > + if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { > + if (msg->flags & I2C_M_IGNORE_NAK) > + return 0; > + return -EREMOTEIO; > + } > + > + return -EIO; > +} > + > +static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], > + int num) > +{ > + struct tegra_i2c_dev *i2c_dev = to_tegra_i2c_dev(adap); > + int i; > + int ret = 0; > + > + ret = tegra_i2c_clock_enable(i2c_dev); > + if (ret < 0) { > + dev_err(i2c_dev->dev, "Clock enable failed %d\n", ret); > + return ret; > + } > + > + for (i = 0; i < num; i++) { > + enum msg_end_type end_type = MSG_END_STOP; > + if (i < (num - 1)) > + end_type = MSG_END_REPEAT_START; > + ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); > + if (ret) > + break; > + } > + tegra_i2c_clock_disable(i2c_dev); > + return ret ?: i; What does this return when ret is true? ret? I've never seen this. > + i2c_dev = xzalloc(sizeof(*i2c_dev)); > + if (!i2c_dev) { > + dev_err(dev, "Could not allocate struct tegra_i2c_dev"); > + return -ENOMEM; > + } No need to check the result of xzalloc. > + ret = tegra_i2c_clock_enable(i2c_dev); > + if (ret < 0) { > + dev_err(i2c_dev->dev, "Clock enable failed %d\n", ret); > + return ret; > + } Indentation broken here. tegra_i2c_init below also calls tegra_i2c_clock_enable, so this should be unnecessary here, right? > + ret = tegra_i2c_init(i2c_dev); > + if (ret) { > + dev_err(dev, "Failed to initialize i2c controller"); > + return ret; > + } > + Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox