[PATCH 1/3] asm-generic: add IO memory accessors

[PATCH 1/3] asm-generic: add IO memory accessors

[Franck Jullien]

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
---
 include/asm-generic/io.h |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index 3f0f5a2..8d83d68 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -219,4 +219,16 @@ static inline void writesb(const void __iomem *addr, const void *buf, int len)
 	outsb(addr - PCI_IOBASE, buf, len);
 }
 
+#define ioread8(addr)		readb(addr)
+#define ioread16(addr)		readw(addr)
+#define ioread16be(addr)	__be16_to_cpu(__raw_readw(addr))
+#define ioread32(addr)		readl(addr)
+#define ioread32be(addr)	__be32_to_cpu(__raw_readl(addr))
+
+#define iowrite8(v, addr)	writeb((v), (addr))
+#define iowrite16(v, addr)	writew((v), (addr))
+#define iowrite16be(v, addr)	__raw_writew(__cpu_to_be16(v), addr)
+#define iowrite32(v, addr)	writel((v), (addr))
+#define iowrite32be(v, addr)	__raw_writel(__cpu_to_be32(v), addr)
+
 #endif /* __ASM_GENERIC_IO_H */
-- 
1.7.1


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[PATCH 2/3] driver/net: fix bus endianess access in ethoc.c

[Franck Jullien]

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
---
 drivers/net/ethoc.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index 2082770..b000875 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -192,12 +192,12 @@ struct ethoc_bd {
 
 static inline u32 ethoc_read(struct ethoc *dev, loff_t offset)
 {
-	return readl(dev->iobase + offset);
+	return ioread32be(dev->iobase + offset);
 }
 
 static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
 {
-	writel(data, dev->iobase + offset);
+	iowrite32be(data, dev->iobase + offset);
 }
 
 static inline void ethoc_read_bd(struct ethoc *dev, int index,
-- 
1.7.1


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[PATCH 3/3] drivers/net/ethoc: add mdio bus support

[Franck Jullien]

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
---
 drivers/net/Kconfig |    1 +
 drivers/net/ethoc.c |   57 +++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 58 insertions(+), 0 deletions(-)

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 057abd2..7a0d5e1 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -80,6 +80,7 @@ config DRIVER_NET_EP93XX
 
 config DRIVER_NET_ETHOC
 	bool "OpenCores ethernet MAC driver"
+	select PHYLIB
 	help
 	  This option enables support for the OpenCores 10/100 Mbps
 	  Ethernet MAC core.
diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index b000875..42780be 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -178,6 +178,8 @@ struct ethoc {
 
 	u32 num_rx;
 	u32 cur_rx;
+
+	struct mii_bus *miibus;
 };
 
 /**
@@ -481,18 +483,71 @@ static int ethoc_send_packet(struct eth_device *edev, void *packet, int length)
 	return 0;
 }
 
+static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
+{
+	struct ethoc *priv = bus->priv;
+	int i;
+
+	ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
+	ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
+
+	for (i = 0; i < 5; i++) {
+		u32 status = ethoc_read(priv, MIISTATUS);
+		if (!(status & MIISTATUS_BUSY)) {
+			u32 data = ethoc_read(priv, MIIRX_DATA);
+			/* reset MII command register */
+			ethoc_write(priv, MIICOMMAND, 0);
+			return data;
+		}
+		mdelay(1);
+	}
+
+	return -EBUSY;
+}
+
+static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
+{
+	struct ethoc *priv = bus->priv;
+	int i;
+
+	ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
+	ethoc_write(priv, MIITX_DATA, val);
+	ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
+
+	for (i = 0; i < 5; i++) {
+		u32 stat = ethoc_read(priv, MIISTATUS);
+		if (!(stat & MIISTATUS_BUSY)) {
+			/* reset MII command register */
+			ethoc_write(priv, MIICOMMAND, 0);
+			return 0;
+		}
+		mdelay(1);
+	}
+
+	return -EBUSY;
+}
+
 static int ethoc_probe(struct device_d *dev)
 {
 	struct eth_device *edev;
 	struct ethoc *priv;
+	struct mii_bus *miibus;
 
 	edev = xzalloc(sizeof(struct eth_device) +
 		       sizeof(struct ethoc));
 	edev->priv = (struct ethoc *)(edev + 1);
+	miibus = xzalloc(sizeof(struct mii_bus));
 
 	priv = edev->priv;
 	priv->iobase = dev_request_mem_region(dev, 0);
 
+	priv->miibus = miibus;
+
+	miibus->read = ethoc_mdio_read;
+	miibus->write = ethoc_mdio_write;
+	miibus->priv = priv;
+	miibus->parent = dev;
+
 	edev->init = ethoc_init_dev;
 	edev->open = ethoc_open;
 	edev->send = ethoc_send_packet;
@@ -503,6 +558,8 @@ static int ethoc_probe(struct device_d *dev)
 	edev->set_ethaddr = ethoc_set_ethaddr;
 	edev->parent = dev;
 
+	mdiobus_register(miibus);
+
 	eth_register(edev);
 
 	return 0;
-- 
1.7.1


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Re: [PATCH 1/3] asm-generic: add IO memory accessors

[Sascha Hauer]

On Tue, May 13, 2014 at 08:38:24PM +0200, Franck Jullien wrote:
> Signed-off-by: Franck Jullien <franck.jullien@gmail.com>

Applied 1/3 and 2/3 as fixes to master.

Sascha

> ---
>  include/asm-generic/io.h |   12 ++++++++++++
>  1 files changed, 12 insertions(+), 0 deletions(-)
> 
> diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
> index 3f0f5a2..8d83d68 100644
> --- a/include/asm-generic/io.h
> +++ b/include/asm-generic/io.h
> @@ -219,4 +219,16 @@ static inline void writesb(const void __iomem *addr, const void *buf, int len)
>  	outsb(addr - PCI_IOBASE, buf, len);
>  }
>  
> +#define ioread8(addr)		readb(addr)
> +#define ioread16(addr)		readw(addr)
> +#define ioread16be(addr)	__be16_to_cpu(__raw_readw(addr))
> +#define ioread32(addr)		readl(addr)
> +#define ioread32be(addr)	__be32_to_cpu(__raw_readl(addr))
> +
> +#define iowrite8(v, addr)	writeb((v), (addr))
> +#define iowrite16(v, addr)	writew((v), (addr))
> +#define iowrite16be(v, addr)	__raw_writew(__cpu_to_be16(v), addr)
> +#define iowrite32(v, addr)	writel((v), (addr))
> +#define iowrite32be(v, addr)	__raw_writel(__cpu_to_be32(v), addr)
> +
>  #endif /* __ASM_GENERIC_IO_H */
> -- 
> 1.7.1
> 
> 
> _______________________________________________
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> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH 3/3] drivers/net/ethoc: add mdio bus support

[Sascha Hauer]

On Tue, May 13, 2014 at 08:38:26PM +0200, Franck Jullien wrote:
> Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
> ---
>  drivers/net/Kconfig |    1 +
>  drivers/net/ethoc.c |   57 +++++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 58 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index 057abd2..7a0d5e1 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -80,6 +80,7 @@ config DRIVER_NET_EP93XX
>  
>  config DRIVER_NET_ETHOC
>  	bool "OpenCores ethernet MAC driver"
> +	select PHYLIB
>  	help
>  	  This option enables support for the OpenCores 10/100 Mbps
>  	  Ethernet MAC core.
> diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
> index b000875..42780be 100644
> --- a/drivers/net/ethoc.c
> +++ b/drivers/net/ethoc.c
> @@ -178,6 +178,8 @@ struct ethoc {
>  
>  	u32 num_rx;
>  	u32 cur_rx;
> +
> +	struct mii_bus *miibus;
>  };
>  
>  /**
> @@ -481,18 +483,71 @@ static int ethoc_send_packet(struct eth_device *edev, void *packet, int length)
>  	return 0;
>  }
>  
> +static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
> +{
> +	struct ethoc *priv = bus->priv;
> +	int i;
> +
> +	ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
> +	ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
> +
> +	for (i = 0; i < 5; i++) {
> +		u32 status = ethoc_read(priv, MIISTATUS);
> +		if (!(status & MIISTATUS_BUSY)) {
> +			u32 data = ethoc_read(priv, MIIRX_DATA);
> +			/* reset MII command register */
> +			ethoc_write(priv, MIICOMMAND, 0);
> +			return data;
> +		}
> +		mdelay(1);
> +	}

We are polling in barebox anyway. Doing it like above means you have a
1ms window in which you do not return even if your hardware is ready.
Please use a timeout loop:

	uint64_t start = get_time_ns();

	while (!is_timeout(start, 5 * MSECOND)) {
		u32 status = ethoc_read(priv, MIISTATUS);
		if (!(status & MIISTATUS_BUSY)) {
			u32 data = ethoc_read(priv, MIIRX_DATA);
			/* reset MII command register */
			ethoc_write(priv, MIICOMMAND, 0);
			return data;
		}
	}

	return -EBUSY;

>  
>  	edev = xzalloc(sizeof(struct eth_device) +
>  		       sizeof(struct ethoc));
>  	edev->priv = (struct ethoc *)(edev + 1);
> +	miibus = xzalloc(sizeof(struct mii_bus));

No need for a separate allocation. Just embed this into struct ethoc.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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