[PATCH 1/4] PCM051: Update RAM timings

[PATCH 1/4] PCM051: Update RAM timings

[Wadim Egorov]

From: Teresa Gámez <t.gamez@phytec.de>

Updated timings for new MT41J256M16HA15EIT RAM.
Timings are backward compatible to the MT41J256M8HX15E RAMs

Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
 arch/arm/boards/phytec-phycore-am335x/lowlevel.c |   28 ++++++++++-----------
 1 files changed, 13 insertions(+), 15 deletions(-)

diff --git a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
index f04961d..2badcc1 100644
--- a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
@@ -15,7 +15,7 @@
 #include <mach/wdt.h>
 #include <debug_ll.h>
 
-static const struct am33xx_cmd_control MT41J256M8HX15E_2x256M8_cmd = {
+static const struct am33xx_cmd_control MT41J256M16HA15EIT_1x512MB_cmd = {
 	.slave_ratio0 = 0x40,
 	.dll_lock_diff0 = 0x0,
 	.invert_clkout0 = 0x1,
@@ -27,23 +27,21 @@ static const struct am33xx_cmd_control MT41J256M8HX15E_2x256M8_cmd = {
 	.invert_clkout2 = 0x1,
 };
 
-static const struct am33xx_emif_regs MT41J256M8HX15E_2x256M8_regs = {
+static const struct am33xx_emif_regs MT41J256M16HA15EIT_1x512MB_regs = {
 	.emif_read_latency	= 0x6,
-	.emif_tim1		= 0x0668A39B,
-	.emif_tim2		= 0x26337FDA,
-	.emif_tim3		= 0x501F830F,
-	.sdram_config		= 0x61C04832,
+	.emif_tim1		= 0x0888A39B,
+	.emif_tim2		= 0x26517FDA,
+	.emif_tim3		= 0x501F84EF,
+	.sdram_config		= 0x61C04B32,
 	.zq_config		= 0x50074BE4,
 	.sdram_ref_ctrl		= 0x0000093B,
 };
 
-static const struct am33xx_ddr_data MT41J256M8HX15E_2x256M8_data = {
+static const struct am33xx_ddr_data MT41J256M16HA15EIT_1x512MB_data = {
 	.rd_slave_ratio0	= 0x3B,
-	.wr_dqs_slave_ratio0	= 0x85,
-	.fifo_we_slave_ratio0	= 0x100,
-	.wr_slave_ratio0	= 0xC1,
-	.use_rank0_delay	= 0x01,
-	.dll_lock_diff0		= 0x0,
+	.wr_dqs_slave_ratio0	= 0x3B,
+	.fifo_we_slave_ratio0	= 0x96,
+	.wr_slave_ratio0	= 0x76,
 };
 
 extern char __dtb_am335x_phytec_phycore_start[];
@@ -72,9 +70,9 @@ static noinline void pcm051_board_init(void)
 
 	am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_303);
 
-	am335x_sdram_init(0x18B, &MT41J256M8HX15E_2x256M8_cmd,
-			&MT41J256M8HX15E_2x256M8_regs,
-			&MT41J256M8HX15E_2x256M8_data);
+	am335x_sdram_init(0x18B, &MT41J256M16HA15EIT_1x512MB_cmd,
+			&MT41J256M16HA15EIT_1x512MB_regs,
+			&MT41J256M16HA15EIT_1x512MB_data);
 
 	am33xx_uart0_soft_reset();
 	am33xx_enable_uart0_pin_mux();
-- 
1.7.0.4


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 2/4] barebox: common: added new filetypes

[Wadim Egorov]

- Added omap CH image header recognition
  * filetype_ch_image
  * filetype_ch_image_be

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
 common/filetype.c  |   12 ++++++++++++
 include/filetype.h |    2 ++
 2 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/common/filetype.c b/common/filetype.c
index 0b5da30..7cdc0a4 100644
--- a/common/filetype.c
+++ b/common/filetype.c
@@ -53,6 +53,9 @@ static const struct filetype_str filetype_str[] = {
 	[filetype_gpt] = { "GUID Partition Table", "gpt" },
 	[filetype_bpk] = { "Binary PacKage", "bpk" },
 	[filetype_barebox_env] = { "barebox environment file", "bbenv" },
+	[filetype_ch_image] = { "TI OMAP CH boot image", "ch-image" },
+	[filetype_ch_image_be] = {
+			"TI OMAP CH boot image (big endian)", "ch-image-be" },
 };
 
 const char *file_type_to_string(enum filetype f)
@@ -177,6 +180,8 @@ enum filetype file_detect_partition_table(const void *_buf, size_t bufsize)
 	return filetype_unknown;
 }
 
+#define CH_TOC_section_name     0x14
+
 enum filetype file_detect_type(const void *_buf, size_t bufsize)
 {
 	const u32 *buf = _buf;
@@ -246,6 +251,13 @@ enum filetype file_detect_type(const void *_buf, size_t bufsize)
 	if (bufsize >= 1536 && buf16[512 + 28] == le16_to_cpu(0xef53))
 		return filetype_ext;
 
+	if (strncmp(buf8 + CH_TOC_section_name, "CHSETTINGS", 10) == 0)
+		return filetype_ch_image;
+
+	if (buf[5] == 0x43485345 && buf[6] == 0x5454494E &&
+		buf[7] == 0x47530000)
+		return filetype_ch_image_be;
+
 	return filetype_unknown;
 }
 
diff --git a/include/filetype.h b/include/filetype.h
index c20a4f9..fc3140c 100644
--- a/include/filetype.h
+++ b/include/filetype.h
@@ -30,6 +30,8 @@ enum filetype {
 	filetype_ubifs,
 	filetype_bpk,
 	filetype_barebox_env,
+	filetype_ch_image,
+	filetype_ch_image_be,
 	filetype_max,
 };
 
-- 
1.7.0.4


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 3/4] ARM: omap: barebox update nand xloadslots handler

[Wadim Egorov]

- Added barebox nand xloadslots update handler
- This handler updates all given xload slots in nand

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
 arch/arm/mach-omap/Kconfig                      |    9 ++
 arch/arm/mach-omap/Makefile                     |    1 +
 arch/arm/mach-omap/am33xx_bbu_nand_xloadslots.c |  114 +++++++++++++++++++++++
 arch/arm/mach-omap/include/mach/bbu.h           |   11 ++
 4 files changed, 135 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-omap/am33xx_bbu_nand_xloadslots.c

diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index 12b9c1f..22bb878 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -93,6 +93,15 @@ config BAREBOX_UPDATE_AM33XX_SPI_NOR_MLO
 	  Say Y for barebox update SPI NOR MLO handler.
 	  AM35xx, AM33xx chips use big endian MLO for SPI NOR flash.
 
+config BAREBOX_UPDATE_AM33XX_NAND_XLOADSLOTS
+	prompt "barebox update nand xload slots handler"
+	bool
+	depends on BAREBOX_UPDATE
+	help
+	  Say Y for barebox update nand xload slots handler.
+	  This update handler updates N nand xload slots with a single command.
+	  The Handler also checks if the given image has a valid CH header.
+
 config ARCH_TEXT_BASE
 	hex
 	default 0x80e80000 if MACH_OMAP343xSDP
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index 81a771e..c9b6f4b 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -32,3 +32,4 @@ obj-$(CONFIG_MFD_TWL6030) += omap4_twl6030_mmc.o
 obj-$(CONFIG_OMAP4_USBBOOT) += omap4_rom_usb.o
 obj-$(CONFIG_CMD_BOOT_ORDER) += boot_order.o
 obj-$(CONFIG_BAREBOX_UPDATE_AM33XX_SPI_NOR_MLO) += am33xx_bbu_spi_mlo.o
+obj-$(CONFIG_BAREBOX_UPDATE_AM33XX_NAND_XLOADSLOTS) += am33xx_bbu_nand_xloadslots.o
diff --git a/arch/arm/mach-omap/am33xx_bbu_nand_xloadslots.c b/arch/arm/mach-omap/am33xx_bbu_nand_xloadslots.c
new file mode 100644
index 0000000..593da02
--- /dev/null
+++ b/arch/arm/mach-omap/am33xx_bbu_nand_xloadslots.c
@@ -0,0 +1,114 @@
+/*
+ * am33xx_bbu_nand_xloadslots.c - barebox update handler for
+ * the nand xload slots.
+ *
+ * Copyright (c) 2014 Wadim Egorov <w.egorov@phytec.de>, Phytec
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <bbu.h>
+#include <fs.h>
+#include <fcntl.h>
+#include <filetype.h>
+
+/*
+ * This handler updates all given xload slots in nand with an image.
+ * The handler expects one or more device files in the bbu_data struct.
+ * If more than one device file needs to be updated, seperate
+ * device files with a comma. e.g.: data->devicefile = "dev1,dev2,dev3";
+ */
+static int nand_xloadslots_update_handler(struct bbu_handler *handler,
+					struct bbu_data *data)
+{
+	int ret = 0;
+	int fd = 0;
+	const void *image = data->image;
+	size_t size = data->len;
+	char *devfile;
+	const char *delimiter = ",";
+	char *devfilecopy;
+
+	if (file_detect_type(image, size) != filetype_ch_image) {
+		pr_err("%s is not a valid ch-image\n", data->imagefile);
+		return -EINVAL;
+	}
+
+	ret = bbu_confirm(data);
+	if (ret != 0)
+		return ret;
+
+	devfilecopy = (char *)malloc(strlen(data->devicefile));
+	if (!devfilecopy) {
+		pr_err("could not allocate enough memory: %s\n", errno_str());
+		return errno;
+	}
+	strcpy(devfilecopy, data->devicefile);
+
+	devfile = strtok(devfilecopy, delimiter);
+	while (devfile != NULL) {
+		ret = fd = open(devfile, O_WRONLY);
+		if (fd < 0) {
+			pr_err("could not open %s: %s\n", devfile,
+				errno_str());
+			goto out;
+		}
+
+		ret = erase(fd, ~0, 0);
+		if (ret < 0) {
+			pr_err("could not erase %s: %s\n", devfile,
+				errno_str());
+			close(fd);
+			goto out;
+		}
+
+		ret = write(fd, image, size);
+		if (ret < 0) {
+			pr_err("could not write to fd %s: %s\n", devfile,
+				errno_str());
+			close(fd);
+			goto out;
+		}
+
+		close(fd);
+		devfile = strtok(NULL, delimiter);
+	}
+
+	ret = 0;
+out:
+	free(devfilecopy);
+
+	return ret;
+}
+
+/*
+ * Register an am33xx xload slots update handler
+ */
+int am33xx_bbu_nand_xloadslots_register_handler(const char *name,
+						char *devicefile)
+{
+	struct bbu_handler *handler;
+	int ret;
+
+	handler = xzalloc(sizeof(*handler));
+	handler->devicefile = devicefile;
+	handler->name = name;
+	handler->handler = nand_xloadslots_update_handler;
+
+	ret = bbu_register_handler(handler);
+
+	if (ret)
+		free(handler);
+
+	return ret;
+}
diff --git a/arch/arm/mach-omap/include/mach/bbu.h b/arch/arm/mach-omap/include/mach/bbu.h
index 6d4b70f..1960a38 100644
--- a/arch/arm/mach-omap/include/mach/bbu.h
+++ b/arch/arm/mach-omap/include/mach/bbu.h
@@ -12,4 +12,15 @@ int am33xx_bbu_spi_nor_mlo_register_handler(const char *name, char *devicefile)
 }
 #endif
 
+#ifdef CONFIG_BAREBOX_UPDATE_AM33XX_NAND_XLOADSLOTS
+int am33xx_bbu_nand_xloadslots_register_handler(const char *name,
+						char *devicefile);
+#else
+int am33xx_bbu_nand_xloadslots_register_handler(const char *name,
+						char *devicefile)
+{
+	return 0;
+}
+#endif
+
 #endif
-- 
1.7.0.4


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 4/4] phycore-am335x: Added bbu nand xloadslots handler

[Wadim Egorov]

Added bbu nand xloadslots handler to phycore-am335x.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
 arch/arm/boards/phytec-phycore-am335x/board.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boards/phytec-phycore-am335x/board.c b/arch/arm/boards/phytec-phycore-am335x/board.c
index 59de42b..d790d97 100644
--- a/arch/arm/boards/phytec-phycore-am335x/board.c
+++ b/arch/arm/boards/phytec-phycore-am335x/board.c
@@ -69,6 +69,11 @@ static int pcm051_devices_init(void)
 	armlinux_set_architecture(MACH_TYPE_PCM051);
 
 	am33xx_bbu_spi_nor_mlo_register_handler("MLO.spi", "/dev/m25p0.xload");
+	am33xx_bbu_nand_xloadslots_register_handler("xloadslots",
+		"/dev/nand0.xload.bb"
+		",/dev/nand0.xload_backup1.bb"
+		",/dev/nand0.xload_backup2.bb"
+		",/dev/nand0.xload_backup3.bb");
 
 	return 0;
 }
-- 
1.7.0.4


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH 4/4] phycore-am335x: Added bbu nand xloadslots handler

[Holger Schurig]

> Added bbu nand xloadslots handler to phycore-am335x.

I'm currently reworking help texts, and I found that in barebox
abbreviations like RAM, NAND, SRAM are often written in lower-case.
That's just stylistic, I know, but still it sticks out a bit.

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH 3/4] ARM: omap: barebox update nand xloadslots handler

[Sascha Hauer]

Hi Wadim,

On Mon, May 12, 2014 at 02:24:21PM +0200, Wadim Egorov wrote:
> +/*
> + * Register an am33xx xload slots update handler
> + */
> +int am33xx_bbu_nand_xloadslots_register_handler(const char *name,
> +						char *devicefile)

You should use char **devicefile, int num_devicefiles to pass the files.
This makes your code simpler and more obvious.

> +{
> +	struct bbu_handler *handler;

You'll need a struct nand_bbu_handler in which you embed struct
bbu_handler to make that work.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH 3/4] ARM: omap: barebox update nand xloadslots handler

[Alexander Aring]

Hi,

some hints about your string handling in this code...

On Mon, May 12, 2014 at 02:24:21PM +0200, Wadim Egorov wrote:
...
> +
> +	devfilecopy = (char *)malloc(strlen(data->devicefile));
> +	if (!devfilecopy) {
> +		pr_err("could not allocate enough memory: %s\n", errno_str());
> +		return errno;
> +	}
> +	strcpy(devfilecopy, data->devicefile);
possible buffer overflow detected. "strlen" returns length of string
excluding of the terminate null byte.

Just use xstrdup here.

- Alex

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH 1/4] PCM051: Update RAM timings

[Sascha Hauer]

On Mon, May 12, 2014 at 02:24:19PM +0200, Wadim Egorov wrote:
> From: Teresa Gámez <t.gamez@phytec.de>
> 
> Updated timings for new MT41J256M16HA15EIT RAM.
> Timings are backward compatible to the MT41J256M8HX15E RAMs

Applied 1/2 and 2/2 for now.

Sascha

> 
> Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
> Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
> ---
>  arch/arm/boards/phytec-phycore-am335x/lowlevel.c |   28 ++++++++++-----------
>  1 files changed, 13 insertions(+), 15 deletions(-)
> 
> diff --git a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
> index f04961d..2badcc1 100644
> --- a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
> +++ b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
> @@ -15,7 +15,7 @@
>  #include <mach/wdt.h>
>  #include <debug_ll.h>
>  
> -static const struct am33xx_cmd_control MT41J256M8HX15E_2x256M8_cmd = {
> +static const struct am33xx_cmd_control MT41J256M16HA15EIT_1x512MB_cmd = {
>  	.slave_ratio0 = 0x40,
>  	.dll_lock_diff0 = 0x0,
>  	.invert_clkout0 = 0x1,
> @@ -27,23 +27,21 @@ static const struct am33xx_cmd_control MT41J256M8HX15E_2x256M8_cmd = {
>  	.invert_clkout2 = 0x1,
>  };
>  
> -static const struct am33xx_emif_regs MT41J256M8HX15E_2x256M8_regs = {
> +static const struct am33xx_emif_regs MT41J256M16HA15EIT_1x512MB_regs = {
>  	.emif_read_latency	= 0x6,
> -	.emif_tim1		= 0x0668A39B,
> -	.emif_tim2		= 0x26337FDA,
> -	.emif_tim3		= 0x501F830F,
> -	.sdram_config		= 0x61C04832,
> +	.emif_tim1		= 0x0888A39B,
> +	.emif_tim2		= 0x26517FDA,
> +	.emif_tim3		= 0x501F84EF,
> +	.sdram_config		= 0x61C04B32,
>  	.zq_config		= 0x50074BE4,
>  	.sdram_ref_ctrl		= 0x0000093B,
>  };
>  
> -static const struct am33xx_ddr_data MT41J256M8HX15E_2x256M8_data = {
> +static const struct am33xx_ddr_data MT41J256M16HA15EIT_1x512MB_data = {
>  	.rd_slave_ratio0	= 0x3B,
> -	.wr_dqs_slave_ratio0	= 0x85,
> -	.fifo_we_slave_ratio0	= 0x100,
> -	.wr_slave_ratio0	= 0xC1,
> -	.use_rank0_delay	= 0x01,
> -	.dll_lock_diff0		= 0x0,
> +	.wr_dqs_slave_ratio0	= 0x3B,
> +	.fifo_we_slave_ratio0	= 0x96,
> +	.wr_slave_ratio0	= 0x76,
>  };
>  
>  extern char __dtb_am335x_phytec_phycore_start[];
> @@ -72,9 +70,9 @@ static noinline void pcm051_board_init(void)
>  
>  	am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_303);
>  
> -	am335x_sdram_init(0x18B, &MT41J256M8HX15E_2x256M8_cmd,
> -			&MT41J256M8HX15E_2x256M8_regs,
> -			&MT41J256M8HX15E_2x256M8_data);
> +	am335x_sdram_init(0x18B, &MT41J256M16HA15EIT_1x512MB_cmd,
> +			&MT41J256M16HA15EIT_1x512MB_regs,
> +			&MT41J256M16HA15EIT_1x512MB_data);
>  
>  	am33xx_uart0_soft_reset();
>  	am33xx_enable_uart0_pin_mux();
> -- 
> 1.7.0.4
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox