From: Sascha Hauer <s.hauer@pengutronix.de>
To: Matteo Fortini <matteo.fortini@gmail.com>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH 1/2] sama5d3x: fix HSMC MODE register offset and add TIMINGS register
Date: Tue, 10 Jun 2014 08:33:46 +0200 [thread overview]
Message-ID: <20140610063346.GR15686@pengutronix.de> (raw)
In-Reply-To: <assp.02348a4d47.1402045936-18733-2-git-send-email-matteo.fortini@gmail.com>
On Fri, Jun 06, 2014 at 11:12:15AM +0200, Matteo Fortini wrote:
> As stated in section 29.19.35 of SAMA5D3 Series Datasheet,
> MODE register has offset 0x10 and at offset 0x0C there is
> a TIMINGS register.
>
> Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
> ---
> arch/arm/mach-at91/include/mach/at91sam9_smc.h | 31 +++++++++++++++++++++++++-
> arch/arm/mach-at91/sam9_smc.c | 19 ++++++++++++++++
> 2 files changed, 49 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
> index d5cf5f7..6412664 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
> @@ -43,6 +43,16 @@ struct sam9_smc_config {
> /* Mode register */
> u32 mode;
> u8 tdf_cycles:4;
> +
> + /* Timings register */
> + u8 tclr;
> + u8 tadl;
> + u8 tar;
> + u8 ocms;
> + u8 trr;
> + u8 twb;
> + u8 rbnsel;
> + u8 nfsel;
> };
>
> extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
> @@ -77,7 +87,25 @@ extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
> #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
> #define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
>
> -#define AT91_SMC_MODE 0x0c /* Mode Register for CS n */
> +#define AT91_SMC_TIMINGS 0x0c /* Timings register for CS n */
> +#define AT91_SMC_TCLR (0x0f << 0) /* CLE to REN Low Delay */
> +#define AT91_SMC_TCLR_(x) ((x) << 0)
> +#define AT91_SMC_TADL (0x0f << 4) /* ALE to Data Start */
> +#define AT91_SMC_TADL_(x) ((x) << 4)
> +#define AT91_SMC_TAR (0x0f << 8) /* ALE to REN Low Delay */
> +#define AT91_SMC_TAR_(x) ((x) << 8)
> +#define AT91_SMC_OCMS (0x1 << 12) /* Off Chip Memory Scrambling Enable */
> +#define AT91_SMC_OCMS_(x) ((x) << 12)
> +#define AT91_SMC_TRR (0x0f << 16) /* Ready to REN Low Delay */
> +#define AT91_SMC_TRR_(x) ((x) << 16)
> +#define AT91_SMC_TWB (0x0f << 24) /* WEN High to REN to Busy */
> +#define AT91_SMC_TWB_(x) ((x) << 24)
> +#define AT91_SMC_RBNSEL (0x07 << 28) /* Ready/Busy Line Selection */
> +#define AT91_SMC_RBNSEL_(x) ((x) << 28)
> +#define AT91_SMC_NFSEL (0x01 << 31) /* Nand Flash Selection */
> +#define AT91_SMC_NFSEL_(x) ((x) << 31)
> +
> +#define AT91_SMC_MODE ((at91_soc_initdata.type == AT91_SOC_SAMA5D3) ? 0x10 : 0x0c) /* Mode Register for CS n */
> #define AT91_SMC_READMODE (1 << 0) /* Read Mode */
> #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
> #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
> @@ -101,4 +129,5 @@ extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
> #define AT91_SMC_PS_16 (2 << 28)
> #define AT91_SMC_PS_32 (3 << 28)
>
> +
> #endif
This hunk shouldn't be here.
> diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
> index c7bfdfd..89f73ef 100644
> --- a/arch/arm/mach-at91/sam9_smc.c
> +++ b/arch/arm/mach-at91/sam9_smc.c
> @@ -30,6 +30,20 @@ static void sam9_smc_cs_write_mode(void __iomem *base,
> base + AT91_SMC_MODE);
> }
>
> +static void sam9_smc_cs_write_timings(void __iomem *base,
> + struct sam9_smc_config *config)
> +{
> + __raw_writel(AT91_SMC_TCLR_(config->tclr)
> + | AT91_SMC_TADL_(config->tadl)
> + | AT91_SMC_TAR_(config->tar)
> + | AT91_SMC_OCMS_(config->ocms)
> + | AT91_SMC_TRR_(config->trr)
> + | AT91_SMC_TWB_(config->twb)
> + | AT91_SMC_RBNSEL_(config->rbnsel)
> + | AT91_SMC_NFSEL_(config->nfsel),
> + base + AT91_SMC_TIMINGS);
> +}
> +
> void sam9_smc_write_mode(int id, int cs,
> struct sam9_smc_config *config)
> {
> @@ -61,6 +75,11 @@ static void sam9_smc_cs_configure(void __iomem *base,
>
> /* Mode register */
> sam9_smc_cs_write_mode(base, config);
> +
> + /* Timings register */
> + if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
> + sam9_smc_cs_write_timings(base, config);
> + }
I would pretty much prefer a
sama5d3_smc_cs_configure(int id, int cs, struct sama5d3_smc_config *config)
function so that the older SoCs do not have the overhead which the new
SoC requires.
Sascha
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next prev parent reply other threads:[~2014-06-10 6:34 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1402045936-18733-1-git-send-email-matteo.fortini@gmail.com>
2014-06-06 9:12 ` Matteo Fortini
2014-06-10 6:33 ` Sascha Hauer [this message]
2014-06-06 9:12 ` [PATCH 2/2] sama5d3x: HSMC NAND initialize TIMINGS and import values from U-Boot Matteo Fortini
[not found] <1403609192-5862-1-git-send-email-matteo.fortini@gmail.com>
2014-06-24 11:26 ` [PATCH 1/2] sama5d3x: fix HSMC MODE register offset and add TIMINGS register Matteo Fortini
2014-06-25 1:45 ` Bo Shen
2014-06-25 6:42 ` Sascha Hauer
2014-07-02 10:12 ` Raphaël Poggi
2014-07-04 7:47 ` Jean-Christophe PLAGNIOL-VILLARD
2014-07-04 8:28 ` Matteo Fortini
2014-07-07 6:20 ` Sascha Hauer
2014-07-07 18:17 ` Jean-Christophe PLAGNIOL-VILLARD
2014-07-08 5:39 ` Sascha Hauer
2014-07-04 7:49 ` Jean-Christophe PLAGNIOL-VILLARD
[not found] <1405959207-21839-1-git-send-email-matteo.fortini@gmail.com>
2014-07-21 16:13 ` Matteo Fortini
2014-07-31 12:39 ` Sascha Hauer
2014-07-31 12:43 ` Matteo Fortini
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