From: Sascha Hauer <s.hauer@pengutronix.de>
To: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH 0/3] MVEBU SoC ID and revision detection
Date: Wed, 25 Jun 2014 08:45:09 +0200 [thread overview]
Message-ID: <20140625064509.GL15686@pengutronix.de> (raw)
In-Reply-To: <1403610336-5949-1-git-send-email-sebastian.hesselbarth@gmail.com>
On Tue, Jun 24, 2014 at 01:45:33PM +0200, Sebastian Hesselbarth wrote:
> This patch set adds support for reading SoC ID and revision from
> PCIe controllers found on Marvell MVEBU SoCs.
>
> Patch 1 adds PCI bus specific OF address translation required for
> reg property parsing of PCIe controller nodes.
>
> Patch 2 selects above PCI OF address translation for MVEBU SoCs.
>
> Patch 3 adds common code to find and parse PCIe controller nodes
> from MVEBU SoC DT and read out SoC ID and revision registers.
>
> The patches are based on barebox next with latest MVEBU patches
> for cleanup and PBL images applied. They have been tested on
> Marvell Kirkwood, Dove, and Armada 370.
>
> Sebastian Hesselbarth (3):
> drivers: of: import PCI bus specific translator
> ARM: mvebu: select PCI specific DT bus translator
> ARM: mvebu: determine SoC id and revision from PCIe nodes
Applied, thanks
Sascha
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prev parent reply other threads:[~2014-06-25 6:45 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-24 11:45 Sebastian Hesselbarth
2014-06-24 11:45 ` [PATCH 1/3] drivers: of: import PCI bus specific translator Sebastian Hesselbarth
2014-06-24 11:45 ` [PATCH 2/3] ARM: mvebu: select PCI specific DT bus translator Sebastian Hesselbarth
2014-06-24 11:45 ` [PATCH 3/3] ARM: mvebu: determine SoC id and revision from PCIe nodes Sebastian Hesselbarth
2014-06-25 6:45 ` Sascha Hauer [this message]
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