* [PATCH 1/4] ARM: dts: remove most of socfpga barebox-specific dt code
@ 2015-08-14 8:36 Steffen Trumtrar
2015-08-14 8:36 ` [PATCH 2/4] clk: socfpga: fix dt binding support Steffen Trumtrar
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Steffen Trumtrar @ 2015-08-14 8:36 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
Instead of using internal devicetree files, use the official ones from
/dts/src/arm.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/dts/socfpga.dtsi | 659 +----------------------------
arch/arm/dts/socfpga_cyclone5.dtsi | 78 ----
arch/arm/dts/socfpga_cyclone5_socdk.dts | 43 +-
arch/arm/dts/socfpga_cyclone5_sockit.dts | 45 +-
arch/arm/dts/socfpga_cyclone5_socrates.dts | 33 +-
5 files changed, 49 insertions(+), 809 deletions(-)
delete mode 100644 arch/arm/dts/socfpga_cyclone5.dtsi
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 14c0654b2ad0..d4d498be1301 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -1,595 +1,12 @@
-/*
- * Copyright (C) 2012 Altera <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/include/ "skeleton.dtsi"
-
/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
aliases {
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
- serial0 = &uart0;
- serial1 = &uart1;
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- gpio2 = &gpio2;
mmc0 = &mmc;
};
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- compatible = "arm,cortex-a9";
- device_type = "cpu";
- reg = <0>;
- next-level-cache = <&L2>;
- };
- cpu@1 {
- compatible = "arm,cortex-a9";
- device_type = "cpu";
- reg = <1>;
- next-level-cache = <&L2>;
- };
- };
-
- intc: intc@fffed000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0xfffed000 0x1000>,
- <0xfffec100 0x100>;
- };
-
soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- device_type = "soc";
- interrupt-parent = <&intc>;
- ranges;
-
- amba {
- compatible = "arm,amba-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- pdma: pdma@ffe01000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0xffe01000 0x1000>;
- interrupts = <0 180 4>;
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
- };
-
- clkmgr@ffd04000 {
- compatible = "altr,clk-mgr";
- reg = <0xffd04000 0x1000>;
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- osc: osc1 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
-
- f2s_periph_ref_clk: f2s_periph_ref_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <10000000>;
- };
-
- main_pll: main_pll {
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <0>;
- compatible = "altr,socfpga-pll-clock";
- clocks = <&osc>;
- reg = <0x40>;
-
- mpuclk: mpuclk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>;
- fixed-divider = <2>;
- reg = <0x48>;
- };
-
- mainclk: mainclk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>;
- fixed-divider = <4>;
- reg = <0x4C>;
- };
-
- dbg_base_clk: dbg_base_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>;
- fixed-divider = <4>;
- reg = <0x50>;
- };
-
- main_qspi_clk: main_qspi_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>;
- reg = <0x54>;
- };
-
- main_nand_sdmmc_clk: main_nand_sdmmc_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>;
- reg = <0x58>;
- };
-
- cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>;
- reg = <0x5C>;
- };
- };
-
- periph_pll: periph_pll {
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <0>;
- compatible = "altr,socfpga-pll-clock";
- clocks = <&osc>;
- reg = <0x80>;
-
- emac0_clk: emac0_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x88>;
- };
-
- emac1_clk: emac1_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x8C>;
- };
-
- per_qspi_clk: per_qsi_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x90>;
- };
-
- per_nand_mmc_clk: per_nand_mmc_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x94>;
- };
-
- per_base_clk: per_base_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x98>;
- };
-
- h2f_usr1_clk: h2f_usr1_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x9C>;
- };
- };
-
- sdram_pll: sdram_pll {
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <0>;
- compatible = "altr,socfpga-pll-clock";
- clocks = <&osc>;
- reg = <0xC0>;
-
- ddr_dqs_clk: ddr_dqs_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&sdram_pll>;
- reg = <0xC8>;
- };
-
- ddr_2x_dqs_clk: ddr_2x_dqs_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&sdram_pll>;
- reg = <0xCC>;
- };
-
- ddr_dq_clk: ddr_dq_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&sdram_pll>;
- reg = <0xD0>;
- };
-
- h2f_usr2_clk: h2f_usr2_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&sdram_pll>;
- reg = <0xD4>;
- };
- };
-
- mpu_periph_clk: mpu_periph_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mpuclk>;
- fixed-divider = <4>;
- };
-
- mpu_l2_ram_clk: mpu_l2_ram_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mpuclk>;
- fixed-divider = <2>;
- };
-
- l4_main_clk: l4_main_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mainclk>;
- clk-gate = <0x60 0>;
- };
-
- l3_main_clk: l3_main_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mainclk>;
- };
-
- l3_mp_clk: l3_mp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mainclk>;
- div-reg = <0x64 0 2>;
- clk-gate = <0x60 1>;
- };
-
- l3_sp_clk: l3_sp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mainclk>;
- div-reg = <0x64 2 2>;
- };
-
- l4_mp_clk: l4_mp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mainclk>, <&per_base_clk>;
- div-reg = <0x64 4 3>;
- parent-reg = <0x70 0 1>;
- clk-gate = <0x60 2>;
- };
-
- l4_sp_clk: l4_sp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mainclk>, <&per_base_clk>;
- div-reg = <0x64 7 3>;
- parent-reg = <0x70 1 1>;
- clk-gate = <0x60 3>;
- };
-
- dbg_at_clk: dbg_at_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&dbg_base_clk>;
- div-reg = <0x68 0 2>;
- clk-gate = <0x60 4>;
- };
-
- dbg_clk: dbg_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&dbg_base_clk>;
- div-reg = <0x68 2 2>;
- clk-gate = <0x60 5>;
- };
-
- dbg_trace_clk: dbg_trace_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&dbg_base_clk>;
- div-reg = <0x6C 0 3>;
- clk-gate = <0x60 6>;
- };
-
- dbg_timer_clk: dbg_timer_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&dbg_base_clk>;
- clk-gate = <0x60 7>;
- };
-
- cfg_clk: cfg_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&cfg_h2f_usr0_clk>;
- clk-gate = <0x60 8>;
- };
-
- h2f_user0_clk: h2f_user0_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&cfg_h2f_usr0_clk>;
- clk-gate = <0x60 9>;
- };
-
- emac_0_clk: emac_0_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&emac0_clk>;
- clk-gate = <0xa0 0>;
- };
-
- emac_1_clk: emac_1_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&emac1_clk>;
- clk-gate = <0xa0 1>;
- };
-
- usb_mp_clk: usb_mp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&per_base_clk>;
- clk-gate = <0xa0 2>;
- div-reg = <0xa4 0 3>;
- };
-
- spi_m_clk: spi_m_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&per_base_clk>;
- clk-gate = <0xa0 3>;
- div-reg = <0xa4 3 3>;
- };
-
- can0_clk: can0_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&per_base_clk>;
- clk-gate = <0xa0 4>;
- div-reg = <0xa4 6 3>;
- };
-
- can1_clk: can1_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&per_base_clk>;
- clk-gate = <0xa0 5>;
- div-reg = <0xa4 9 3>;
- };
-
- gpio_db_clk: gpio_db_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&per_base_clk>;
- clk-gate = <0xa0 6>;
- div-reg = <0xa8 0 24>;
- };
-
- h2f_user1_clk: h2f_user1_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&h2f_usr1_clk>;
- clk-gate = <0xa0 7>;
- };
-
- sdmmc_clk: sdmmc_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
- clk-gate = <0xa0 8>;
- parent-reg = <0xac 0 2>;
- };
-
- nand_x_clk: nand_x_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
- clk-gate = <0xa0 9>;
- };
-
- nand_clk: nand_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
- clk-gate = <0xa0 10>;
- fixed-divider = <4>;
- parent-reg = <0xac 2 2>;
- };
-
- qspi_clk: qspi_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
- clk-gate = <0xa0 11>;
- parent-reg = <0xac 4 2>;
- };
- };
- };
-
- gmac0: ethernet@ff700000 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
- reg = <0xff700000 0x2000>;
- interrupts = <0 115 4>;
- interrupt-names = "macirq";
- mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac_0_clk>;
- clock-names = "stmmaceth";
- status = "disabled";
- };
-
- gmac1: ethernet@ff702000 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
- reg = <0xff702000 0x2000>;
- interrupts = <0 120 4>;
- interrupt-names = "macirq";
- mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac_1_clk>;
- clock-names = "stmmaceth";
- status = "disabled";
- };
-
- fpgamgr@ff706000 {
- compatible = "altr,socfpga-fpga-mgr";
- reg = <0xff706000 0x1000>,
- <0xffb90000 0x1000>;
- };
-
- gpio0: gpio@ff708000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0xff708000 0x1000>;
- interrupts = <0 164 4>;
- width = <29>;
- virtual_irq_start = <257>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- clocks = <&per_base_clk>;
- };
-
- gpio1: gpio@ff709000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0xff709000 0x1000>;
- interrupts = <0 165 4>;
- width = <29>;
- virtual_irq_start = <286>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- clocks = <&per_base_clk>;
- };
-
- gpio2: gpio@ff70a000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0xff70a000 0x1000>;
- interrupts = <0 166 4>;
- width = <27>;
- virtual_irq_start = <315>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- clocks = <&per_base_clk>;
- };
-
- L2: l2-cache@fffef000 {
- compatible = "arm,pl310-cache";
- reg = <0xfffef000 0x1000>;
- interrupts = <0 38 0x04>;
- cache-unified;
- cache-level = <2>;
- };
-
- mmc: dwmmc0@ff704000 {
- compatible = "altr,socfpga-dw-mshc";
- reg = <0xff704000 0x1000>;
- interrupts = <0 139 4>;
- fifo-depth = <0x400>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&l4_mp_clk>, <&sdmmc_clk>;
- clock-names = "biu", "ciu";
- dw-mshc-ciu-div = <3>;
- };
-
- nand0: nand@ff900000 {
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- compatible = "denali,denali-nand-dt";
- reg = <0xff900000 0x100000>,
- <0xffb80000 0x10000>;
- reg-names = "nand_data", "denali_reg";
- interrupts = <0x0 0x90 0x4>;
- dma-mask = <0xffffffff>;
- clocks = <&nand_clk>;
- status = "disabled";
- };
-
- i2c0: i2c@0xffc04000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc04000 0x1000>;
- clock-frequency = <400000000>;
- clocks = <&l4_sp_clk>;
- interrupts = <0 158 0x4>;
- status = "disabled";
- };
-
- i2c1: i2c@0xffc05000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc05000 0x1000>;
- clock-frequency = <100000000>;
- clocks = <&l4_sp_clk>;
- interrupts = <0 159 0x4>;
- status = "disabled";
- };
-
- i2c2: i2c@0xffc06000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc06000 0x1000>;
- clock-frequency = <100000000>;
- clocks = <&l4_sp_clk>;
- interrupts = <0 160 0x4>;
- status = "disabled";
- };
-
- i2c3: i2c@0xffc07000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc07000 0x1000>;
- clock-frequency = <100000000>;
- clocks = <&l4_sp_clk>;
- interrupts = <0 161 0x4>;
- status = "disabled";
- };
-
qspi: spi@ff705000 {
compatible = "cdns,qspi-nor";
- #address-cells = <1>;
+ #address-cells = <1>;
#size-cells = <0>;
reg = <0xff705000 0x1000>,
<0xffa00000 0x1000>;
@@ -601,68 +18,26 @@
status = "disabled";
};
- /* Local timer */
- timer@fffec600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0xfffec600 0x100>;
- interrupts = <1 13 0xf04>;
- clocks = <&mpu_periph_clk>;
- };
-
- timer@ffc08000 {
- compatible = "snps,dw-apb-timer";
- interrupts = <0 167 4>;
- reg = <0xffc08000 0x1000>;
- clocks = <&osc>;
- };
-
- timer@ffc09000 {
- compatible = "snps,dw-apb-timer";
- interrupts = <0 168 4>;
- reg = <0xffc09000 0x1000>;
- clocks = <&osc>;
- };
-
- timer@ffd00000 {
- compatible = "snps,dw-apb-timer";
- interrupts = <0 169 4>;
- reg = <0xffd00000 0x1000>;
- clocks = <&l4_sp_clk>;
- };
-
- timer@ffd01000 {
- compatible = "snps,dw-apb-timer";
- interrupts = <0 170 4>;
- reg = <0xffd01000 0x1000>;
- clocks = <&l4_sp_clk>;
- };
-
- uart0: serial0@ffc02000 {
- compatible = "snps,dw-apb-uart";
- reg = <0xffc02000 0x1000>;
- interrupts = <0 162 4>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&l4_sp_clk>;
- };
-
- uart1: serial1@ffc03000 {
- compatible = "snps,dw-apb-uart";
- reg = <0xffc03000 0x1000>;
- interrupts = <0 163 4>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&l4_sp_clk>;
- };
-
- rstmgr@ffd05000 {
- compatible = "altr,rst-mgr";
- reg = <0xffd05000 0x1000>;
+ fpgamgr@ff706000 {
+ compatible = "altr,socfpga-fpga-mgr";
+ reg = <0xff706000 0x1000>,
+ <0xffb90000 0x1000>;
};
system_mgr: sysmgr@ffd08000 {
compatible = "altr,sys-mgr", "syscon";
reg = <0xffd08000 0x4000>;
};
- };
+ };
+};
+&osc2 {
+ clock-frequency = <0>;
+};
+
+&f2s_periph_ref_clk {
+ clock-frequency = <0>;
+};
+
+&f2s_sdram_ref_clk {
+ clock-frequency = <0>;
};
diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi
deleted file mode 100644
index ee2ec6c61c29..000000000000
--- a/arch/arm/dts/socfpga_cyclone5.dtsi
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/dts-v1/;
-/include/ "socfpga.dtsi"
-
-/ {
- soc {
- clkmgr@ffd04000 {
- clocks {
- osc1 {
- clock-frequency = <25000000>;
- };
- };
- };
-
- ethernet@ff702000 {
- phy-mode = "rgmii";
- snps,phy-addr = <0xffffffff>; /* probe for phy addr */
- status = "okay";
- };
-
- dwmmc0@ff704000 {
- num-slots = <1>;
- supports-highspeed;
- broken-cd;
- altr,sysmgr = <&system_mgr>;
- altr,dw-mshc-sdr-timing = <0 3>;
-
- slot@0 {
- reg = <0>;
- bus-width = <4>;
- };
- };
-
- timer@ffc08000 {
- clock-frequency = <100000000>;
- };
-
- timer@ffc09000 {
- clock-frequency = <100000000>;
- };
-
- timer@ffd00000 {
- clock-frequency = <25000000>;
- };
-
- timer@ffd01000 {
- clock-frequency = <25000000>;
- };
-
- serial0@ffc02000 {
- clock-frequency = <100000000>;
- };
-
- serial1@ffc03000 {
- clock-frequency = <100000000>;
- };
-
- sysmgr@ffd08000 {
- cpu1-start-addr = <0xffd080c4>;
- };
- };
-};
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index fec321a9d582..f93ac105c46f 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -15,51 +15,12 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-/include/ "socfpga_cyclone5.dtsi"
+#include <arm/socfpga_cyclone5_socdk.dts>
+#include "socfpga.dtsi"
/ {
model = "Altera SOCFPGA Cyclone V SoC Development Kit";
compatible = "altr,socdk", "altr,socfpga-cyclone5", "altr,socfpga";
-
- chosen {
- };
-
- memory {
- name = "memory";
- device_type = "memory";
- reg = <0x0 0x0>;
- };
-
- aliases {
- ethernet0 = &gmac1;
- };
-
- regulator_3_3v: 3-3-v-regulator {
- compatible = "regulator-fixed";
- regulator-name = "3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "rgmii";
-
- rxd0-skew-ps = <0>;
- rxd1-skew-ps = <0>;
- rxd2-skew-ps = <0>;
- rxd3-skew-ps = <0>;
- txen-skew-ps = <0>;
- txc-skew-ps = <2600>;
- rxdv-skew-ps = <0>;
- rxc-skew-ps = <2000>;
-};
-
-&mmc {
- cd-gpios = <&gpio1 18 0>;
- vmmc-supply = <®ulator_3_3v>;
- vqmmc-supply = <®ulator_3_3v>;
};
&qspi {
diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts b/arch/arm/dts/socfpga_cyclone5_sockit.dts
index 1c3fb4d39c0b..8b37574e5dff 100644
--- a/arch/arm/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts
@@ -15,21 +15,13 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-/include/ "socfpga_cyclone5.dtsi"
+#include <arm/socfpga_cyclone5_sockit.dts>
+#include "socfpga.dtsi"
/ {
model = "Terasic SoCkit";
compatible = "terasic,sockit", "altr,socfpga";
- chosen {
- };
-
- memory {
- name = "memory";
- device_type = "memory";
- reg = <0x0 0x0>;
- };
-
leds: gpio-leds {
};
@@ -37,28 +29,36 @@
};
};
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
&leds {
compatible = "gpio-leds";
led@0 {
label = "0";
- gpios = <&gpio1 24 0>;
+ gpios = <&portb 24 0>;
linux,default-trigger = "heartbeat";
};
led@1 {
label = "1";
- gpios = <&gpio1 25 0>;
+ gpios = <&portb 25 0>;
};
led@2 {
label = "2";
- gpios = <&gpio1 26 0>;
+ gpios = <&portb 26 0>;
};
led@3 {
label = "3";
- gpios = <&gpio1 27 0>;
+ gpios = <&portb 27 0>;
};
};
@@ -67,38 +67,29 @@
key@0 {
label = "F1";
- gpios = <&gpio2 21 0>;
+ gpios = <&portc 21 0>;
linux,code = <59>;
};
key@1 {
label = "F2";
- gpios = <&gpio2 22 0>;
+ gpios = <&portc 22 0>;
linux,code = <60>;
};
key@2 {
label = "F3";
- gpios = <&gpio2 23 0>;
+ gpios = <&portc 23 0>;
linux,code = <61>;
};
key@3 {
label = "F4";
- gpios = <&gpio2 24 0>;
+ gpios = <&portc 24 0>;
linux,code = <62>;
};
};
-&gmac1 {
- phy-mode = "rgmii";
- status = "okay";
-};
-
-&mmc {
- status = "okay";
-};
-
&i2c0 {
status = "disabled";
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index 125ad1b8502d..29b41f10433f 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -15,23 +15,23 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-/include/ "socfpga_cyclone5.dtsi"
+#include <arm/socfpga_cyclone5_socrates.dts>
+#include "socfpga.dtsi"
/ {
model = "EBV SoCrates";
compatible = "ebv,socrates", "altr,socfpga";
- chosen {
+ leds: gpio-leds {
};
+};
- memory {
- name = "memory";
- device_type = "memory";
- reg = <0x0 0x0>;
- };
+&gpio0 {
+ status = "okay";
+};
- leds: gpio-leds {
- };
+&gpio1 {
+ status = "okay";
};
&leds {
@@ -39,30 +39,21 @@
led@0 {
label = "0";
- gpios = <&gpio0 28 1>;
+ gpios = <&porta 28 1>;
linux,default-trigger = "heartbeat";
};
led@1 {
label = "1";
- gpios = <&gpio1 19 1>;
+ gpios = <&portb 19 1>;
};
led@2 {
label = "2";
- gpios = <&gpio1 25 1>;
+ gpios = <&portb 25 1>;
};
};
-&gmac1 {
- phy-mode = "rgmii";
- status = "okay";
-};
-
-&mmc {
- status = "okay";
-};
-
&qspi {
status = "okay";
--
2.4.6
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^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 2/4] clk: socfpga: fix dt binding support
2015-08-14 8:36 [PATCH 1/4] ARM: dts: remove most of socfpga barebox-specific dt code Steffen Trumtrar
@ 2015-08-14 8:36 ` Steffen Trumtrar
2015-08-14 8:36 ` [PATCH 3/4] gpio: dw: fix copy&paste variable name Steffen Trumtrar
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Steffen Trumtrar @ 2015-08-14 8:36 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
Change the set_parent/get_parent functions for clock-gates to work
with the Linux kernel DT bindings.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
drivers/clk/socfpga.c | 73 ++++++++++++++++++++++++++++++++++++---------------
1 file changed, 52 insertions(+), 21 deletions(-)
diff --git a/drivers/clk/socfpga.c b/drivers/clk/socfpga.c
index 3387c0e63451..5952efb3368e 100644
--- a/drivers/clk/socfpga.c
+++ b/drivers/clk/socfpga.c
@@ -42,6 +42,11 @@
#define SOCFPGA_PLL_DIVQ_SHIFT 16
#define SOCFGPA_MAX_PARENTS 3
+#define SOCFPGA_L4_MP_CLK "l4_mp_clk"
+#define SOCFPGA_L4_SP_CLK "l4_sp_clk"
+#define SOCFPGA_NAND_CLK "nand_clk"
+#define SOCFPGA_NAND_X_CLK "nand_x_clk"
+#define SOCFPGA_MMC_CLK "sdmmc_clk"
#define SOCFPGA_DB_CLK "gpio_db_clk"
#define div_mask(width) ((1 << (width)) - 1)
@@ -164,13 +169,10 @@ struct clk_socfpga {
const char *parent;
void __iomem *reg;
void __iomem *div_reg;
- void __iomem *parent_reg;
unsigned int fixed_div;
unsigned int bit_idx;
unsigned int shift;
unsigned int width;
- unsigned int parent_shift;
- unsigned int parent_width;
const char *parent_names[SOCFGPA_MAX_PARENTS];
};
@@ -231,21 +233,58 @@ static unsigned long clk_socfpga_recalc_rate(struct clk *clk,
static int clk_socfpga_get_parent(struct clk *clk)
{
- struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk);
+ u32 perpll_src;
+ u32 l4_src;
+
+ if (streq(clk->name, SOCFPGA_L4_MP_CLK)) {
+ l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+ return l4_src &= 0x1;
+ }
+ if (streq(clk->name, SOCFPGA_L4_SP_CLK)) {
+ l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+ return !!(l4_src & 2);
+ }
+
+ perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+ if (streq(clk->name, SOCFPGA_MMC_CLK))
+ return perpll_src &= 0x3;
+ if (streq(clk->name, SOCFPGA_NAND_CLK) ||
+ streq(clk->name, SOCFPGA_NAND_X_CLK))
+ return (perpll_src >> 2) & 3;
- return readl(cs->parent_reg) >> cs->parent_shift &
- ((1 << cs->parent_width) - 1);
+ /* QSPI clock */
+ return (perpll_src >> 4) & 3;
}
static int clk_socfpga_set_parent(struct clk *clk, u8 parent)
{
- struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk);
- uint32_t val;
-
- val = readl(cs->parent_reg);
- val &= ~(((1 << cs->parent_width) - 1) << cs->parent_shift);
- val |= parent << cs->parent_shift;
- writel(val, cs->parent_reg);
+ u32 src_reg;
+
+ if (streq(clk->name, SOCFPGA_L4_MP_CLK)) {
+ src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+ src_reg &= ~0x1;
+ src_reg |= parent;
+ writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
+ } else if (streq(clk->name, SOCFPGA_L4_SP_CLK)) {
+ src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+ src_reg &= ~0x2;
+ src_reg |= (parent << 1);
+ writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
+ } else {
+ src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+ if (streq(clk->name, SOCFPGA_MMC_CLK)) {
+ src_reg &= ~0x3;
+ src_reg |= parent;
+ } else if (streq(clk->name, SOCFPGA_NAND_CLK) ||
+ streq(clk->name, SOCFPGA_NAND_X_CLK)) {
+ src_reg &= ~0xC;
+ src_reg |= (parent << 2);
+ } else {/* QSPI clock */
+ src_reg &= ~0x30;
+ src_reg |= (parent << 4);
+ }
+ writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+ }
return 0;
}
@@ -263,7 +302,6 @@ static struct clk *socfpga_gate_clk(struct device_node *node)
{
u32 clk_gate[2];
u32 div_reg[3];
- u32 parent_reg[3];
u32 fixed_div;
struct clk_socfpga *cs;
int ret;
@@ -293,13 +331,6 @@ static struct clk *socfpga_gate_clk(struct device_node *node)
cs->width = div_reg[2];
}
- ret = of_property_read_u32_array(node, "parent-reg", parent_reg, 3);
- if (!ret) {
- cs->parent_reg = clk_mgr_base_addr + parent_reg[0];
- cs->parent_shift = parent_reg[1];
- cs->parent_width = parent_reg[2];
- }
-
for (i = 0; i < SOCFGPA_MAX_PARENTS; i++) {
cs->parent_names[i] = of_clk_get_parent_name(node, i);
if (!cs->parent_names[i])
--
2.4.6
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barebox@lists.infradead.org
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^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 3/4] gpio: dw: fix copy&paste variable name
2015-08-14 8:36 [PATCH 1/4] ARM: dts: remove most of socfpga barebox-specific dt code Steffen Trumtrar
2015-08-14 8:36 ` [PATCH 2/4] clk: socfpga: fix dt binding support Steffen Trumtrar
@ 2015-08-14 8:36 ` Steffen Trumtrar
2015-08-14 8:36 ` [PATCH 4/4] gpio: dw: implement new bindings Steffen Trumtrar
2015-08-19 13:56 ` [PATCH 1/4] ARM: dts: remove most of socfpga barebox-specific dt code Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Steffen Trumtrar @ 2015-08-14 8:36 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
This is a DW driver not IMX; fix variable name.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
drivers/gpio/gpio-dw.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/gpio-dw.c b/drivers/gpio/gpio-dw.c
index e582eb6d91ca..362f365fa6a1 100644
--- a/drivers/gpio/gpio-dw.c
+++ b/drivers/gpio/gpio-dw.c
@@ -99,7 +99,7 @@ static int dw_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
GPIOF_DIR_OUT : GPIOF_DIR_IN;
}
-static struct gpio_ops imx_gpio_ops = {
+static struct gpio_ops dw_gpio_ops = {
.direction_input = dw_gpio_direction_input,
.direction_output = dw_gpio_direction_output,
.get_direction = dw_gpio_get_direction,
@@ -118,7 +118,7 @@ static int dw_gpio_probe(struct device_d *dev)
if (IS_ERR(chip->regs))
return PTR_ERR(chip->regs);
- chip->chip.ops = &imx_gpio_ops;
+ chip->chip.ops = &dw_gpio_ops;
if (dev->id < 0) {
chip->chip.base = of_alias_get_id(dev->device_node, "gpio");
if (chip->chip.base < 0)
--
2.4.6
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^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 4/4] gpio: dw: implement new bindings
2015-08-14 8:36 [PATCH 1/4] ARM: dts: remove most of socfpga barebox-specific dt code Steffen Trumtrar
2015-08-14 8:36 ` [PATCH 2/4] clk: socfpga: fix dt binding support Steffen Trumtrar
2015-08-14 8:36 ` [PATCH 3/4] gpio: dw: fix copy&paste variable name Steffen Trumtrar
@ 2015-08-14 8:36 ` Steffen Trumtrar
2015-08-19 13:56 ` [PATCH 1/4] ARM: dts: remove most of socfpga barebox-specific dt code Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Steffen Trumtrar @ 2015-08-14 8:36 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
The gpio-driver was developed when the bindings where not stable.
As these have changed in the meantime, the driver has to be updated to
the status quo.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
drivers/gpio/gpio-dw.c | 79 +++++++++++++++++++++++++++++++++++---------------
1 file changed, 55 insertions(+), 24 deletions(-)
diff --git a/drivers/gpio/gpio-dw.c b/drivers/gpio/gpio-dw.c
index 362f365fa6a1..258e43b84e59 100644
--- a/drivers/gpio/gpio-dw.c
+++ b/drivers/gpio/gpio-dw.c
@@ -33,11 +33,15 @@
#define DW_GPIO_CONFIG2_WIDTH(val, port) (((val) >> ((port) * 4) & 0x1f) + 1)
#define DW_GPIO_CONFIG1_NPORTS(val) (((val) >> 2 & 0x3) + 1)
+struct dw_gpio {
+ void __iomem *regs;
+};
+
struct dw_gpio_instance {
+ struct dw_gpio *parent;
struct gpio_chip chip;
u32 gpio_state; /* GPIO state shadow register */
u32 gpio_dir; /* GPIO direction shadow register */
- void __iomem *regs;
};
static inline struct dw_gpio_instance *to_dw_gpio(struct gpio_chip *gc)
@@ -48,29 +52,32 @@ static inline struct dw_gpio_instance *to_dw_gpio(struct gpio_chip *gc)
static int dw_gpio_get(struct gpio_chip *gc, unsigned offset)
{
struct dw_gpio_instance *chip = to_dw_gpio(gc);
+ struct dw_gpio *parent = chip->parent;
- return (readl(chip->regs + DW_GPIO_EXT) >> offset) & 1;
+ return (readl(parent->regs + DW_GPIO_EXT) >> offset) & 1;
}
static void dw_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
{
struct dw_gpio_instance *chip = to_dw_gpio(gc);
+ struct dw_gpio *parent = chip->parent;
u32 data_reg;
- data_reg = readl(chip->regs + DW_GPIO_DR);
+ data_reg = readl(parent->regs + DW_GPIO_DR);
data_reg = (data_reg & ~(1<<offset)) | (value << offset);
- writel(data_reg, chip->regs + DW_GPIO_DR);
+ writel(data_reg, parent->regs + DW_GPIO_DR);
}
static int dw_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
{
struct dw_gpio_instance *chip = to_dw_gpio(gc);
+ struct dw_gpio *parent = chip->parent;
u32 gpio_ddr;
/* Set pin as input, assumes software controlled IP */
- gpio_ddr = readl(chip->regs + DW_GPIO_DDR);
+ gpio_ddr = readl(parent->regs + DW_GPIO_DDR);
gpio_ddr &= ~(1 << offset);
- writel(gpio_ddr, chip->regs + DW_GPIO_DDR);
+ writel(gpio_ddr, parent->regs + DW_GPIO_DDR);
return 0;
}
@@ -79,14 +86,15 @@ static int dw_gpio_direction_output(struct gpio_chip *gc,
unsigned offset, int value)
{
struct dw_gpio_instance *chip = to_dw_gpio(gc);
+ struct dw_gpio *parent = chip->parent;
u32 gpio_ddr;
dw_gpio_set(gc, offset, value);
/* Set pin as output, assumes software controlled IP */
- gpio_ddr = readl(chip->regs + DW_GPIO_DDR);
+ gpio_ddr = readl(parent->regs + DW_GPIO_DDR);
gpio_ddr |= (1 << offset);
- writel(gpio_ddr, chip->regs + DW_GPIO_DDR);
+ writel(gpio_ddr, parent->regs + DW_GPIO_DDR);
return 0;
}
@@ -94,8 +102,9 @@ static int dw_gpio_direction_output(struct gpio_chip *gc,
static int dw_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
{
struct dw_gpio_instance *chip = to_dw_gpio(gc);
+ struct dw_gpio *parent = chip->parent;
- return (readl(chip->regs + DW_GPIO_DDR) & (1 << offset)) ?
+ return (readl(parent->regs + DW_GPIO_DDR) & (1 << offset)) ?
GPIOF_DIR_OUT : GPIOF_DIR_IN;
}
@@ -107,47 +116,69 @@ static struct gpio_ops dw_gpio_ops = {
.set = dw_gpio_set,
};
-static int dw_gpio_probe(struct device_d *dev)
+static int dw_gpio_add_port(struct device_d *dev, struct device_node *node,
+ struct dw_gpio *parent)
{
struct dw_gpio_instance *chip;
uint32_t config1, config2;
int ngpio, ret;
chip = xzalloc(sizeof(*chip));
- chip->regs = dev_request_mem_region(dev, 0);
- if (IS_ERR(chip->regs))
- return PTR_ERR(chip->regs);
chip->chip.ops = &dw_gpio_ops;
- if (dev->id < 0) {
- chip->chip.base = of_alias_get_id(dev->device_node, "gpio");
- if (chip->chip.base < 0)
- return chip->chip.base;
- chip->chip.base *= 32;
- } else {
+ if (dev->id < 0)
+ chip->chip.base = DEVICE_ID_DYNAMIC;
+ else
chip->chip.base = dev->id * 32;
- }
- config2 = readl(chip->regs + DW_GPIO_CONFIG2);
- config1 = readl(chip->regs + DW_GPIO_CONFIG1);
+ config2 = readl(parent->regs + DW_GPIO_CONFIG2);
+ config1 = readl(parent->regs + DW_GPIO_CONFIG1);
ngpio = DW_GPIO_CONFIG2_WIDTH(config2, 0);
if (DW_GPIO_CONFIG1_NPORTS(config1) > 1)
dev_info(dev, "ignoring ports B-D\n");
+ chip->parent = parent;
chip->chip.ngpio = ngpio;
- chip->chip.dev = dev;
+ chip->chip.dev = add_generic_device("dw-port", DEVICE_ID_DYNAMIC, NULL,
+ dev->resource[0].start,
+ resource_size(&dev->resource[0]),
+ IORESOURCE_MEM, NULL);
+
+ if (!chip->chip.dev) {
+ dev_err(dev, "unable to add device\n");
+ return -ENODEV;
+ }
+
+ chip->chip.dev->device_node = node;
ret = gpiochip_add(&chip->chip);
if (ret)
return ret;
- dev_dbg(dev, "probed gpiochip with %d gpios, base %d\n",
+ dev_dbg(chip->chip.dev, "probed gpiochip with %d gpios, base %d\n",
chip->chip.ngpio, chip->chip.base);
return 0;
}
+static int dw_gpio_probe(struct device_d *dev)
+{
+ struct dw_gpio *gpio;
+ struct device_node *node;
+
+ gpio = xzalloc(sizeof(*gpio));
+
+ gpio->regs = dev_request_mem_region(dev, 0);
+ if (IS_ERR(gpio->regs))
+ return PTR_ERR(gpio->regs);
+
+ for_each_child_of_node(dev->device_node, node)
+ dw_gpio_add_port(dev, node, gpio);
+
+ return 0;
+}
+
static __maybe_unused struct of_device_id dwgpio_match[] = {
{
.compatible = "snps,dw-apb-gpio",
--
2.4.6
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^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH 1/4] ARM: dts: remove most of socfpga barebox-specific dt code
2015-08-14 8:36 [PATCH 1/4] ARM: dts: remove most of socfpga barebox-specific dt code Steffen Trumtrar
` (2 preceding siblings ...)
2015-08-14 8:36 ` [PATCH 4/4] gpio: dw: implement new bindings Steffen Trumtrar
@ 2015-08-19 13:56 ` Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Sascha Hauer @ 2015-08-19 13:56 UTC (permalink / raw)
To: Steffen Trumtrar; +Cc: barebox
On Fri, Aug 14, 2015 at 10:36:42AM +0200, Steffen Trumtrar wrote:
> Instead of using internal devicetree files, use the official ones from
> /dts/src/arm.
>
> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Applied, thanks
Sascha
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-- links below jump to the message on this page --
2015-08-14 8:36 [PATCH 1/4] ARM: dts: remove most of socfpga barebox-specific dt code Steffen Trumtrar
2015-08-14 8:36 ` [PATCH 2/4] clk: socfpga: fix dt binding support Steffen Trumtrar
2015-08-14 8:36 ` [PATCH 3/4] gpio: dw: fix copy&paste variable name Steffen Trumtrar
2015-08-14 8:36 ` [PATCH 4/4] gpio: dw: implement new bindings Steffen Trumtrar
2015-08-19 13:56 ` [PATCH 1/4] ARM: dts: remove most of socfpga barebox-specific dt code Sascha Hauer
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