[PATCH 1/4] ARM: l2x0: correct indentation

[PATCH 1/4] ARM: l2x0: correct indentation

[Lucas Stach]

This is a trivial commit.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/cpu/cache-l2x0.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/cache-l2x0.c b/arch/arm/cpu/cache-l2x0.c
index 428dd9324992..6bd540ea69b3 100644
--- a/arch/arm/cpu/cache-l2x0.c
+++ b/arch/arm/cpu/cache-l2x0.c
@@ -129,7 +129,7 @@ static void l2x0_disable(void)
 	writel(0, l2x0_base + L2X0_CTRL);
 }
 
-void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
+void l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
 {
 	__u32 aux;
 	__u32 cache_id;
@@ -161,7 +161,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
 		break;
 	}
 
-       l2x0_way_mask = (1 << ways) - 1;
+	l2x0_way_mask = (1 << ways) - 1;
 
 	/*
 	 * Check if l2x0 controller is already enabled.
-- 
2.6.0


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[PATCH 2/4] ARM: l2x0: move outer cache flush on disable to user

[Lucas Stach]

There are systems like the Calxeda Highbank, which need to do SMC
calls in order to access the secure L2C registers, which means they
want to replace the outer cache disable function with their own.

As the cache flush before entering the boot target is still needed
and to avoid exposing L2C internals to the architectures move the
flush before disable into the only current user.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/cpu/cache-l2x0.c | 2 --
 arch/arm/cpu/cpu.c        | 4 +++-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/cache-l2x0.c b/arch/arm/cpu/cache-l2x0.c
index 6bd540ea69b3..0aa2482321e8 100644
--- a/arch/arm/cpu/cache-l2x0.c
+++ b/arch/arm/cpu/cache-l2x0.c
@@ -124,8 +124,6 @@ static void l2x0_flush_all(void)
 
 static void l2x0_disable(void)
 {
-	writel(0xff, l2x0_base + L2X0_CLEAN_INV_WAY);
-	while (readl(l2x0_base + L2X0_CLEAN_INV_WAY));
 	writel(0, l2x0_base + L2X0_CTRL);
 }
 
diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index ff8f43d175ec..e8191ecde5a8 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -80,8 +80,10 @@ struct outer_cache_fns outer_cache;
 void mmu_disable(void)
 {
 	__mmu_cache_flush();
-	if (outer_cache.disable)
+	if (outer_cache.disable) {
+		outer_cache.flush_all();
 		outer_cache.disable();
+	}
 	__mmu_cache_off();
 }
 
-- 
2.6.0


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[PATCH 3/4] ARM: imx6: use l2x0 header for register definitions

[Lucas Stach]

Instead of using a redundant definition. This makes things a bit cleaner
and also avoids to introduce another private define in the next patch.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/mach-imx/imx6.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index ceabe19dc2ab..509ac8460216 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -23,6 +23,7 @@
 #include <mach/imx6-regs.h>
 #include <mach/generic.h>
 #include <asm/mmu.h>
+#include <asm/cache-l2x0.h>
 
 #define SI_REV 0x260
 
@@ -195,8 +196,6 @@ int imx6_devices_init(void)
 	return 0;
 }
 
-#define L310_PREFETCH_CTRL		0xF60
-
 static int imx6_mmu_init(void)
 {
 	void __iomem *l2x0_base = IOMEM(0x00a02000);
@@ -205,8 +204,8 @@ static int imx6_mmu_init(void)
 	if (!cpu_is_mx6())
 		return 0;
 
-	/* Configure the L2 PREFETCH and POWER registers */
-	val = readl(l2x0_base + L310_PREFETCH_CTRL);
+	/* configure the PREFETCH register */
+	val = readl(l2x0_base + L2X0_PREFETCH_CTRL);
 	val |= 0x70800000;
 
 	/*
@@ -221,7 +220,7 @@ static int imx6_mmu_init(void)
 	if (cpu_is_mx6q())
 		val &= ~(1 << 30 | 1 << 23);
 
-	writel(val, l2x0_base + L310_PREFETCH_CTRL);
+	writel(val, l2x0_base + L2X0_PREFETCH_CTRL);
 
 	l2x0_init(l2x0_base, 0x0, ~0UL);
 
-- 
2.6.0


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[PATCH 4/4] ARM: imx6: set shared attribute override bit in PL310

[Lucas Stach]

In order to make the system compliant to the ARMv7 ARM RevC clarifications
regarding conflicting memory aliases the shared override bit needs to be
set. This needs to be done in the bootloader, as the kernel will not apply
any modifications to the AUX_CTRL register by default, as it is a secure only
register.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/mach-imx/imx6.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 509ac8460216..c49de49209f3 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -222,6 +222,17 @@ static int imx6_mmu_init(void)
 
 	writel(val, l2x0_base + L2X0_PREFETCH_CTRL);
 
+	/*
+	 * Set shared attribute override bit in AUX_CTRL register, this is done
+	 * here as it must be done regardless of the usage of the L2 cache in
+	 * barebox itself. The kernel will not touch this bit, but it must be
+	 * set to make the system compliant to the ARMv7 ARM RevC clarifications
+	 * regarding conflicting memory aliases.
+	 */
+	val = readl(l2x0_base + L2X0_AUX_CTRL);
+	val |= (1 << 22);
+	writel(val, l2x0_base + L2X0_AUX_CTRL);
+
 	l2x0_init(l2x0_base, 0x0, ~0UL);
 
 	return 0;
-- 
2.6.0


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Re: [PATCH 1/4] ARM: l2x0: correct indentation

[Sascha Hauer]

On Mon, Oct 12, 2015 at 03:54:49PM +0200, Lucas Stach wrote:
> This is a trivial commit.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  arch/arm/cpu/cache-l2x0.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Applied, thanks

Sascha

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