Re: [PATCH 1/2] nand: imx6: Changed default NAND clock

[Stefan Lengfeld <s.lengfeld@phytec.de>]

Hi Sascha,

On Fri, Oct 21, 2016 at 09:11:47AM +0200, Sascha Hauer wrote:
> On Thu, Oct 20, 2016 at 03:40:06PM +0200, Christian Hemp wrote:
> > From: Daniel Schultz <d.schultz@phytec.de>
> > 
> > The Barebox recognized false bad erase blocks while booting from a
> > Spansion NAND (1). This error occurred due a to high clock. The
> > Kernel sets the default NAND clock to 22Mhz. So, to fix this error and
> > to be more identical with the Kernel, the Barebox should be too.
> 
> The timing is changed afterwards to a faster mode and the clock is
> changed again. Does that work for you properly?
> 
> Sascha

Yes, if the NAND chip supports EDO mode, the clock is changed to 80/100Mhz
correctly. Here is the driver output with additional debug messages:

    nand: NAND device: Manufacturer ID: 0x2c, Chip ID: 0xdc (Micron MT29F4G08ABADAWP), 512MiB, page size: 2048, OOB size: 64
    mxs_nand_setup_timing: mode 5
    mxs_nand_setup_timing: mxs_nand_compute_edo_timing
    mxs_nand_setup_timing: clock is 96000000

The patch fixes the case, when the NAND chip does not support EDO mode.
Instead of function 'mxs_nand_compute_edo_timing' the function
'mxs_nand_compute_hardware_timing' is called here.

        mode = mxs_nand_enable_edo_mode(info);
        if (mode >= 0)
                mxs_nand_compute_edo_timing(info, &hw, mode);
        else
                mxs_nand_compute_hardware_timing(info, &hw);

Since 'mxs_nand_compute_hardware_timing' does not change the clock, the clock
is too fast for the NAND chip.

Here is the output of two different NAND chips without EDO mode. The patch to
set the clock to 22Mhz was already applied:

    nand: NAND device: Manufacturer ID: 0x01, Chip ID: 0xd3 (AMD/Spansion S34ML08G2), 1024MiB, page size: 2048, OOB size: 128
    mxs_nand_setup_timing: mode -22
    mxs_nand_setup_timing: mxs_nand_compute_hardware_timing
    mxs_nand_setup_timing: clock is 21818181
    
    nand: NAND device: Manufacturer ID: 0xec, Chip ID: 0xd3 (Samsung NAND 1GiB 3,3V 8-bit), 1024MiB, page size: 2048, OOB size: 64
    mxs_nand_setup_timing: mode -2
    mxs_nand_setup_timing: mxs_nand_compute_hardware_timing
    mxs_nand_setup_timing: clock is 21818181

Mit freundlichen Grüßen / Kind regards,
	Stefan Lengfeld

> 
> > 
> > 1: nand: NAND device: Manufacturer ID: 0x01, Chip ID: 0xd3 (AMD/Spansion
> > S34ML08G2), 1024MiB, page size: 2048, OOB size: 128
> > 
> > Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
> > Tested-by: Stefan Lengfeld <s.lengfeld@phytec.de>
> > Signed-off-by: Christian Hemp <c.hemp@phytec.de>
> > ---
> >  drivers/mtd/nand/nand_mxs.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
> > index 01aa063..fe955e8 100644
> > --- a/drivers/mtd/nand/nand_mxs.c
> > +++ b/drivers/mtd/nand/nand_mxs.c
> > @@ -2145,7 +2145,7 @@ static int mxs_nand_probe(struct device_d *dev)
> >  
> >  	if (mxs_nand_is_imx6(nand_info)) {
> >  		clk_disable(nand_info->clk);
> > -		clk_set_rate(nand_info->clk, 96000000);
> > +		clk_set_rate(nand_info->clk, 22000000);
> >  		clk_enable(nand_info->clk);
> >  		nand_info->dma_channel_base = 0;
> >  	} else {
> > -- 
> > 1.9.1
> > 
> > 
> > _______________________________________________
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> > barebox@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/barebox
> > 
> 
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