From: Lucas Stach <l.stach@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH 4/5] PCI: align BAR address to BAR size
Date: Tue, 1 Nov 2016 09:58:54 +0100 [thread overview]
Message-ID: <20161101085855.953-4-l.stach@pengutronix.de> (raw)
In-Reply-To: <20161101085855.953-1-l.stach@pengutronix.de>
PCI BARs require their address to be at least aligned to their
size, otherwise address decoding will fail as the base address
gets rounded down.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
drivers/pci/pci.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 19cda1f145bc..12aafccde578 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -174,11 +174,12 @@ static void setup_device(struct pci_dev *dev, int max_bar)
continue;
}
pr_debug("pbar%d: mask=%08x io %d bytes\n", bar, mask, size);
- if (last_io + size >
+ if (ALIGN(last_io, size) + size >
dev->bus->resource[PCI_BUS_RESOURCE_IO]->end) {
pr_debug("BAR does not fit within bus IO res\n");
return;
}
+ last_io = ALIGN(last_io, size);
pr_debug("pbar%d: allocated at 0x%08x\n", bar, last_io);
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_io);
dev->resource[bar].flags = IORESOURCE_IO;
@@ -193,11 +194,12 @@ static void setup_device(struct pci_dev *dev, int max_bar)
}
pr_debug("pbar%d: mask=%08x P memory %d bytes\n",
bar, mask, size);
- if (last_mem_pref + size >
+ if (ALIGN(last_mem_pref, size) + size >
dev->bus->resource[PCI_BUS_RESOURCE_MEM_PREF]->end) {
pr_debug("BAR does not fit within bus p-mem res\n");
return;
}
+ last_mem_pref = ALIGN(last_mem_pref, size);
pr_debug("pbar%d: allocated at 0x%08x\n", bar, last_mem_pref);
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_mem_pref);
dev->resource[bar].flags = IORESOURCE_MEM |
@@ -212,11 +214,12 @@ static void setup_device(struct pci_dev *dev, int max_bar)
}
pr_debug("pbar%d: mask=%08x NP memory %d bytes\n",
bar, mask, size);
- if (last_mem + size >
+ if (ALIGN(last_mem, size) + size >
dev->bus->resource[PCI_BUS_RESOURCE_MEM]->end) {
pr_debug("BAR does not fit within bus np-mem res\n");
return;
}
+ last_mem = ALIGN(last_mem, size);
pr_debug("pbar%d: allocated at 0x%08x\n", bar, last_mem);
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_mem);
dev->resource[bar].flags = IORESOURCE_MEM;
--
2.10.1
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next prev parent reply other threads:[~2016-11-01 8:59 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-01 8:58 [PATCH 1/5] PCI: add some useful debug output Lucas Stach
2016-11-01 8:58 ` [PATCH 2/5] PCI: only check specific flag for 64bit BAR Lucas Stach
2016-11-01 8:58 ` [PATCH 3/5] PCI: align address range before scanning bridge Lucas Stach
2016-11-01 8:58 ` Lucas Stach [this message]
2016-11-01 8:58 ` [PATCH 5/5] PCI: split PCI hierarchy enumeration and config from device registration Lucas Stach
2016-11-03 6:12 ` [PATCH 1/5] PCI: add some useful debug output Sascha Hauer
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