From: Sascha Hauer <s.hauer@pengutronix.de>
To: Lucas Stach <l.stach@pengutronix.de>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH 1/5] PCI: add some useful debug output
Date: Thu, 3 Nov 2016 07:12:23 +0100 [thread overview]
Message-ID: <20161103061223.xpuomwamm4zspgtv@pengutronix.de> (raw)
In-Reply-To: <20161101085855.953-1-l.stach@pengutronix.de>
On Tue, Nov 01, 2016 at 09:58:51AM +0100, Lucas Stach wrote:
> This makes diagnosing problems in address space allocation
> much easier.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> drivers/pci/pci.c | 6 ++++++
> 1 file changed, 6 insertions(+)
Applied, thanks
Sascha
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 191561da0368..46f5d5f7de36 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -179,6 +179,7 @@ static void setup_device(struct pci_dev *dev, int max_bar)
> pr_debug("BAR does not fit within bus IO res\n");
> return;
> }
> + pr_debug("pbar%d: allocated at 0x%08x\n", bar, last_io);
> pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_io);
> dev->resource[bar].flags = IORESOURCE_IO;
> last_addr = last_io;
> @@ -197,6 +198,7 @@ static void setup_device(struct pci_dev *dev, int max_bar)
> pr_debug("BAR does not fit within bus p-mem res\n");
> return;
> }
> + pr_debug("pbar%d: allocated at 0x%08x\n", bar, last_mem_pref);
> pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_mem_pref);
> dev->resource[bar].flags = IORESOURCE_MEM |
> IORESOURCE_PREFETCH;
> @@ -215,6 +217,7 @@ static void setup_device(struct pci_dev *dev, int max_bar)
> pr_debug("BAR does not fit within bus np-mem res\n");
> return;
> }
> + pr_debug("pbar%d: allocated at 0x%08x\n", bar, last_mem);
> pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_mem);
> dev->resource[bar].flags = IORESOURCE_MEM;
> last_addr = last_mem;
> @@ -286,18 +289,21 @@ static void postscan_setup_bridge(struct pci_dev *dev)
>
> if (last_mem) {
> last_mem = ALIGN(last_mem, SZ_1M);
> + pr_debug("bridge NP limit at 0x%08x\n", last_mem);
> pci_write_config_word(dev, PCI_MEMORY_LIMIT,
> ((last_mem - 1) & 0xfff00000) >> 16);
> }
>
> if (last_mem_pref) {
> last_mem_pref = ALIGN(last_mem_pref, SZ_1M);
> + pr_debug("bridge P limit at 0x%08x\n", last_mem_pref);
> pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT,
> ((last_mem_pref - 1) & 0xfff00000) >> 16);
> }
>
> if (last_io) {
> last_io = ALIGN(last_io, SZ_4K);
> + pr_debug("bridge IO limit at 0x%08x\n", last_io);
> pci_write_config_byte(dev, PCI_IO_LIMIT,
> ((last_io - 1) & 0x0000f000) >> 8);
> pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
> --
> 2.10.1
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
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prev parent reply other threads:[~2016-11-03 6:12 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-01 8:58 Lucas Stach
2016-11-01 8:58 ` [PATCH 2/5] PCI: only check specific flag for 64bit BAR Lucas Stach
2016-11-01 8:58 ` [PATCH 3/5] PCI: align address range before scanning bridge Lucas Stach
2016-11-01 8:58 ` [PATCH 4/5] PCI: align BAR address to BAR size Lucas Stach
2016-11-01 8:58 ` [PATCH 5/5] PCI: split PCI hierarchy enumeration and config from device registration Lucas Stach
2016-11-03 6:12 ` Sascha Hauer [this message]
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