mail archive of the barebox mailing list
 help / color / mirror / Atom feed
* [RFCv2 0/2] add initial RISC-V architecture support
@ 2016-11-13 21:50 Antony Pavlov
  2016-11-13 21:50 ` [RFCv2 1/2] serial: add driver for SiFive UART Antony Pavlov
  2016-11-13 21:50 ` [RFCv2 2/2] add initial RISC-V architecture support Antony Pavlov
  0 siblings, 2 replies; 5+ messages in thread
From: Antony Pavlov @ 2016-11-13 21:50 UTC (permalink / raw)
  To: barebox

This patchseries adds initial RISC-V architecture support for barebox.

See Documentation/boards/riscv.rst for instructions.

You can obtain this patch from github:

  $ git clone -b 20161113.riscv https://github.com/frantony/barebox

Changes since 20161013:

  * drop spike pk support;
  * add qemu-sifive board support;
  * add Documentation/boards/riscv.rst;
  * fix guard macro names.

TODOs:

  * split patch;
  * use sifive timer IP-block.

Antony Pavlov (2):
  serial: add driver for SiFive UART
  Add initial RISC-V architecture support

 Documentation/boards/riscv.rst                 |  63 ++++++++++++++
 arch/riscv/Kconfig                             |  42 ++++++++++
 arch/riscv/Makefile                            |  51 ++++++++++++
 arch/riscv/boards/qemu-sifive/.gitignore       |   1 +
 arch/riscv/boards/qemu-sifive/Makefile         |   1 +
 arch/riscv/boards/qemu-sifive/board.c          |  28 +++++++
 arch/riscv/boot/Makefile                       |   2 +
 arch/riscv/boot/main_entry.c                   |  40 +++++++++
 arch/riscv/boot/start.S                        |  44 ++++++++++
 arch/riscv/configs/qemu-sifive_defconfig       |  75 +++++++++++++++++
 arch/riscv/dts/.gitignore                      |   1 +
 arch/riscv/dts/Makefile                        |   9 ++
 arch/riscv/dts/qemu-sifive.dts                 |  19 +++++
 arch/riscv/dts/skeleton.dtsi                   |  13 +++
 arch/riscv/include/asm/barebox.h               |   1 +
 arch/riscv/include/asm/bitops.h                |  35 ++++++++
 arch/riscv/include/asm/bitsperlong.h           |  10 +++
 arch/riscv/include/asm/byteorder.h             |  12 +++
 arch/riscv/include/asm/common.h                |   6 ++
 arch/riscv/include/asm/elf.h                   |  11 +++
 arch/riscv/include/asm/io.h                    |   8 ++
 arch/riscv/include/asm/posix_types.h           |   1 +
 arch/riscv/include/asm/sections.h              |   1 +
 arch/riscv/include/asm/string.h                |   1 +
 arch/riscv/include/asm/swab.h                  |   6 ++
 arch/riscv/include/asm/types.h                 |  60 ++++++++++++++
 arch/riscv/include/asm/unaligned.h             |  19 +++++
 arch/riscv/lib/.gitignore                      |   1 +
 arch/riscv/lib/Makefile                        |   3 +
 arch/riscv/lib/asm-offsets.c                   |  12 +++
 arch/riscv/lib/barebox.lds.S                   |  87 ++++++++++++++++++++
 arch/riscv/lib/dtb.c                           |  41 ++++++++++
 arch/riscv/mach-sifive/Kconfig                 |  16 ++++
 arch/riscv/mach-sifive/Makefile                |   3 +
 arch/riscv/mach-sifive/include/mach/debug_ll.h |  38 +++++++++
 drivers/of/Kconfig                             |   2 +-
 drivers/serial/Kconfig                         |   3 +
 drivers/serial/Makefile                        |   1 +
 drivers/serial/serial_sifive.c                 | 109 +++++++++++++++++++++++++
 39 files changed, 875 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/boards/riscv.rst
 create mode 100644 arch/riscv/Kconfig
 create mode 100644 arch/riscv/Makefile
 create mode 100644 arch/riscv/boards/qemu-sifive/.gitignore
 create mode 100644 arch/riscv/boards/qemu-sifive/Makefile
 create mode 100644 arch/riscv/boards/qemu-sifive/board.c
 create mode 100644 arch/riscv/boot/Makefile
 create mode 100644 arch/riscv/boot/main_entry.c
 create mode 100644 arch/riscv/boot/start.S
 create mode 100644 arch/riscv/configs/qemu-sifive_defconfig
 create mode 100644 arch/riscv/dts/.gitignore
 create mode 100644 arch/riscv/dts/Makefile
 create mode 100644 arch/riscv/dts/qemu-sifive.dts
 create mode 100644 arch/riscv/dts/skeleton.dtsi
 create mode 100644 arch/riscv/include/asm/barebox.h
 create mode 100644 arch/riscv/include/asm/bitops.h
 create mode 100644 arch/riscv/include/asm/bitsperlong.h
 create mode 100644 arch/riscv/include/asm/byteorder.h
 create mode 100644 arch/riscv/include/asm/common.h
 create mode 100644 arch/riscv/include/asm/elf.h
 create mode 100644 arch/riscv/include/asm/io.h
 create mode 100644 arch/riscv/include/asm/posix_types.h
 create mode 100644 arch/riscv/include/asm/sections.h
 create mode 100644 arch/riscv/include/asm/string.h
 create mode 100644 arch/riscv/include/asm/swab.h
 create mode 100644 arch/riscv/include/asm/types.h
 create mode 100644 arch/riscv/include/asm/unaligned.h
 create mode 100644 arch/riscv/lib/.gitignore
 create mode 100644 arch/riscv/lib/Makefile
 create mode 100644 arch/riscv/lib/asm-offsets.c
 create mode 100644 arch/riscv/lib/barebox.lds.S
 create mode 100644 arch/riscv/lib/dtb.c
 create mode 100644 arch/riscv/mach-sifive/Kconfig
 create mode 100644 arch/riscv/mach-sifive/Makefile
 create mode 100644 arch/riscv/mach-sifive/include/mach/debug_ll.h
 create mode 100644 drivers/serial/serial_sifive.c

-- 
2.10.2


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2016-11-18  8:37 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-11-13 21:50 [RFCv2 0/2] add initial RISC-V architecture support Antony Pavlov
2016-11-13 21:50 ` [RFCv2 1/2] serial: add driver for SiFive UART Antony Pavlov
2016-11-17  7:07   ` Sascha Hauer
2016-11-18  8:41     ` Antony Pavlov
2016-11-13 21:50 ` [RFCv2 2/2] add initial RISC-V architecture support Antony Pavlov

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox