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* i.MX7 Ethernet clock fixes
@ 2017-02-06  6:50 Sascha Hauer
  2017-02-06  6:50 ` [PATCH 1/9] clk: Keep enable count consistent over reparent Sascha Hauer
                   ` (8 more replies)
  0 siblings, 9 replies; 10+ messages in thread
From: Sascha Hauer @ 2017-02-06  6:50 UTC (permalink / raw)
  To: Barebox List

The following patches are encessary to make fec ethernet work on i.MX7.
There are some inaccuracies in the barebox clock support have to be fixed
first, but the real problem was that our clock code derived from the
Kernel controls non existing clock gates whereas the real gates are not
touched at all. It seems this was never noticed in the kernel since U-Boot
has configured the clocks correctly beforehand.

Sascha

----------------------------------------------------------------
Sascha Hauer (9):
      clk: Keep enable count consistent over reparent
      clk: implement CLK_OPS_PARENT_ENABLE
      clk: i.MX: clk-gate2: Allow to pass flags
      clk: i.MX: Pass CLK_OPS_PARENT_ENABLE where necessary
      clk: i.MX7: do clock reparenting when all clocks are initialized
      clk: Add support for shared gates
      clk: i.MX7: Fix ethernet clocks
      clk: i.MX7: do not register PLL bypass clocks as separate clocks
      clk: i.MX7: setup ethernet clocks

 drivers/clk/Makefile          |   3 +-
 drivers/clk/clk-gate-shared.c | 123 +++++++++++++++++++++
 drivers/clk/clk.c             |  52 +++++++--
 drivers/clk/imx/clk-gate2.c   |  11 +-
 drivers/clk/imx/clk-imx7.c    | 249 +++++++++++++++++++++---------------------
 drivers/clk/imx/clk.h         |  20 ++--
 include/linux/clk.h           |   5 +
 7 files changed, 315 insertions(+), 148 deletions(-)
 create mode 100644 drivers/clk/clk-gate-shared.c

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^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH 1/9] clk: Keep enable count consistent over reparent
  2017-02-06  6:50 i.MX7 Ethernet clock fixes Sascha Hauer
@ 2017-02-06  6:50 ` Sascha Hauer
  2017-02-06  6:50 ` [PATCH 2/9] clk: implement CLK_OPS_PARENT_ENABLE Sascha Hauer
                   ` (7 subsequent siblings)
  8 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2017-02-06  6:50 UTC (permalink / raw)
  To: Barebox List

When reparenting a clock we have to make sure the new parent is enabled
when the clock was enabled on the old parent. Also we have to decrease
the old parents use counter when the clock was enabled.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/clk.c | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 1566beabd..6f3053727 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -173,14 +173,15 @@ struct clk *clk_lookup(const char *name)
 	return ERR_PTR(-ENODEV);
 }
 
-int clk_set_parent(struct clk *clk, struct clk *parent)
+int clk_set_parent(struct clk *clk, struct clk *newparent)
 {
-	int i;
+	int i, ret;
+	struct clk *curparent = clk_get_parent(clk);
 
 	if (IS_ERR(clk))
 		return PTR_ERR(clk);
-	if (IS_ERR(parent))
-		return PTR_ERR(parent);
+	if (IS_ERR(newparent))
+		return PTR_ERR(newparent);
 
 	if (!clk->num_parents)
 		return -EINVAL;
@@ -192,14 +193,22 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 			clk->parents[i] = clk_lookup(clk->parent_names[i]);
 
 		if (!IS_ERR_OR_NULL(clk->parents[i]))
-			if (clk->parents[i] == parent)
+			if (clk->parents[i] == newparent)
 				break;
 	}
 
 	if (i == clk->num_parents)
 		return -EINVAL;
 
-	return clk->ops->set_parent(clk, i);
+	if (clk->enable_count)
+		clk_enable(newparent);
+
+	ret = clk->ops->set_parent(clk, i);
+
+	if (clk->enable_count)
+		clk_disable(curparent);
+
+	return ret;
 }
 
 struct clk *clk_get_parent(struct clk *clk)
-- 
2.11.0


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^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH 2/9] clk: implement CLK_OPS_PARENT_ENABLE
  2017-02-06  6:50 i.MX7 Ethernet clock fixes Sascha Hauer
  2017-02-06  6:50 ` [PATCH 1/9] clk: Keep enable count consistent over reparent Sascha Hauer
@ 2017-02-06  6:50 ` Sascha Hauer
  2017-02-06  6:50 ` [PATCH 3/9] clk: i.MX: clk-gate2: Allow to pass flags Sascha Hauer
                   ` (6 subsequent siblings)
  8 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2017-02-06  6:50 UTC (permalink / raw)
  To: Barebox List

Some clocks may only be modified when their parent clocks are enabled.
The kernel has the CLK_OPS_PARENT_ENABLE flag for this purpose.
Implement it for barebox aswell.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/clk.c   | 31 +++++++++++++++++++++++++++----
 include/linux/clk.h |  2 ++
 2 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 6f3053727..93e000c6e 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -141,6 +141,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 {
 	struct clk *parent;
 	unsigned long parent_rate = 0;
+	int ret;
 
 	if (!clk)
 		return 0;
@@ -148,14 +149,26 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 	if (IS_ERR(clk))
 		return PTR_ERR(clk);
 
+	if (!clk->ops->set_rate)
+		return -ENOSYS;
+
 	parent = clk_get_parent(clk);
-	if (parent)
+	if (parent) {
 		parent_rate = clk_get_rate(parent);
 
-	if (clk->ops->set_rate)
-		return clk->ops->set_rate(clk, rate, parent_rate);
+		if (clk->flags & CLK_OPS_PARENT_ENABLE) {
+			ret = clk_enable(parent);
+			if (ret)
+				return ret;
+		}
+	}
+
+	ret = clk->ops->set_rate(clk, rate, parent_rate);
+
+	if (parent && clk->flags & CLK_OPS_PARENT_ENABLE)
+		clk_disable(parent);
 
-	return -ENOSYS;
+	return ret;
 }
 
 struct clk *clk_lookup(const char *name)
@@ -203,8 +216,18 @@ int clk_set_parent(struct clk *clk, struct clk *newparent)
 	if (clk->enable_count)
 		clk_enable(newparent);
 
+	if (clk->flags & CLK_OPS_PARENT_ENABLE) {
+		clk_enable(curparent);
+		clk_enable(newparent);
+	}
+
 	ret = clk->ops->set_parent(clk, i);
 
+	if (clk->flags & CLK_OPS_PARENT_ENABLE) {
+		clk_disable(curparent);
+		clk_disable(newparent);
+	}
+
 	if (clk->enable_count)
 		clk_disable(curparent);
 
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 8cb9731f1..697ab4ff4 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -198,6 +198,8 @@ static inline int clk_set_rate(struct clk *clk, unsigned long rate)
 #ifdef CONFIG_COMMON_CLK
 
 #define CLK_SET_RATE_PARENT     (1 << 0) /* propagate rate change up one level */
+/* parents need enable during gate/ungate, set rate and re-parent */
+#define CLK_OPS_PARENT_ENABLE   (1 << 12)
 
 #define CLK_GATE_INVERTED	(1 << 0)
 #define CLK_GATE_HIWORD_MASK	(1 << 1)
-- 
2.11.0


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^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH 3/9] clk: i.MX: clk-gate2: Allow to pass flags
  2017-02-06  6:50 i.MX7 Ethernet clock fixes Sascha Hauer
  2017-02-06  6:50 ` [PATCH 1/9] clk: Keep enable count consistent over reparent Sascha Hauer
  2017-02-06  6:50 ` [PATCH 2/9] clk: implement CLK_OPS_PARENT_ENABLE Sascha Hauer
@ 2017-02-06  6:50 ` Sascha Hauer
  2017-02-06  6:50 ` [PATCH 4/9] clk: i.MX: Pass CLK_OPS_PARENT_ENABLE where necessary Sascha Hauer
                   ` (5 subsequent siblings)
  8 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2017-02-06  6:50 UTC (permalink / raw)
  To: Barebox List

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/imx/clk-gate2.c | 11 ++++++-----
 drivers/clk/imx/clk.h       |  8 ++++----
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
index f952f3e3f..e7dcd87a7 100644
--- a/drivers/clk/imx/clk-gate2.c
+++ b/drivers/clk/imx/clk-gate2.c
@@ -88,7 +88,8 @@ static struct clk_ops clk_gate2_ops = {
 };
 
 struct clk *clk_gate2_alloc(const char *name, const char *parent,
-			    void __iomem *reg, u8 shift, u8 cgr_val)
+			    void __iomem *reg, u8 shift, u8 cgr_val,
+			    unsigned long flags)
 {
 	struct clk_gate2 *g = xzalloc(sizeof(*g));
 
@@ -100,7 +101,7 @@ struct clk *clk_gate2_alloc(const char *name, const char *parent,
 	g->clk.name = name;
 	g->clk.parent_names = &g->parent;
 	g->clk.num_parents = 1;
-	g->clk.flags = CLK_SET_RATE_PARENT;
+	g->clk.flags = CLK_SET_RATE_PARENT | flags;
 
 	return &g->clk;
 }
@@ -113,12 +114,12 @@ void clk_gate2_free(struct clk *clk)
 }
 
 struct clk *clk_gate2(const char *name, const char *parent, void __iomem *reg,
-		      u8 shift, u8 cgr_val)
+		      u8 shift, u8 cgr_val, unsigned long flags)
 {
 	struct clk *g;
 	int ret;
 
-	g = clk_gate2_alloc(name , parent, reg, shift, cgr_val);
+	g = clk_gate2_alloc(name , parent, reg, shift, cgr_val, flags);
 
 	ret = clk_register(g);
 	if (ret) {
@@ -135,7 +136,7 @@ struct clk *clk_gate2_inverted(const char *name, const char *parent,
 	struct clk *clk;
 	struct clk_gate2 *g;
 
-	clk = clk_gate2(name, parent, reg, shift, 0x3);
+	clk = clk_gate2(name, parent, reg, shift, 0x3, 0);
 	if (IS_ERR(clk))
 		return clk;
 
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 1610c48ec..4f80a3262 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -2,7 +2,7 @@
 #define __IMX_CLK_H
 
 struct clk *clk_gate2(const char *name, const char *parent, void __iomem *reg,
-		      u8 shift, u8 cgr_val);
+		      u8 shift, u8 cgr_val, unsigned long flags);
 
 static inline struct clk *imx_clk_divider(const char *name, const char *parent,
 		void __iomem *reg, u8 shift, u8 width)
@@ -77,13 +77,13 @@ static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
 static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
 		void __iomem *reg, u8 shift)
 {
-	return clk_gate2(name, parent, reg, shift, 0x3);
+	return clk_gate2(name, parent, reg, shift, 0x3, 0);
 }
 
 static inline struct clk *imx_clk_gate2_cgr(const char *name, const char *parent,
 					    void __iomem *reg, u8 shift, u8 cgr_val)
 {
-	return clk_gate2(name, parent, reg, shift, cgr_val);
+	return clk_gate2(name, parent, reg, shift, cgr_val, 0);
 }
 
 static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
@@ -95,7 +95,7 @@ static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
 static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
 		void __iomem *reg, u8 shift)
 {
-	return clk_gate2(name, parent, reg, shift, 0x3);
+	return clk_gate2(name, parent, reg, shift, 0x3, 0);
 }
 
 struct clk *imx_clk_pllv1(const char *name, const char *parent,
-- 
2.11.0


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^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH 4/9] clk: i.MX: Pass CLK_OPS_PARENT_ENABLE where necessary
  2017-02-06  6:50 i.MX7 Ethernet clock fixes Sascha Hauer
                   ` (2 preceding siblings ...)
  2017-02-06  6:50 ` [PATCH 3/9] clk: i.MX: clk-gate2: Allow to pass flags Sascha Hauer
@ 2017-02-06  6:50 ` Sascha Hauer
  2017-02-06  6:50 ` [PATCH 5/9] clk: i.MX7: do clock reparenting when all clocks are initialized Sascha Hauer
                   ` (4 subsequent siblings)
  8 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2017-02-06  6:50 UTC (permalink / raw)
  To: Barebox List

CLK_OPS_PARENT_ENABLE was missing on some i.MX7 specific clocks.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/imx/clk.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 4f80a3262..019114848 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -19,7 +19,7 @@ static inline struct clk *imx_clk_divider_np(const char *name, const char *paren
 static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
 		void __iomem *reg, u8 shift, u8 width)
 {
-	return clk_divider(name, parent, reg, shift, width, 0);
+	return clk_divider(name, parent, reg, shift, width, CLK_OPS_PARENT_ENABLE);
 }
 
 static inline struct clk *imx_clk_divider_table(const char *name,
@@ -53,7 +53,7 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
 static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
 		u8 shift, u8 width, const char **parents, u8 num_parents)
 {
-	return clk_mux(name, reg, shift, width, parents, num_parents, 0);
+	return clk_mux(name, reg, shift, width, parents, num_parents, CLK_OPS_PARENT_ENABLE);
 }
 
 static inline struct clk *imx_clk_mux_p(const char *name, void __iomem *reg,
@@ -89,13 +89,13 @@ static inline struct clk *imx_clk_gate2_cgr(const char *name, const char *parent
 static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
 		void __iomem *reg, u8 shift)
 {
-	return clk_gate(name, parent, reg, shift, CLK_SET_RATE_PARENT, 0);
+	return clk_gate(name, parent, reg, shift, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 0);
 }
 
 static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
 		void __iomem *reg, u8 shift)
 {
-	return clk_gate2(name, parent, reg, shift, 0x3, 0);
+	return clk_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE);
 }
 
 struct clk *imx_clk_pllv1(const char *name, const char *parent,
-- 
2.11.0


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^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH 5/9] clk: i.MX7: do clock reparenting when all clocks are initialized
  2017-02-06  6:50 i.MX7 Ethernet clock fixes Sascha Hauer
                   ` (3 preceding siblings ...)
  2017-02-06  6:50 ` [PATCH 4/9] clk: i.MX: Pass CLK_OPS_PARENT_ENABLE where necessary Sascha Hauer
@ 2017-02-06  6:50 ` Sascha Hauer
  2017-02-06  6:50 ` [PATCH 6/9] clk: Add support for shared gates Sascha Hauer
                   ` (3 subsequent siblings)
  8 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2017-02-06  6:50 UTC (permalink / raw)
  To: Barebox List

By the time the i.MX7 clock driver probes the fixed clocks which
are the roots of the clock tree are not yet present, so reparenting
especially to one of the fixed clocks does not work. Move the
tree setup to a later initcall when the fixed clocks are there.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/imx/clk-imx7.c | 31 +++++++++++++++++++++++--------
 1 file changed, 23 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/imx/clk-imx7.c b/drivers/clk/imx/clk-imx7.c
index 45c5a4667..383b685a1 100644
--- a/drivers/clk/imx/clk-imx7.c
+++ b/drivers/clk/imx/clk-imx7.c
@@ -383,11 +383,12 @@ static struct clk ** const uart_clks[] __initconst = {
 	NULL
 };
 
+static int imx7_clk_initialized;
+
 static int imx7_ccm_probe(struct device_d *dev)
 {
 	struct resource *iores;
 	void __iomem *base, *anatop_base, *ccm_base;
-	int i;
 
 	anatop_base = IOMEM(MX7_ANATOP_BASE_ADDR);
 	iores = dev_request_mem_resource(dev, 0);
@@ -418,13 +419,6 @@ static int imx7_ccm_probe(struct device_d *dev)
 	clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_p("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel));
 	clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_p("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel));
 
-	clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
-	clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
-	clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
-	clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
-	clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
-	clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
-
 	clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13);
 	clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13);
 	clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13);
@@ -848,9 +842,29 @@ static int imx7_ccm_probe(struct device_d *dev)
 	clk_data.clk_num = ARRAY_SIZE(clks);
 	of_clk_add_provider(dev->device_node, of_clk_src_onecell_get, &clk_data);
 
+	imx7_clk_initialized = 1;
+
+	return 0;
+}
+
+static int imx7_clk_setup(void)
+{
+	int i;
+
+	if (!imx7_clk_initialized)
+		return 0;
+
+	clks[IMX7D_OSC_24M_CLK] = clk_lookup("osc");
+
 	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
 		clk_enable(clks[clks_init_on[i]]);
 
+	clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
+	clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
+	clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
+	clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
+	clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
+
 	/* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
 	clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
 
@@ -859,6 +873,7 @@ static int imx7_ccm_probe(struct device_d *dev)
 
 	return 0;
 }
+postcore_initcall(imx7_clk_setup);
 
 static __maybe_unused struct of_device_id imx7_ccm_dt_ids[] = {
 	{
-- 
2.11.0


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^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH 6/9] clk: Add support for shared gates
  2017-02-06  6:50 i.MX7 Ethernet clock fixes Sascha Hauer
                   ` (4 preceding siblings ...)
  2017-02-06  6:50 ` [PATCH 5/9] clk: i.MX7: do clock reparenting when all clocks are initialized Sascha Hauer
@ 2017-02-06  6:50 ` Sascha Hauer
  2017-02-06  6:50 ` [PATCH 7/9] clk: i.MX7: Fix ethernet clocks Sascha Hauer
                   ` (2 subsequent siblings)
  8 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2017-02-06  6:50 UTC (permalink / raw)
  To: Barebox List

Sometimes a single software control knob controls multiple gates
in hardware. This patch adds support for shared gates which help
coping this situation. The first gate is registered with the hardware
gate as usual, the others are registered as shared gates which does
not have hardware control itself, but only switches the real hardware
gate.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/Makefile          |   3 +-
 drivers/clk/clk-gate-shared.c | 123 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk.h           |   3 ++
 3 files changed, 128 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/clk-gate-shared.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index a4e4ed024..5811d28b8 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,6 +1,7 @@
 obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed.o clk-divider.o clk-fixed-factor.o \
 				clk-mux.o clk-gate.o clk-composite.o \
-				clk-fractional-divider.o clk-conf.o
+				clk-fractional-divider.o clk-conf.o \
+				clk-gate-shared.o
 obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
 
 obj-$(CONFIG_ARCH_MVEBU)	+= mvebu/
diff --git a/drivers/clk/clk-gate-shared.c b/drivers/clk/clk-gate-shared.c
new file mode 100644
index 000000000..a95f940dd
--- /dev/null
+++ b/drivers/clk/clk-gate-shared.c
@@ -0,0 +1,123 @@
+/*
+ * clk-gate-shared.c - generic barebox clock support. Based on Linux clk support
+ *
+ * Copyright (c) 2017 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <common.h>
+#include <io.h>
+#include <malloc.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+struct clk_gate_shared {
+	struct clk clk;
+	const char *parent;
+	const char *companion_gate;
+	struct clk *companion_clk;
+};
+
+#define to_clk_gate_shared(_clk) container_of(_clk, struct clk_gate_shared, clk)
+
+static struct clk *lookup_companion(struct clk_gate_shared *g)
+{
+	if (IS_ERR(g->companion_clk))
+		g->companion_clk = clk_lookup(g->companion_gate);
+
+	if (IS_ERR(g->companion_clk))
+		return NULL;
+
+	return g->companion_clk;
+}
+
+static int clk_gate_shared_enable(struct clk *clk)
+{
+	struct clk_gate_shared *g = to_clk_gate_shared(clk);
+
+	return clk_enable(lookup_companion(g));
+}
+
+static void clk_gate_shared_disable(struct clk *clk)
+{
+	struct clk_gate_shared *g = to_clk_gate_shared(clk);
+
+	clk_disable(lookup_companion(g));
+}
+
+static int clk_gate_shared_is_enabled(struct clk *clk)
+{
+	struct clk_gate_shared *g = to_clk_gate_shared(clk);
+
+	return clk_is_enabled(lookup_companion(g));
+}
+
+static struct clk_ops clk_gate_shared_ops = {
+	.set_rate = clk_parent_set_rate,
+	.round_rate = clk_parent_round_rate,
+	.enable = clk_gate_shared_enable,
+	.disable = clk_gate_shared_disable,
+	.is_enabled = clk_gate_shared_is_enabled,
+};
+
+struct clk *clk_gate_shared_alloc(const char *name, const char *parent, const char *companion,
+			   unsigned flags)
+{
+	struct clk_gate_shared *g = xzalloc(sizeof(*g));
+
+	g->parent = parent;
+	g->companion_gate = companion;
+	g->companion_clk = ERR_PTR(-EINVAL);
+	g->clk.ops = &clk_gate_shared_ops;
+	g->clk.name = name;
+	g->clk.flags = flags;
+	g->clk.parent_names = &g->parent;
+	g->clk.num_parents = 1;
+
+	return &g->clk;
+}
+
+void clk_gate_shared_free(struct clk *clk)
+{
+	struct clk_gate_shared *g = to_clk_gate_shared(clk);
+
+	free(g);
+}
+
+/*
+ * clk_gate_shared - register a gate controlled by another gate
+ * @name: The name of the new clock gate
+ * @parent: The parent name of the new clock
+ * companion: The hardware gate this clock is controlled by
+ * @flags: common CLK_* flags
+ *
+ * This gate clock is used when a single software control knob controls multiple
+ * gates in hardware. The first gate is then registered as the real hardware gate,
+ * the others are registered with this function. This gate has no hardware control
+ * itself, but only enables/disabled its companion hardware gate.
+ */
+struct clk *clk_gate_shared(const char *name, const char *parent, const char *companion,
+			    unsigned flags)
+{
+	struct clk *clk;
+	int ret;
+
+	clk = clk_gate_shared_alloc(name , parent, companion, flags);
+
+	ret = clk_register(clk);
+	if (ret) {
+		clk_gate_shared_free(clk);
+		return ERR_PTR(ret);
+	}
+
+	return clk;
+}
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 697ab4ff4..7dd52388c 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -296,6 +296,9 @@ struct clk *clk_gate(const char *name, const char *parent, void __iomem *reg,
 		u8 shift, unsigned flags, u8 clk_gate_flags);
 struct clk *clk_gate_inverted(const char *name, const char *parent, void __iomem *reg,
 		u8 shift, unsigned flags);
+struct clk *clk_gate_shared(const char *name, const char *parent, const char *shared,
+			    unsigned flags);
+
 int clk_is_enabled(struct clk *clk);
 
 int clk_is_enabled_always(struct clk *clk);
-- 
2.11.0


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^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH 7/9] clk: i.MX7: Fix ethernet clocks
  2017-02-06  6:50 i.MX7 Ethernet clock fixes Sascha Hauer
                   ` (5 preceding siblings ...)
  2017-02-06  6:50 ` [PATCH 6/9] clk: Add support for shared gates Sascha Hauer
@ 2017-02-06  6:50 ` Sascha Hauer
  2017-02-06  6:50 ` [PATCH 8/9] clk: i.MX7: do not register PLL bypass clocks as separate clocks Sascha Hauer
  2017-02-06  6:50 ` [PATCH 9/9] clk: i.MX7: setup ethernet clocks Sascha Hauer
  8 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2017-02-06  6:50 UTC (permalink / raw)
  To: Barebox List

The original clock code from Linux registers some gates at
base + 0x44e0, 0x44f0, 0x4500, 0x4510. These are not in the reference
manual and do not seem to have any effect on the hardware. The
reference manual lists clocks at 0x4700 and 0x4710 which Linux
does not control at all. These clocks really do have an effect on
the hardware and are needed for ethernet support. Register the
existing clocks rather than the made up clocks to support
ethernet.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/imx/clk-imx7.c | 15 +++++++++++----
 drivers/clk/imx/clk.h      |  6 ++++++
 2 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/imx/clk-imx7.c b/drivers/clk/imx/clk-imx7.c
index 383b685a1..eb072b73e 100644
--- a/drivers/clk/imx/clk-imx7.c
+++ b/drivers/clk/imx/clk-imx7.c
@@ -777,11 +777,18 @@ static int imx7_ccm_probe(struct device_d *dev)
 	clks[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_gate4("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0);
 	clks[IMX7D_EPDC_PIXEL_ROOT_CLK] = imx_clk_gate4("epdc_pixel_root_clk", "epdc_pixel_post_div", base + 0x44a0, 0);
 	clks[IMX7D_LCDIF_PIXEL_ROOT_CLK] = imx_clk_gate4("lcdif_pixel_root_clk", "lcdif_pixel_post_div", base + 0x44b0, 0);
-	clks[IMX7D_ENET1_REF_ROOT_CLK] = imx_clk_gate4("enet1_ref_root_clk", "enet1_ref_post_div", base + 0x44e0, 0);
-	clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate4("enet1_time_root_clk", "enet1_time_post_div", base + 0x44f0, 0);
-	clks[IMX7D_ENET2_REF_ROOT_CLK] = imx_clk_gate4("enet2_ref_root_clk", "enet2_ref_post_div", base + 0x4500, 0);
-	clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate4("enet2_time_root_clk", "enet2_time_post_div", base + 0x4510, 0);
+
+	/*
+	 * Linux code controls gates at 0x44e0, 0x44f0, 0x4500 and 0x4500. However, these do not seem to
+	 * exist in hardware. According to the reference manual the ethernet clocks are controlled by
+	 * gates at 0x4700 and 0x4710
+	 */
+	clks[IMX7D_ENET1_REF_ROOT_CLK] = imx_clk_gate4("enet1_ref_root_clk", "enet1_ref_post_div", base + 0x4700, 0);
+	clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate_shared("enet1_time_root_clk", "enet1_time_post_div", "enet1_ref_root_clk");
+	clks[IMX7D_ENET2_REF_ROOT_CLK] = imx_clk_gate4("enet2_ref_root_clk", "enet2_ref_post_div", base + 0x4710, 0);
+	clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate_shared("enet2_time_root_clk", "enet2_time_post_div", "enet2_ref_root_clk");
 	clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_gate4("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520, 0);
+
 	clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk", "eim_post_div", base + 0x4160, 0);
 	clks[IMX7D_NAND_ROOT_CLK] = imx_clk_gate4("nand_root_clk", "nand_post_div", base + 0x4140, 0);
 	clks[IMX7D_QSPI_ROOT_CLK] = imx_clk_gate4("qspi_root_clk", "qspi_post_div", base + 0x4150, 0);
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 019114848..8da806403 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -98,6 +98,12 @@ static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
 	return clk_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE);
 }
 
+static inline struct clk *imx_clk_gate_shared(const char *name, const char *parent,
+					      const char *shared)
+{
+	return clk_gate_shared(name, parent, shared, CLK_SET_RATE_PARENT);
+}
+
 struct clk *imx_clk_pllv1(const char *name, const char *parent,
 		void __iomem *base);
 
-- 
2.11.0


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barebox@lists.infradead.org
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^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH 8/9] clk: i.MX7: do not register PLL bypass clocks as separate clocks
  2017-02-06  6:50 i.MX7 Ethernet clock fixes Sascha Hauer
                   ` (6 preceding siblings ...)
  2017-02-06  6:50 ` [PATCH 7/9] clk: i.MX7: Fix ethernet clocks Sascha Hauer
@ 2017-02-06  6:50 ` Sascha Hauer
  2017-02-06  6:50 ` [PATCH 9/9] clk: i.MX7: setup ethernet clocks Sascha Hauer
  8 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2017-02-06  6:50 UTC (permalink / raw)
  To: Barebox List

In the Kernel the bypass bits in the PLLs are now registered as
separate clocks and are no longer handled in the PLL code. In
barebox we haven't made this step and there currently seems to
be no reason to do so.
This means that the bypass bits are currently modified in both
the PLL driver and in the separate clocks which does not work
properly. Drop all the bypass clocks to let the bypass bits
be handled in the PLL driver exclusively.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/imx/clk-imx7.c | 204 +++++++++++++++++++--------------------------
 1 file changed, 85 insertions(+), 119 deletions(-)

diff --git a/drivers/clk/imx/clk-imx7.c b/drivers/clk/imx/clk-imx7.c
index eb072b73e..6bf123419 100644
--- a/drivers/clk/imx/clk-imx7.c
+++ b/drivers/clk/imx/clk-imx7.c
@@ -24,32 +24,32 @@
 #include "clk.h"
 
 static struct clk *clks[IMX7D_CLK_END];
-static const char *arm_a7_sel[] = { "osc", "pll_arm_main_clk",
-	"pll_enet_500m_clk", "pll_dram_main_clk",
-	"pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_audio_post_div",
+static const char *arm_a7_sel[] = { "osc", "pll_arm_main",
+	"pll_enet_500m_clk", "pll_dram_main",
+	"pll_sys_main", "pll_sys_pfd0_392m_clk", "pll_audio_post_div",
 	"pll_usb_main_clk", };
 
 static const char *arm_m4_sel[] = { "osc", "pll_sys_main_240m_clk",
 	"pll_enet_250m_clk", "pll_sys_pfd2_270m_clk",
-	"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk",
+	"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main",
 	"pll_usb_main_clk", };
 
 static const char *arm_m0_sel[] = { "osc", "pll_sys_main_120m_clk",
 	"pll_enet_125m_clk", "pll_sys_pfd2_135m_clk",
-	"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk",
+	"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main",
 	"pll_usb_main_clk", };
 
 static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
 	"pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd5_clk",
-	"pll_audio_post_div", "pll_video_main_clk", "pll_sys_pfd7_clk", };
+	"pll_audio_post_div", "pll_video_main", "pll_sys_pfd7_clk", };
 
 static const char *disp_axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
 	"pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd6_clk",
-	"pll_sys_pfd7_clk", "pll_audio_post_div", "pll_video_main_clk", };
+	"pll_sys_pfd7_clk", "pll_audio_post_div", "pll_video_main", };
 
 static const char *enet_axi_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
 	"pll_dram_533m_clk", "pll_enet_250m_clk",
-	"pll_sys_main_240m_clk", "pll_audio_post_div", "pll_video_main_clk",
+	"pll_sys_main_240m_clk", "pll_audio_post_div", "pll_video_main",
 	"pll_sys_pfd4_clk", };
 
 static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
@@ -60,25 +60,25 @@ static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
 static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
 	"pll_dram_533m_clk", "pll_sys_pfd0_392m_clk",
 	"pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_post_div",
-	"pll_video_main_clk", };
+	"pll_video_main", };
 
-static const char *dram_phym_sel[] = { "pll_dram_main_clk",
+static const char *dram_phym_sel[] = { "pll_dram_main",
 	"dram_phym_alt_clk", };
 
-static const char *dram_sel[] = { "pll_dram_main_clk",
+static const char *dram_sel[] = { "pll_dram_main",
 	"dram_alt_root_clk", };
 
 static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk",
-	"pll_sys_main_clk", "pll_enet_500m_clk",
+	"pll_sys_main", "pll_enet_500m_clk",
 	"pll_usb_main_clk", "pll_sys_pfd7_clk", "pll_audio_post_div",
-	"pll_video_main_clk", };
+	"pll_video_main", };
 
 static const char *dram_alt_sel[] = { "osc", "pll_dram_533m_clk",
-	"pll_sys_main_clk", "pll_enet_500m_clk",
+	"pll_sys_main", "pll_enet_500m_clk",
 	"pll_enet_250m_clk", "pll_sys_pfd0_392m_clk",
 	"pll_audio_post_div", "pll_sys_pfd2_270m_clk", };
 
-static const char *usb_hsic_sel[] = { "osc", "pll_sys_main_clk",
+static const char *usb_hsic_sel[] = { "osc", "pll_sys_main",
 	"pll_usb_main_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk",
 	"pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", };
 
@@ -92,63 +92,63 @@ static const char *pcie_phy_sel[] = { "osc", "pll_enet_100m_clk",
 	"ext_clk_4", "pll_sys_pfd0_392m_clk", };
 
 static const char *epdc_pixel_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
-	"pll_dram_533m_clk", "pll_sys_main_clk", "pll_sys_pfd5_clk",
-	"pll_sys_pfd6_clk", "pll_sys_pfd7_clk", "pll_video_main_clk", };
+	"pll_dram_533m_clk", "pll_sys_main", "pll_sys_pfd5_clk",
+	"pll_sys_pfd6_clk", "pll_sys_pfd7_clk", "pll_video_main", };
 
 static const char *lcdif_pixel_sel[] = { "osc", "pll_sys_pfd5_clk",
 	"pll_dram_533m_clk", "ext_clk_3", "pll_sys_pfd4_clk",
-	"pll_sys_pfd2_270m_clk", "pll_video_main_clk",
+	"pll_sys_pfd2_270m_clk", "pll_video_main",
 	"pll_usb_main_clk", };
 
 static const char *mipi_dsi_sel[] = { "osc", "pll_sys_pfd5_clk",
-	"pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk",
-	"pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_post_div", };
+	"pll_sys_pfd3_clk", "pll_sys_main", "pll_sys_pfd0_196m_clk",
+	"pll_dram_533m_clk", "pll_video_main", "pll_audio_post_div", };
 
 static const char *mipi_csi_sel[] = { "osc", "pll_sys_pfd4_clk",
-	"pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk",
-	"pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_post_div", };
+	"pll_sys_pfd3_clk", "pll_sys_main", "pll_sys_pfd0_196m_clk",
+	"pll_dram_533m_clk", "pll_video_main", "pll_audio_post_div", };
 
 static const char *mipi_dphy_sel[] = { "osc", "pll_sys_main_120m_clk",
 	"pll_dram_533m_clk", "pll_sys_pfd5_clk", "ref_1m_clk", "ext_clk_2",
-	"pll_video_main_clk", "ext_clk_3", };
+	"pll_video_main", "ext_clk_3", };
 
 static const char *sai1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
-	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",
+	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main",
 	"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", };
 
 static const char *sai2_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
-	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",
+	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main",
 	"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", };
 
 static const char *sai3_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
-	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",
+	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main",
 	"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_3", };
 
 static const char *spdif_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
-	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",
+	"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main",
 	"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_3_clk", };
 
 static const char *enet1_ref_sel[] = { "osc", "pll_enet_125m_clk",
 	"pll_enet_50m_clk", "pll_enet_25m_clk",
-	"pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_main_clk",
+	"pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_main",
 	"ext_clk_4", };
 
 static const char *enet1_time_sel[] = { "osc", "pll_enet_100m_clk",
 	"pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3",
-	"ext_clk_4", "pll_video_main_clk", };
+	"ext_clk_4", "pll_video_main", };
 
 static const char *enet2_ref_sel[] = { "osc", "pll_enet_125m_clk",
 	"pll_enet_50m_clk", "pll_enet_25m_clk",
-	"pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_main_clk",
+	"pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_main",
 	"ext_clk_4", };
 
 static const char *enet2_time_sel[] = { "osc", "pll_enet_100m_clk",
 	"pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3",
-	"ext_clk_4", "pll_video_main_clk", };
+	"ext_clk_4", "pll_video_main", };
 
 static const char *enet_phy_ref_sel[] = { "osc", "pll_enet_25m_clk",
 	"pll_enet_50m_clk", "pll_enet_125m_clk",
-	"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk",
+	"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main",
 	"pll_sys_pfd3_clk", };
 
 static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
@@ -156,10 +156,10 @@ static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
 	"pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_enet_125m_clk",
 	"pll_usb_main_clk", };
 
-static const char *nand_sel[] = { "osc", "pll_sys_main_clk",
+static const char *nand_sel[] = { "osc", "pll_sys_main",
 	"pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd3_clk",
 	"pll_enet_500m_clk", "pll_enet_250m_clk",
-	"pll_video_main_clk", };
+	"pll_video_main", };
 
 static const char *qspi_sel[] = { "osc", "pll_sys_pfd4_clk",
 	"pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd3_clk",
@@ -178,113 +178,113 @@ static const char *usdhc3_sel[] = { "osc", "pll_sys_pfd0_392m_clk",
 	"pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", };
 
 static const char *can1_sel[] = { "osc", "pll_sys_main_120m_clk",
-	"pll_dram_533m_clk", "pll_sys_main_clk",
+	"pll_dram_533m_clk", "pll_sys_main",
 	"pll_enet_40m_clk", "pll_usb_main_clk", "ext_clk_1",
 	"ext_clk_4", };
 
 static const char *can2_sel[] = { "osc", "pll_sys_main_120m_clk",
-	"pll_dram_533m_clk", "pll_sys_main_clk",
+	"pll_dram_533m_clk", "pll_sys_main",
 	"pll_enet_40m_clk", "pll_usb_main_clk", "ext_clk_1",
 	"ext_clk_3", };
 
 static const char *i2c1_sel[] = { "osc", "pll_sys_main_120m_clk",
 	"pll_enet_50m_clk", "pll_dram_533m_clk",
-	"pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",
+	"pll_audio_post_div", "pll_video_main", "pll_usb_main_clk",
 	"pll_sys_pfd2_135m_clk", };
 
 static const char *i2c2_sel[] = { "osc", "pll_sys_main_120m_clk",
 	"pll_enet_50m_clk", "pll_dram_533m_clk",
-	"pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",
+	"pll_audio_post_div", "pll_video_main", "pll_usb_main_clk",
 	"pll_sys_pfd2_135m_clk", };
 
 static const char *i2c3_sel[] = { "osc", "pll_sys_main_120m_clk",
 	"pll_enet_50m_clk", "pll_dram_533m_clk",
-	"pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",
+	"pll_audio_post_div", "pll_video_main", "pll_usb_main_clk",
 	"pll_sys_pfd2_135m_clk", };
 
 static const char *i2c4_sel[] = { "osc", "pll_sys_main_120m_clk",
 	"pll_enet_50m_clk", "pll_dram_533m_clk",
-	"pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",
+	"pll_audio_post_div", "pll_video_main", "pll_usb_main_clk",
 	"pll_sys_pfd2_135m_clk", };
 
 static const char *uart1_sel[] = { "osc", "pll_sys_main_240m_clk",
 	"pll_enet_40m_clk", "pll_enet_100m_clk",
-	"pll_sys_main_clk", "ext_clk_2", "ext_clk_4",
+	"pll_sys_main", "ext_clk_2", "ext_clk_4",
 	"pll_usb_main_clk", };
 
 static const char *uart2_sel[] = { "osc", "pll_sys_main_240m_clk",
 	"pll_enet_40m_clk", "pll_enet_100m_clk",
-	"pll_sys_main_clk", "ext_clk_2", "ext_clk_3",
+	"pll_sys_main", "ext_clk_2", "ext_clk_3",
 	"pll_usb_main_clk", };
 
 static const char *uart3_sel[] = { "osc", "pll_sys_main_240m_clk",
 	"pll_enet_40m_clk", "pll_enet_100m_clk",
-	"pll_sys_main_clk", "ext_clk_2", "ext_clk_4",
+	"pll_sys_main", "ext_clk_2", "ext_clk_4",
 	"pll_usb_main_clk", };
 
 static const char *uart4_sel[] = { "osc", "pll_sys_main_240m_clk",
 	"pll_enet_40m_clk", "pll_enet_100m_clk",
-	"pll_sys_main_clk", "ext_clk_2", "ext_clk_3",
+	"pll_sys_main", "ext_clk_2", "ext_clk_3",
 	"pll_usb_main_clk", };
 
 static const char *uart5_sel[] = { "osc", "pll_sys_main_240m_clk",
 	"pll_enet_40m_clk", "pll_enet_100m_clk",
-	"pll_sys_main_clk", "ext_clk_2", "ext_clk_4",
+	"pll_sys_main", "ext_clk_2", "ext_clk_4",
 	"pll_usb_main_clk", };
 
 static const char *uart6_sel[] = { "osc", "pll_sys_main_240m_clk",
 	"pll_enet_40m_clk", "pll_enet_100m_clk",
-	"pll_sys_main_clk", "ext_clk_2", "ext_clk_3",
+	"pll_sys_main", "ext_clk_2", "ext_clk_3",
 	"pll_usb_main_clk", };
 
 static const char *uart7_sel[] = { "osc", "pll_sys_main_240m_clk",
 	"pll_enet_40m_clk", "pll_enet_100m_clk",
-	"pll_sys_main_clk", "ext_clk_2", "ext_clk_4",
+	"pll_sys_main", "ext_clk_2", "ext_clk_4",
 	"pll_usb_main_clk", };
 
 static const char *ecspi1_sel[] = { "osc", "pll_sys_main_240m_clk",
 	"pll_enet_40m_clk", "pll_sys_main_120m_clk",
-	"pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk",
+	"pll_sys_main", "pll_sys_pfd4_clk", "pll_enet_250m_clk",
 	"pll_usb_main_clk", };
 
 static const char *ecspi2_sel[] = { "osc", "pll_sys_main_240m_clk",
 	"pll_enet_40m_clk", "pll_sys_main_120m_clk",
-	"pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk",
+	"pll_sys_main", "pll_sys_pfd4_clk", "pll_enet_250m_clk",
 	"pll_usb_main_clk", };
 
 static const char *ecspi3_sel[] = { "osc", "pll_sys_main_240m_clk",
 	"pll_enet_40m_clk", "pll_sys_main_120m_clk",
-	"pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk",
+	"pll_sys_main", "pll_sys_pfd4_clk", "pll_enet_250m_clk",
 	"pll_usb_main_clk", };
 
 static const char *ecspi4_sel[] = { "osc", "pll_sys_main_240m_clk",
 	"pll_enet_40m_clk", "pll_sys_main_120m_clk",
-	"pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk",
+	"pll_sys_main", "pll_sys_pfd4_clk", "pll_enet_250m_clk",
 	"pll_usb_main_clk", };
 
 static const char *pwm1_sel[] = { "osc", "pll_enet_100m_clk",
 	"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
-	"ext_clk_1", "ref_1m_clk", "pll_video_main_clk", };
+	"ext_clk_1", "ref_1m_clk", "pll_video_main", };
 
 static const char *pwm2_sel[] = { "osc", "pll_enet_100m_clk",
 	"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
-	"ext_clk_1", "ref_1m_clk", "pll_video_main_clk", };
+	"ext_clk_1", "ref_1m_clk", "pll_video_main", };
 
 static const char *pwm3_sel[] = { "osc", "pll_enet_100m_clk",
 	"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
-	"ext_clk_2", "ref_1m_clk", "pll_video_main_clk", };
+	"ext_clk_2", "ref_1m_clk", "pll_video_main", };
 
 static const char *pwm4_sel[] = { "osc", "pll_enet_100m_clk",
 	"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
-	"ext_clk_2", "ref_1m_clk", "pll_video_main_clk", };
+	"ext_clk_2", "ref_1m_clk", "pll_video_main", };
 
 static const char *flextimer1_sel[] = { "osc", "pll_enet_100m_clk",
 	"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
-	"ext_clk_3", "ref_1m_clk", "pll_video_main_clk", };
+	"ext_clk_3", "ref_1m_clk", "pll_video_main", };
 
 static const char *flextimer2_sel[] = { "osc", "pll_enet_100m_clk",
 	"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
-	"ext_clk_3", "ref_1m_clk", "pll_video_main_clk", };
+	"ext_clk_3", "ref_1m_clk", "pll_video_main", };
 
 static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
 	"pll_sys_main_120m_clk", "pll_dram_533m_clk",
@@ -293,23 +293,23 @@ static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
 
 static const char *sim2_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
 	"pll_sys_main_120m_clk", "pll_dram_533m_clk",
-	"pll_usb_main_clk", "pll_video_main_clk", "pll_enet_125m_clk",
+	"pll_usb_main_clk", "pll_video_main", "pll_enet_125m_clk",
 	"pll_sys_pfd7_clk", };
 
 static const char *gpt1_sel[] = { "osc", "pll_enet_100m_clk",
-	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",
+	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main",
 	"ref_1m_clk", "pll_audio_post_div", "ext_clk_1", };
 
 static const char *gpt2_sel[] = { "osc", "pll_enet_100m_clk",
-	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",
+	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main",
 	"ref_1m_clk", "pll_audio_post_div", "ext_clk_2", };
 
 static const char *gpt3_sel[] = { "osc", "pll_enet_100m_clk",
-	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",
+	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main",
 	"ref_1m_clk", "pll_audio_post_div", "ext_clk_3", };
 
 static const char *gpt4_sel[] = { "osc", "pll_enet_100m_clk",
-	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",
+	"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main",
 	"ref_1m_clk", "pll_audio_post_div", "ext_clk_4", };
 
 static const char *trace_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
@@ -324,12 +324,12 @@ static const char *wdog_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
 
 static const char *csi_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
 	"pll_sys_main_120m_clk", "pll_dram_533m_clk",
-	"pll_enet_125m_clk", "pll_audio_post_div", "pll_video_main_clk",
+	"pll_enet_125m_clk", "pll_audio_post_div", "pll_video_main",
 	"pll_usb_main_clk", };
 
 static const char *audio_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
 	"pll_sys_main_120m_clk", "pll_dram_533m_clk",
-	"pll_enet_125m_clk", "pll_audio_post_div", "pll_video_main_clk",
+	"pll_enet_125m_clk", "pll_audio_post_div", "pll_video_main",
 	"pll_usb_main_clk", };
 
 static const char *wrclk_sel[] = { "osc", "pll_enet_40m_clk",
@@ -337,30 +337,22 @@ static const char *wrclk_sel[] = { "osc", "pll_enet_40m_clk",
 	"pll_sys_main_240m_clk", "pll_sys_pfd2_270m_clk",
 	"pll_enet_500m_clk", "pll_sys_pfd7_clk", };
 
-static const char *clko1_sel[] = { "osc", "pll_sys_main_clk",
+static const char *clko1_sel[] = { "osc", "pll_sys_main",
 	"pll_sys_main_240m_clk", "pll_sys_pfd0_196m_clk", "pll_sys_pfd3_clk",
 	"pll_enet_500m_clk", "pll_dram_533m_clk", "ref_1m_clk", };
 
 static const char *clko2_sel[] = { "osc", "pll_sys_main_240m_clk",
 	"pll_sys_pfd0_392m_clk", "pll_sys_pfd1_166m_clk", "pll_sys_pfd4_clk",
-	"pll_audio_post_div", "pll_video_main_clk", "ckil", };
+	"pll_audio_post_div", "pll_video_main", "ckil", };
 
-static const char *lvds1_sel[] = { "pll_arm_main_clk",
-	"pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_332m_clk",
+static const char *lvds1_sel[] = { "pll_arm_main",
+	"pll_sys_main", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_332m_clk",
 	"pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk",
 	"pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk",
-	"pll_audio_post_div", "pll_video_main_clk", "pll_enet_500m_clk",
+	"pll_audio_post_div", "pll_video_main", "pll_enet_500m_clk",
 	"pll_enet_250m_clk", "pll_enet_125m_clk", "pll_enet_100m_clk",
 	"pll_enet_50m_clk", "pll_enet_40m_clk", "pll_enet_25m_clk",
-	"pll_dram_main_clk", };
-
-static const char *pll_bypass_src_sel[] = { "osc", "dummy", };
-static const char *pll_arm_bypass_sel[] = { "pll_arm_main", "pll_arm_main_src", };
-static const char *pll_dram_bypass_sel[] = { "pll_dram_main", "pll_dram_main_src", };
-static const char *pll_sys_bypass_sel[] = { "pll_sys_main", "pll_sys_main_src", };
-static const char *pll_enet_bypass_sel[] = { "pll_enet_main", "pll_enet_main_src", };
-static const char *pll_audio_bypass_sel[] = { "pll_audio_main", "pll_audio_main_src", };
-static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_src", };
+	"pll_dram_main", };
 
 static int const clks_init_on[] __initconst = {
 	IMX7D_ARM_A7_ROOT_CLK, IMX7D_MAIN_AXI_ROOT_CLK,
@@ -398,13 +390,6 @@ static int imx7_ccm_probe(struct device_d *dev)
 
 	base = anatop_base;
 
-	clks[IMX7D_PLL_ARM_MAIN_SRC]  = imx_clk_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
-	clks[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
-	clks[IMX7D_PLL_SYS_MAIN_SRC]  = imx_clk_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
-	clks[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
-	clks[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
-	clks[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
-
 	clks[IMX7D_PLL_ARM_MAIN]  = imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "osc", base + 0x60, 0x7f);
 	clks[IMX7D_PLL_DRAM_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_dram_main", "osc", base + 0x70, 0x7f);
 	clks[IMX7D_PLL_SYS_MAIN]  = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll_sys_main", "osc", base + 0xb0, 0x1);
@@ -412,33 +397,20 @@ static int imx7_ccm_probe(struct device_d *dev)
 	clks[IMX7D_PLL_AUDIO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_audio_main", "osc", base + 0xf0, 0x7f);
 	clks[IMX7D_PLL_VIDEO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_video_main", "osc", base + 0x130, 0x7f);
 
-	clks[IMX7D_PLL_ARM_MAIN_BYPASS]  = imx_clk_mux_p("pll_arm_main_bypass", base + 0x60, 16, 1, pll_arm_bypass_sel, ARRAY_SIZE(pll_arm_bypass_sel));
-	clks[IMX7D_PLL_DRAM_MAIN_BYPASS] = imx_clk_mux_p("pll_dram_main_bypass", base + 0x70, 16, 1, pll_dram_bypass_sel, ARRAY_SIZE(pll_dram_bypass_sel));
-	clks[IMX7D_PLL_SYS_MAIN_BYPASS]  = imx_clk_mux_p("pll_sys_main_bypass", base + 0xb0, 16, 1, pll_sys_bypass_sel, ARRAY_SIZE(pll_sys_bypass_sel));
-	clks[IMX7D_PLL_ENET_MAIN_BYPASS] = imx_clk_mux_p("pll_enet_main_bypass", base + 0xe0, 16, 1, pll_enet_bypass_sel, ARRAY_SIZE(pll_enet_bypass_sel));
-	clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_p("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel));
-	clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_p("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel));
-
-	clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13);
-	clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13);
-	clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13);
-	clks[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13);
-	clks[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13);
-
-	clks[IMX7D_PLL_SYS_PFD0_392M_CLK] = imx_clk_pfd("pll_sys_pfd0_392m_clk", "pll_sys_main_clk", base + 0xc0, 0);
-	clks[IMX7D_PLL_SYS_PFD1_332M_CLK] = imx_clk_pfd("pll_sys_pfd1_332m_clk", "pll_sys_main_clk", base + 0xc0, 1);
-	clks[IMX7D_PLL_SYS_PFD2_270M_CLK] = imx_clk_pfd("pll_sys_pfd2_270m_clk", "pll_sys_main_clk", base + 0xc0, 2);
-
-	clks[IMX7D_PLL_SYS_PFD3_CLK] = imx_clk_pfd("pll_sys_pfd3_clk", "pll_sys_main_clk", base + 0xc0, 3);
-	clks[IMX7D_PLL_SYS_PFD4_CLK] = imx_clk_pfd("pll_sys_pfd4_clk", "pll_sys_main_clk", base + 0xd0, 0);
-	clks[IMX7D_PLL_SYS_PFD5_CLK] = imx_clk_pfd("pll_sys_pfd5_clk", "pll_sys_main_clk", base + 0xd0, 1);
-	clks[IMX7D_PLL_SYS_PFD6_CLK] = imx_clk_pfd("pll_sys_pfd6_clk", "pll_sys_main_clk", base + 0xd0, 2);
-	clks[IMX7D_PLL_SYS_PFD7_CLK] = imx_clk_pfd("pll_sys_pfd7_clk", "pll_sys_main_clk", base + 0xd0, 3);
-
-	clks[IMX7D_PLL_SYS_MAIN_480M] = imx_clk_fixed_factor("pll_sys_main_480m", "pll_sys_main_clk", 1, 1);
-	clks[IMX7D_PLL_SYS_MAIN_240M] = imx_clk_fixed_factor("pll_sys_main_240m", "pll_sys_main_clk", 1, 2);
-	clks[IMX7D_PLL_SYS_MAIN_120M] = imx_clk_fixed_factor("pll_sys_main_120m", "pll_sys_main_clk", 1, 4);
-	clks[IMX7D_PLL_DRAM_MAIN_533M] = imx_clk_fixed_factor("pll_dram_533m", "pll_dram_main_clk", 1, 2);
+	clks[IMX7D_PLL_SYS_PFD0_392M_CLK] = imx_clk_pfd("pll_sys_pfd0_392m_clk", "pll_sys_main", base + 0xc0, 0);
+	clks[IMX7D_PLL_SYS_PFD1_332M_CLK] = imx_clk_pfd("pll_sys_pfd1_332m_clk", "pll_sys_main", base + 0xc0, 1);
+	clks[IMX7D_PLL_SYS_PFD2_270M_CLK] = imx_clk_pfd("pll_sys_pfd2_270m_clk", "pll_sys_main", base + 0xc0, 2);
+
+	clks[IMX7D_PLL_SYS_PFD3_CLK] = imx_clk_pfd("pll_sys_pfd3_clk", "pll_sys_main", base + 0xc0, 3);
+	clks[IMX7D_PLL_SYS_PFD4_CLK] = imx_clk_pfd("pll_sys_pfd4_clk", "pll_sys_main", base + 0xd0, 0);
+	clks[IMX7D_PLL_SYS_PFD5_CLK] = imx_clk_pfd("pll_sys_pfd5_clk", "pll_sys_main", base + 0xd0, 1);
+	clks[IMX7D_PLL_SYS_PFD6_CLK] = imx_clk_pfd("pll_sys_pfd6_clk", "pll_sys_main", base + 0xd0, 2);
+	clks[IMX7D_PLL_SYS_PFD7_CLK] = imx_clk_pfd("pll_sys_pfd7_clk", "pll_sys_main", base + 0xd0, 3);
+
+	clks[IMX7D_PLL_SYS_MAIN_480M] = imx_clk_fixed_factor("pll_sys_main_480m", "pll_sys_main", 1, 1);
+	clks[IMX7D_PLL_SYS_MAIN_240M] = imx_clk_fixed_factor("pll_sys_main_240m", "pll_sys_main", 1, 2);
+	clks[IMX7D_PLL_SYS_MAIN_120M] = imx_clk_fixed_factor("pll_sys_main_120m", "pll_sys_main", 1, 4);
+	clks[IMX7D_PLL_DRAM_MAIN_533M] = imx_clk_fixed_factor("pll_dram_533m", "pll_dram_main", 1, 2);
 
 	clks[IMX7D_PLL_SYS_MAIN_480M_CLK] = imx_clk_gate_dis("pll_sys_main_480m_clk", "pll_sys_main_480m", base + 0xb0, 4);
 	clks[IMX7D_PLL_SYS_MAIN_240M_CLK] = imx_clk_gate_dis("pll_sys_main_240m_clk", "pll_sys_main_240m", base + 0xb0, 5);
@@ -453,7 +425,7 @@ static int imx7_ccm_probe(struct device_d *dev)
 	clks[IMX7D_PLL_SYS_PFD1_166M_CLK] = imx_clk_gate_dis("pll_sys_pfd1_166m_clk", "pll_sys_pfd1_166m", base + 0xb0, 27);
 	clks[IMX7D_PLL_SYS_PFD2_135M_CLK] = imx_clk_gate_dis("pll_sys_pfd2_135m_clk", "pll_sys_pfd2_135m", base + 0xb0, 28);
 
-	clks[IMX7D_PLL_ENET_MAIN_CLK] = imx_clk_fixed_factor("pll_enet_main_clk", "pll_enet_main_bypass", 1, 1);
+	clks[IMX7D_PLL_ENET_MAIN_CLK] = imx_clk_fixed_factor("pll_enet_main_clk", "pll_enet_main", 1, 1);
 	clks[IMX7D_PLL_ENET_MAIN_500M] = imx_clk_fixed_factor("pll_enet_500m", "pll_enet_main_clk", 1, 2);
 	clks[IMX7D_PLL_ENET_MAIN_250M] = imx_clk_fixed_factor("pll_enet_250m", "pll_enet_main_clk", 1, 4);
 	clks[IMX7D_PLL_ENET_MAIN_125M] = imx_clk_fixed_factor("pll_enet_125m", "pll_enet_main_clk", 1, 8);
@@ -866,12 +838,6 @@ static int imx7_clk_setup(void)
 	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
 		clk_enable(clks[clks_init_on[i]]);
 
-	clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
-	clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
-	clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
-	clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
-	clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
-
 	/* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
 	clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
 
-- 
2.11.0


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^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH 9/9] clk: i.MX7: setup ethernet clocks
  2017-02-06  6:50 i.MX7 Ethernet clock fixes Sascha Hauer
                   ` (7 preceding siblings ...)
  2017-02-06  6:50 ` [PATCH 8/9] clk: i.MX7: do not register PLL bypass clocks as separate clocks Sascha Hauer
@ 2017-02-06  6:50 ` Sascha Hauer
  8 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2017-02-06  6:50 UTC (permalink / raw)
  To: Barebox List

Reparent ethernet clocks so that they can be used by the
fec driver. The values are the same as U-Boot uses.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/imx/clk-imx7.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/clk/imx/clk-imx7.c b/drivers/clk/imx/clk-imx7.c
index 6bf123419..d3a036c0c 100644
--- a/drivers/clk/imx/clk-imx7.c
+++ b/drivers/clk/imx/clk-imx7.c
@@ -844,6 +844,17 @@ static int imx7_clk_setup(void)
 	/* set uart module clock's parent clock source that must be great then 80MHz */
 	clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
 
+	clk_set_parent(clks[IMX7D_ENET1_REF_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_125M_CLK]);
+	clk_set_parent(clks[IMX7D_ENET1_TIME_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_100M_CLK]);
+	clk_set_parent(clks[IMX7D_ENET2_REF_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_125M_CLK]);
+	clk_set_parent(clks[IMX7D_ENET2_TIME_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_100M_CLK]);
+
+	clk_set_rate(clks[IMX7D_PLL_SYS_PFD4_CLK], 392000000);
+	clk_set_parent(clks[IMX7D_ENET_AXI_ROOT_SRC], clks[IMX7D_PLL_SYS_PFD4_CLK]);
+	clk_set_rate(clks[IMX7D_ENET_AXI_ROOT_CLK], 197000000);
+	clk_set_rate(clks[IMX7D_ENET1_TIME_ROOT_CLK], 25000000);
+	clk_set_rate(clks[IMX7D_ENET2_TIME_ROOT_CLK], 25000000);
+
 	return 0;
 }
 postcore_initcall(imx7_clk_setup);
-- 
2.11.0


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^ permalink raw reply	[flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-02-06  6:54 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-02-06  6:50 i.MX7 Ethernet clock fixes Sascha Hauer
2017-02-06  6:50 ` [PATCH 1/9] clk: Keep enable count consistent over reparent Sascha Hauer
2017-02-06  6:50 ` [PATCH 2/9] clk: implement CLK_OPS_PARENT_ENABLE Sascha Hauer
2017-02-06  6:50 ` [PATCH 3/9] clk: i.MX: clk-gate2: Allow to pass flags Sascha Hauer
2017-02-06  6:50 ` [PATCH 4/9] clk: i.MX: Pass CLK_OPS_PARENT_ENABLE where necessary Sascha Hauer
2017-02-06  6:50 ` [PATCH 5/9] clk: i.MX7: do clock reparenting when all clocks are initialized Sascha Hauer
2017-02-06  6:50 ` [PATCH 6/9] clk: Add support for shared gates Sascha Hauer
2017-02-06  6:50 ` [PATCH 7/9] clk: i.MX7: Fix ethernet clocks Sascha Hauer
2017-02-06  6:50 ` [PATCH 8/9] clk: i.MX7: do not register PLL bypass clocks as separate clocks Sascha Hauer
2017-02-06  6:50 ` [PATCH 9/9] clk: i.MX7: setup ethernet clocks Sascha Hauer

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