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From: Lucas Stach <l.stach@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH 3/3] ARM: execute DMB before trying to flush cache
Date: Wed,  1 Mar 2017 15:26:41 +0100	[thread overview]
Message-ID: <20170301142641.6596-3-l.stach@pengutronix.de> (raw)
In-Reply-To: <20170301142641.6596-1-l.stach@pengutronix.de>

The CPU write buffer needs to be coherent with the cache, otherwise
we might flush stale entries with the actual data stuck in the cache.

This is really important on newer CPU core with bigger write buffers.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/cpu/cache-armv7.S | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index c19618bde182..aaa8bf8c62e1 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -68,6 +68,7 @@ ENTRY(v7_mmu_cache_flush)
 ENDPROC(v7_mmu_cache_flush)
 
 ENTRY(__v7_mmu_cache_flush_invalidate)
+		mcr	p15, 0, r12, c7, c10, 5	@ DMB
 		mrc	p15, 0, r12, c0, c1, 5	@ read ID_MMFR1
 		tst	r12, #0xf << 16		@ hierarchical cache (ARMv7)
 		mov	r12, #0
-- 
2.11.0


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  parent reply	other threads:[~2017-03-01 14:27 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-01 14:26 [PATCH 1/3] ARM: align exception vectors to 32 byte Lucas Stach
2017-03-01 14:26 ` [PATCH 2/3] ARM: correctly identify ARMv6 K/Z Lucas Stach
2017-03-01 17:55   ` Jean-Christophe PLAGNIOL-VILLARD
2017-03-02 10:42     ` Lucas Stach
2017-03-03  6:04       ` Sascha Hauer
2017-03-03 14:26         ` Jean-Christophe PLAGNIOL-VILLARD
2017-03-01 14:26 ` Lucas Stach [this message]
2017-03-02  8:08 ` [PATCH 1/3] ARM: align exception vectors to 32 byte Uwe Kleine-König
2017-03-03  6:06 ` Sascha Hauer

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