[PATCH 1/3] ARM: align exception vectors to 32 byte

[PATCH 1/3] ARM: align exception vectors to 32 byte

[Lucas Stach]

On ARMv7 the exception vectors inside the barebox binary are used directly
by remapping the vectors base through the VBAR register. While VBAR allows
to remap the exception vectors freely, it still imposes a minimum alignment
of 32 byte, as the lower bits are treated as the exception vector offset.
Enforce this alignment inside the barebox binary.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/lib32/barebox.lds.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/lib32/barebox.lds.S b/arch/arm/lib32/barebox.lds.S
index b49c269a4346..e7b87b7cdd18 100644
--- a/arch/arm/lib32/barebox.lds.S
+++ b/arch/arm/lib32/barebox.lds.S
@@ -45,7 +45,7 @@ SECTIONS
 		__bare_init_start = .;
 		*(.text_bare_init*)
 		__bare_init_end = .;
-		. = ALIGN(4);
+		. = ALIGN(0x20);
 		__exceptions_start = .;
 		KEEP(*(.text_exceptions*))
 		__exceptions_stop = .;
-- 
2.11.0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 2/3] ARM: correctly identify ARMv6 K/Z

[Lucas Stach]

The ARMv6 K/Z derivatives have a v7 compatible MMU, but all other parts
(including the cache handling) is still at v6. As we don't make use of
the more advanced features of the v7 MMU in Barebox, it's okay to just
override this to properly identify the CPU as ARMv6.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/cpu/cpuinfo.c             | 8 ++++++++
 arch/arm/include/asm/system_info.h | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/arch/arm/cpu/cpuinfo.c b/arch/arm/cpu/cpuinfo.c
index 86e19d9780d5..175475b038dc 100644
--- a/arch/arm/cpu/cpuinfo.c
+++ b/arch/arm/cpu/cpuinfo.c
@@ -165,6 +165,14 @@ static int do_cpuinfo(int argc, char *argv[])
 	} else
 		cpu_arch = CPU_ARCH_UNKNOWN;
 
+	/*
+	 * Special case for ARMv6 (K/Z) (has v7 compatible MMU, but is v6
+	 * otherwise). The below check just matches all ARMv6, as done in the
+	 * Linux kernel.
+	 */
+	if ((mainid & 0x7f000) == 0x7b000)
+		cpu_arch = CPU_ARCH_ARMv6;
+
 	switch (cpu_arch) {
 	case CPU_ARCH_ARMv3:
 		architecture = "v3";
diff --git a/arch/arm/include/asm/system_info.h b/arch/arm/include/asm/system_info.h
index 25fffd268177..a27b79e6dd08 100644
--- a/arch/arm/include/asm/system_info.h
+++ b/arch/arm/include/asm/system_info.h
@@ -188,6 +188,14 @@ static inline int arm_early_get_cpu_architecture(void)
 		cpu_arch = CPU_ARCH_UNKNOWN;
 #endif
 
+	/*
+	 * Special case for ARMv6 (K/Z) (has v7 compatible MMU, but is v6
+	 * otherwise). The below check just matches all ARMv6, as done in the
+	 * Linux kernel.
+	 */
+	if ((read_cpuid_id() & 0x7f000) == 0x7b000)
+		cpu_arch = CPU_ARCH_ARMv6;
+
 	return cpu_arch;
 }
 
-- 
2.11.0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 3/3] ARM: execute DMB before trying to flush cache

[Lucas Stach]

The CPU write buffer needs to be coherent with the cache, otherwise
we might flush stale entries with the actual data stuck in the cache.

This is really important on newer CPU core with bigger write buffers.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/cpu/cache-armv7.S | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index c19618bde182..aaa8bf8c62e1 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -68,6 +68,7 @@ ENTRY(v7_mmu_cache_flush)
 ENDPROC(v7_mmu_cache_flush)
 
 ENTRY(__v7_mmu_cache_flush_invalidate)
+		mcr	p15, 0, r12, c7, c10, 5	@ DMB
 		mrc	p15, 0, r12, c0, c1, 5	@ read ID_MMFR1
 		tst	r12, #0xf << 16		@ hierarchical cache (ARMv7)
 		mov	r12, #0
-- 
2.11.0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH 2/3] ARM: correctly identify ARMv6 K/Z

[Jean-Christophe PLAGNIOL-VILLARD]

On 15:26 Wed 01 Mar     , Lucas Stach wrote:
> The ARMv6 K/Z derivatives have a v7 compatible MMU, but all other parts
> (including the cache handling) is still at v6. As we don't make use of
> the more advanced features of the v7 MMU in Barebox, it's okay to just
> override this to properly identify the CPU as ARMv6.
evenif we do not use it now I do not liek the idea to report it as ARMv6

It will be better to report it correctly

Best Regards,
J.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  arch/arm/cpu/cpuinfo.c             | 8 ++++++++
>  arch/arm/include/asm/system_info.h | 8 ++++++++
>  2 files changed, 16 insertions(+)
> 
> diff --git a/arch/arm/cpu/cpuinfo.c b/arch/arm/cpu/cpuinfo.c
> index 86e19d9780d5..175475b038dc 100644
> --- a/arch/arm/cpu/cpuinfo.c
> +++ b/arch/arm/cpu/cpuinfo.c
> @@ -165,6 +165,14 @@ static int do_cpuinfo(int argc, char *argv[])
>  	} else
>  		cpu_arch = CPU_ARCH_UNKNOWN;
>  
> +	/*
> +	 * Special case for ARMv6 (K/Z) (has v7 compatible MMU, but is v6
> +	 * otherwise). The below check just matches all ARMv6, as done in the
> +	 * Linux kernel.
> +	 */
> +	if ((mainid & 0x7f000) == 0x7b000)
> +		cpu_arch = CPU_ARCH_ARMv6;
> +
>  	switch (cpu_arch) {
>  	case CPU_ARCH_ARMv3:
>  		architecture = "v3";
> diff --git a/arch/arm/include/asm/system_info.h b/arch/arm/include/asm/system_info.h
> index 25fffd268177..a27b79e6dd08 100644
> --- a/arch/arm/include/asm/system_info.h
> +++ b/arch/arm/include/asm/system_info.h
> @@ -188,6 +188,14 @@ static inline int arm_early_get_cpu_architecture(void)
>  		cpu_arch = CPU_ARCH_UNKNOWN;
>  #endif
>  
> +	/*
> +	 * Special case for ARMv6 (K/Z) (has v7 compatible MMU, but is v6
> +	 * otherwise). The below check just matches all ARMv6, as done in the
> +	 * Linux kernel.
> +	 */
> +	if ((read_cpuid_id() & 0x7f000) == 0x7b000)
> +		cpu_arch = CPU_ARCH_ARMv6;
> +
>  	return cpu_arch;
>  }
>  
> -- 
> 2.11.0
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH 1/3] ARM: align exception vectors to 32 byte

[Uwe Kleine-König]

Hello Lucas,

On Wed, Mar 01, 2017 at 03:26:39PM +0100, Lucas Stach wrote:
> On ARMv7 the exception vectors inside the barebox binary are used directly
> by remapping the vectors base through the VBAR register. While VBAR allows
> to remap the exception vectors freely, it still imposes a minimum alignment
> of 32 byte, as the lower bits are treated as the exception vector offset.
> Enforce this alignment inside the barebox binary.

maybe put a part of this into a comment?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH 2/3] ARM: correctly identify ARMv6 K/Z

[Lucas Stach]

Am Mittwoch, den 01.03.2017, 18:55 +0100 schrieb Jean-Christophe
PLAGNIOL-VILLARD:
> On 15:26 Wed 01 Mar     , Lucas Stach wrote:
> > The ARMv6 K/Z derivatives have a v7 compatible MMU, but all other
> > parts
> > (including the cache handling) is still at v6. As we don't make use
> > of
> > the more advanced features of the v7 MMU in Barebox, it's okay to
> > just
> > override this to properly identify the CPU as ARMv6.
> 
> evenif we do not use it now I do not liek the idea to report it as
> ARMv6
> 
> It will be better to report it correctly
> 
Weather you like it or not, ARM1176 is ARMv6 with a v7 MMU bolted on,
so reporting it as ARMv6 is the correct thing to do. Also we use the
same detection logic to decide about which cache functions to use and
ARMv6 K/Z still need the ARMv6 cache functions instead of the ARMv7
ones.

The MMU versions is about the least interesting features of those CPUs
as far as Barebox is concerned.

Regards,
Lucas

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH 2/3] ARM: correctly identify ARMv6 K/Z

[Sascha Hauer]

On Thu, Mar 02, 2017 at 11:42:48AM +0100, Lucas Stach wrote:
> Am Mittwoch, den 01.03.2017, 18:55 +0100 schrieb Jean-Christophe
> PLAGNIOL-VILLARD:
> > On 15:26 Wed 01 Mar     , Lucas Stach wrote:
> > > The ARMv6 K/Z derivatives have a v7 compatible MMU, but all other
> > > parts
> > > (including the cache handling) is still at v6. As we don't make use
> > > of
> > > the more advanced features of the v7 MMU in Barebox, it's okay to
> > > just
> > > override this to properly identify the CPU as ARMv6.
> > 
> > evenif we do not use it now I do not liek the idea to report it as
> > ARMv6
> > 
> > It will be better to report it correctly
> > 
> Weather you like it or not, ARM1176 is ARMv6 with a v7 MMU bolted on,
> so reporting it as ARMv6 is the correct thing to do.

+1

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH 1/3] ARM: align exception vectors to 32 byte

[Sascha Hauer]

On Wed, Mar 01, 2017 at 03:26:39PM +0100, Lucas Stach wrote:
> On ARMv7 the exception vectors inside the barebox binary are used directly
> by remapping the vectors base through the VBAR register. While VBAR allows
> to remap the exception vectors freely, it still imposes a minimum alignment
> of 32 byte, as the lower bits are treated as the exception vector offset.
> Enforce this alignment inside the barebox binary.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  arch/arm/lib32/barebox.lds.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Applied, thanks

Sascha

> 
> diff --git a/arch/arm/lib32/barebox.lds.S b/arch/arm/lib32/barebox.lds.S
> index b49c269a4346..e7b87b7cdd18 100644
> --- a/arch/arm/lib32/barebox.lds.S
> +++ b/arch/arm/lib32/barebox.lds.S
> @@ -45,7 +45,7 @@ SECTIONS
>  		__bare_init_start = .;
>  		*(.text_bare_init*)
>  		__bare_init_end = .;
> -		. = ALIGN(4);
> +		. = ALIGN(0x20);
>  		__exceptions_start = .;
>  		KEEP(*(.text_exceptions*))
>  		__exceptions_stop = .;
> -- 
> 2.11.0
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH 2/3] ARM: correctly identify ARMv6 K/Z

[Jean-Christophe PLAGNIOL-VILLARD]

On 07:04 Fri 03 Mar     , Sascha Hauer wrote:
> On Thu, Mar 02, 2017 at 11:42:48AM +0100, Lucas Stach wrote:
> > Am Mittwoch, den 01.03.2017, 18:55 +0100 schrieb Jean-Christophe
> > PLAGNIOL-VILLARD:
> > > On 15:26 Wed 01 Mar     , Lucas Stach wrote:
> > > > The ARMv6 K/Z derivatives have a v7 compatible MMU, but all other
> > > > parts
> > > > (including the cache handling) is still at v6. As we don't make use
> > > > of
> > > > the more advanced features of the v7 MMU in Barebox, it's okay to
> > > > just
> > > > override this to properly identify the CPU as ARMv6.
> > > 
> > > evenif we do not use it now I do not liek the idea to report it as
> > > ARMv6
> > > 
> > > It will be better to report it correctly
> > > 
> > Weather you like it or not, ARM1176 is ARMv6 with a v7 MMU bolted on,
> > so reporting it as ARMv6 is the correct thing to do.

except when will want to use them we will have to fix the detection it's
better to do it at assignation to check the arm1176 or v6

Best Regards,
J.

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox