* [PATCH 0/7] SoCFPGA: add support for Arria10
@ 2017-04-03 10:55 Steffen Trumtrar
2017-04-03 10:55 ` [PATCH 1/7] ARM: socfpga: rename socfpga->cyclone5 Steffen Trumtrar
` (7 more replies)
0 siblings, 8 replies; 12+ messages in thread
From: Steffen Trumtrar @ 2017-04-03 10:55 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
Hi!
Although Cyclone5 and Arria10 share a lot of the peripherals,
they a different in the critical parts (SDRAM controller, clock setup,...)
The Arria10 has a larger OCRAM (64KB vs 256KB), that is why we can
omit the xload support for now. The xload support can be added, once
Arria10 boards that need to program the FPGA very early (might be needed for
the SDRAM controller) are available.
Supported peripherals are:
- clock manager
- serial
- ethernet
- i2c
- MMC
Regards,
Steffen
Steffen Trumtrar (7):
ARM: socfpga: rename socfpga->cyclone5
clk: socfpga: move driver to subdirectory
net: designware: add dwmac-3.72a compatible
ARM: socfpga: add arria10 support
clk: socfpga: add arria10 clk drivers
ARM: socfpga: add support for reflex achilles board
ARM: socfpga: add arria10 defconfig
arch/arm/Kconfig | 6 +-
arch/arm/boards/Makefile | 1 +
arch/arm/boards/altera-socdk/board.c | 2 +-
.../boards/altera-socdk/iocsr_config_cyclone5.c | 2 +-
arch/arm/boards/altera-socdk/lowlevel.c | 4 +-
arch/arm/boards/ebv-socrates/board.c | 2 +-
.../boards/ebv-socrates/iocsr_config_cyclone5.c | 2 +-
arch/arm/boards/ebv-socrates/lowlevel.c | 4 +-
arch/arm/boards/reflex-achilles/Makefile | 2 +
arch/arm/boards/reflex-achilles/hps.xml | 351 +++++++++
arch/arm/boards/reflex-achilles/lowlevel.c | 48 ++
.../boards/reflex-achilles/pinmux-config-arria10.c | 105 +++
.../boards/reflex-achilles/pll-config-arria10.c | 55 ++
arch/arm/boards/terasic-de0-nano-soc/board.c | 2 +-
.../terasic-de0-nano-soc/iocsr_config_cyclone5.c | 2 +-
arch/arm/boards/terasic-de0-nano-soc/lowlevel.c | 4 +-
arch/arm/boards/terasic-sockit/board.c | 1 -
.../boards/terasic-sockit/iocsr_config_cyclone5.c | 2 +-
arch/arm/boards/terasic-sockit/lowlevel.c | 4 +-
arch/arm/configs/socfpga-arria10_defconfig | 89 +++
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_arria10_achilles.dts | 124 ++++
arch/arm/mach-socfpga/Kconfig | 23 +
arch/arm/mach-socfpga/Makefile | 10 +-
.../{bootsource.c => arria10-bootsource.c} | 14 +-
arch/arm/mach-socfpga/arria10-clock-manager.c | 807 +++++++++++++++++++++
arch/arm/mach-socfpga/arria10-generic.c | 85 +++
arch/arm/mach-socfpga/arria10-init.c | 275 +++++++
arch/arm/mach-socfpga/arria10-reset-manager.c | 422 +++++++++++
arch/arm/mach-socfpga/arria10-sdram.c | 557 ++++++++++++++
arch/arm/mach-socfpga/cyclone5-bootsource.c | 100 +++
.../{clock-manager.c => cyclone5-clock-manager.c} | 4 +-
...e-controller.c => cyclone5-freeze-controller.c} | 2 +-
arch/arm/mach-socfpga/cyclone5-generic.c | 210 ++++++
arch/arm/mach-socfpga/{init.c => cyclone5-init.c} | 10 +-
.../{reset-manager.c => cyclone5-reset-manager.c} | 4 +-
.../{scan-manager.c => cyclone5-scan-manager.c} | 4 +-
...{system-manager.c => cyclone5-system-manager.c} | 4 +-
arch/arm/mach-socfpga/generic.c | 104 ---
.../include/mach/arria10-clock-manager.h | 249 +++++++
.../arm/mach-socfpga/include/mach/arria10-pinmux.h | 128 ++++
arch/arm/mach-socfpga/include/mach/arria10-regs.h | 114 +++
.../include/mach/arria10-reset-manager.h | 119 +++
arch/arm/mach-socfpga/include/mach/arria10-sdram.h | 353 +++++++++
.../include/mach/arria10-system-manager.h | 97 +++
.../{clock-manager.h => cyclone5-clock-manager.h} | 6 +-
...e-controller.h => cyclone5-freeze-controller.h} | 6 +-
.../mach/{socfpga-regs.h => cyclone5-regs.h} | 0
.../{reset-manager.h => cyclone5-reset-manager.h} | 0
.../{scan-manager.h => cyclone5-scan-manager.h} | 2 +-
.../{sdram_config.h => cyclone5-sdram-config.h} | 6 +-
.../include/mach/{sdram.h => cyclone5-sdram.h} | 0
.../mach/{sequencer.c => cyclone5-sequencer.c} | 6 +-
.../mach/{sequencer.h => cyclone5-sequencer.h} | 0
...{system-manager.h => cyclone5-system-manager.h} | 0
arch/arm/mach-socfpga/include/mach/generic.h | 35 +
arch/arm/mach-socfpga/include/mach/pll_config.h | 2 +-
arch/arm/mach-socfpga/include/mach/sdram_io.h | 2 +-
.../mach-socfpga/include/mach/sequencer_defines.h | 6 -
arch/arm/mach-socfpga/include/mach/system.h | 0
arch/arm/mach-socfpga/include/mach/tclrpt.h | 2 +-
arch/arm/mach-socfpga/nic301.c | 2 +-
arch/arm/mach-socfpga/xload.c | 96 +--
drivers/clk/Makefile | 2 +-
drivers/clk/socfpga/Makefile | 3 +
drivers/clk/socfpga/clk-gate-a10.c | 197 +++++
drivers/clk/socfpga/clk-periph-a10.c | 130 ++++
drivers/clk/socfpga/clk-pll-a10.c | 143 ++++
drivers/clk/{socfpga.c => socfpga/clk.c} | 11 +-
drivers/clk/socfpga/clk.h | 90 +++
drivers/firmware/socfpga.c | 8 +-
drivers/net/designware.c | 3 +
images/Makefile.socfpga | 12 +
scripts/socfpga_import_preloader | 2 +-
scripts/socfpga_mkimage.c | 1 +
scripts/socfpga_xml_to_config.sh | 86 +++
76 files changed, 5097 insertions(+), 270 deletions(-)
create mode 100644 arch/arm/boards/reflex-achilles/Makefile
create mode 100644 arch/arm/boards/reflex-achilles/hps.xml
create mode 100644 arch/arm/boards/reflex-achilles/lowlevel.c
create mode 100644 arch/arm/boards/reflex-achilles/pinmux-config-arria10.c
create mode 100644 arch/arm/boards/reflex-achilles/pll-config-arria10.c
create mode 100644 arch/arm/configs/socfpga-arria10_defconfig
create mode 100644 arch/arm/dts/socfpga_arria10_achilles.dts
rename arch/arm/mach-socfpga/{bootsource.c => arria10-bootsource.c} (77%)
create mode 100644 arch/arm/mach-socfpga/arria10-clock-manager.c
create mode 100644 arch/arm/mach-socfpga/arria10-generic.c
create mode 100644 arch/arm/mach-socfpga/arria10-init.c
create mode 100644 arch/arm/mach-socfpga/arria10-reset-manager.c
create mode 100644 arch/arm/mach-socfpga/arria10-sdram.c
create mode 100644 arch/arm/mach-socfpga/cyclone5-bootsource.c
rename arch/arm/mach-socfpga/{clock-manager.c => cyclone5-clock-manager.c} (99%)
rename arch/arm/mach-socfpga/{freeze-controller.c => cyclone5-freeze-controller.c} (99%)
create mode 100644 arch/arm/mach-socfpga/cyclone5-generic.c
rename arch/arm/mach-socfpga/{init.c => cyclone5-init.c} (89%)
rename arch/arm/mach-socfpga/{reset-manager.c => cyclone5-reset-manager.c} (96%)
rename arch/arm/mach-socfpga/{scan-manager.c => cyclone5-scan-manager.c} (98%)
rename arch/arm/mach-socfpga/{system-manager.c => cyclone5-system-manager.c} (93%)
delete mode 100644 arch/arm/mach-socfpga/generic.c
create mode 100644 arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h
create mode 100644 arch/arm/mach-socfpga/include/mach/arria10-pinmux.h
create mode 100644 arch/arm/mach-socfpga/include/mach/arria10-regs.h
create mode 100644 arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h
create mode 100644 arch/arm/mach-socfpga/include/mach/arria10-sdram.h
create mode 100644 arch/arm/mach-socfpga/include/mach/arria10-system-manager.h
rename arch/arm/mach-socfpga/include/mach/{clock-manager.h => cyclone5-clock-manager.h} (99%)
rename arch/arm/mach-socfpga/include/mach/{freeze-controller.h => cyclone5-freeze-controller.h} (96%)
rename arch/arm/mach-socfpga/include/mach/{socfpga-regs.h => cyclone5-regs.h} (100%)
rename arch/arm/mach-socfpga/include/mach/{reset-manager.h => cyclone5-reset-manager.h} (100%)
rename arch/arm/mach-socfpga/include/mach/{scan-manager.h => cyclone5-scan-manager.h} (99%)
rename arch/arm/mach-socfpga/include/mach/{sdram_config.h => cyclone5-sdram-config.h} (98%)
rename arch/arm/mach-socfpga/include/mach/{sdram.h => cyclone5-sdram.h} (100%)
rename arch/arm/mach-socfpga/include/mach/{sequencer.c => cyclone5-sequencer.c} (99%)
rename arch/arm/mach-socfpga/include/mach/{sequencer.h => cyclone5-sequencer.h} (100%)
rename arch/arm/mach-socfpga/include/mach/{system-manager.h => cyclone5-system-manager.h} (100%)
mode change 100755 => 100644 arch/arm/mach-socfpga/include/mach/sdram_io.h
delete mode 100644 arch/arm/mach-socfpga/include/mach/sequencer_defines.h
mode change 100755 => 100644 arch/arm/mach-socfpga/include/mach/system.h
mode change 100755 => 100644 arch/arm/mach-socfpga/include/mach/tclrpt.h
create mode 100644 drivers/clk/socfpga/Makefile
create mode 100644 drivers/clk/socfpga/clk-gate-a10.c
create mode 100644 drivers/clk/socfpga/clk-periph-a10.c
create mode 100644 drivers/clk/socfpga/clk-pll-a10.c
rename drivers/clk/{socfpga.c => socfpga/clk.c} (96%)
create mode 100644 drivers/clk/socfpga/clk.h
create mode 100755 scripts/socfpga_xml_to_config.sh
--
2.11.0
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/7] ARM: socfpga: rename socfpga->cyclone5
2017-04-03 10:55 [PATCH 0/7] SoCFPGA: add support for Arria10 Steffen Trumtrar
@ 2017-04-03 10:55 ` Steffen Trumtrar
2017-04-03 10:55 ` [PATCH 2/7] clk: socfpga: move driver to subdirectory Steffen Trumtrar
` (6 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Steffen Trumtrar @ 2017-04-03 10:55 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
Prepare the SoCFPGA code base for different system types
(Arria10, Stratix10,...).
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/boards/altera-socdk/board.c | 2 +-
.../boards/altera-socdk/iocsr_config_cyclone5.c | 2 +-
arch/arm/boards/altera-socdk/lowlevel.c | 4 +-
arch/arm/boards/ebv-socrates/board.c | 2 +-
.../boards/ebv-socrates/iocsr_config_cyclone5.c | 2 +-
arch/arm/boards/ebv-socrates/lowlevel.c | 4 +-
arch/arm/boards/terasic-de0-nano-soc/board.c | 2 +-
.../terasic-de0-nano-soc/iocsr_config_cyclone5.c | 2 +-
arch/arm/boards/terasic-de0-nano-soc/lowlevel.c | 4 +-
arch/arm/boards/terasic-sockit/board.c | 1 -
.../boards/terasic-sockit/iocsr_config_cyclone5.c | 2 +-
arch/arm/boards/terasic-sockit/lowlevel.c | 4 +-
arch/arm/mach-socfpga/Makefile | 6 +-
.../{bootsource.c => cyclone5-bootsource.c} | 12 +-
.../{clock-manager.c => cyclone5-clock-manager.c} | 4 +-
...e-controller.c => cyclone5-freeze-controller.c} | 2 +-
arch/arm/mach-socfpga/cyclone5-generic.c | 210 +++++++++++++++++++++
arch/arm/mach-socfpga/{init.c => cyclone5-init.c} | 10 +-
.../{reset-manager.c => cyclone5-reset-manager.c} | 4 +-
.../{scan-manager.c => cyclone5-scan-manager.c} | 4 +-
...{system-manager.c => cyclone5-system-manager.c} | 4 +-
.../{clock-manager.h => cyclone5-clock-manager.h} | 6 +-
...e-controller.h => cyclone5-freeze-controller.h} | 6 +-
.../mach/{socfpga-regs.h => cyclone5-regs.h} | 0
.../{reset-manager.h => cyclone5-reset-manager.h} | 0
.../{scan-manager.h => cyclone5-scan-manager.h} | 2 +-
.../{sdram_config.h => cyclone5-sdram-config.h} | 6 +-
.../include/mach/{sdram.h => cyclone5-sdram.h} | 0
.../mach/{sequencer.c => cyclone5-sequencer.c} | 6 +-
.../mach/{sequencer.h => cyclone5-sequencer.h} | 0
...{system-manager.h => cyclone5-system-manager.h} | 0
arch/arm/mach-socfpga/include/mach/pll_config.h | 2 +-
arch/arm/mach-socfpga/include/mach/sdram_io.h | 2 +-
.../mach-socfpga/include/mach/sequencer_defines.h | 6 -
arch/arm/mach-socfpga/include/mach/system.h | 0
arch/arm/mach-socfpga/include/mach/tclrpt.h | 2 +-
arch/arm/mach-socfpga/nic301.c | 2 +-
arch/arm/mach-socfpga/xload.c | 4 +-
drivers/firmware/socfpga.c | 8 +-
scripts/socfpga_import_preloader | 2 +-
40 files changed, 271 insertions(+), 70 deletions(-)
rename arch/arm/mach-socfpga/{bootsource.c => cyclone5-bootsource.c} (79%)
rename arch/arm/mach-socfpga/{clock-manager.c => cyclone5-clock-manager.c} (99%)
rename arch/arm/mach-socfpga/{freeze-controller.c => cyclone5-freeze-controller.c} (99%)
create mode 100644 arch/arm/mach-socfpga/cyclone5-generic.c
rename arch/arm/mach-socfpga/{init.c => cyclone5-init.c} (89%)
rename arch/arm/mach-socfpga/{reset-manager.c => cyclone5-reset-manager.c} (96%)
rename arch/arm/mach-socfpga/{scan-manager.c => cyclone5-scan-manager.c} (98%)
rename arch/arm/mach-socfpga/{system-manager.c => cyclone5-system-manager.c} (93%)
rename arch/arm/mach-socfpga/include/mach/{clock-manager.h => cyclone5-clock-manager.h} (99%)
rename arch/arm/mach-socfpga/include/mach/{freeze-controller.h => cyclone5-freeze-controller.h} (96%)
rename arch/arm/mach-socfpga/include/mach/{socfpga-regs.h => cyclone5-regs.h} (100%)
rename arch/arm/mach-socfpga/include/mach/{reset-manager.h => cyclone5-reset-manager.h} (100%)
rename arch/arm/mach-socfpga/include/mach/{scan-manager.h => cyclone5-scan-manager.h} (99%)
rename arch/arm/mach-socfpga/include/mach/{sdram_config.h => cyclone5-sdram-config.h} (98%)
rename arch/arm/mach-socfpga/include/mach/{sdram.h => cyclone5-sdram.h} (100%)
rename arch/arm/mach-socfpga/include/mach/{sequencer.c => cyclone5-sequencer.c} (99%)
rename arch/arm/mach-socfpga/include/mach/{sequencer.h => cyclone5-sequencer.h} (100%)
rename arch/arm/mach-socfpga/include/mach/{system-manager.h => cyclone5-system-manager.h} (100%)
mode change 100755 => 100644 arch/arm/mach-socfpga/include/mach/sdram_io.h
delete mode 100644 arch/arm/mach-socfpga/include/mach/sequencer_defines.h
mode change 100755 => 100644 arch/arm/mach-socfpga/include/mach/system.h
mode change 100755 => 100644 arch/arm/mach-socfpga/include/mach/tclrpt.h
diff --git a/arch/arm/boards/altera-socdk/board.c b/arch/arm/boards/altera-socdk/board.c
index d7fb923a043b..f4b1dcd3249f 100644
--- a/arch/arm/boards/altera-socdk/board.c
+++ b/arch/arm/boards/altera-socdk/board.c
@@ -8,7 +8,7 @@
#include <linux/sizes.h>
#include <fcntl.h>
#include <fs.h>
-#include <mach/socfpga-regs.h>
+#include <mach/cyclone5-regs.h>
static int ksz9021rn_phy_fixup(struct phy_device *dev)
{
diff --git a/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c b/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c
index 07a4485f1fe6..9777d15dfebf 100644
--- a/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c
+++ b/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c
@@ -27,7 +27,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include <mach/scan-manager.h>
+#include <mach/cyclone5-scan-manager.h>
static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)]
= {
diff --git a/arch/arm/boards/altera-socdk/lowlevel.c b/arch/arm/boards/altera-socdk/lowlevel.c
index 02c995fe4522..8cfe8391596d 100644
--- a/arch/arm/boards/altera-socdk/lowlevel.c
+++ b/arch/arm/boards/altera-socdk/lowlevel.c
@@ -7,13 +7,13 @@
#include <debug_ll.h>
#include <asm/cache.h>
#include "sdram_config.h"
-#include <mach/sdram_config.h>
+#include <mach/cyclone5-sdram-config.h>
#include "pinmux_config.c"
#include "pll_config.h"
#include <mach/pll_config.h>
#include "sequencer_defines.h"
#include "sequencer_auto.h"
-#include <mach/sequencer.c>
+#include <mach/cyclone5-sequencer.c>
#include "sequencer_auto_inst_init.c"
#include "sequencer_auto_ac_init.c"
#include "iocsr_config_cyclone5.c"
diff --git a/arch/arm/boards/ebv-socrates/board.c b/arch/arm/boards/ebv-socrates/board.c
index f3207b88efdf..965150f9a3be 100644
--- a/arch/arm/boards/ebv-socrates/board.c
+++ b/arch/arm/boards/ebv-socrates/board.c
@@ -11,7 +11,7 @@
#include <linux/sizes.h>
#include <fcntl.h>
#include <fs.h>
-#include <mach/socfpga-regs.h>
+#include <mach/cyclone5-regs.h>
static int phy_fixup(struct phy_device *dev)
{
diff --git a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c
index ab6733f92bcf..9a814cba796c 100644
--- a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c
+++ b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c
@@ -27,7 +27,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include <mach/scan-manager.h>
+#include <mach/cyclone5-scan-manager.h>
static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
0x00000000,
diff --git a/arch/arm/boards/ebv-socrates/lowlevel.c b/arch/arm/boards/ebv-socrates/lowlevel.c
index ea4e1d746a95..9643269f8e16 100644
--- a/arch/arm/boards/ebv-socrates/lowlevel.c
+++ b/arch/arm/boards/ebv-socrates/lowlevel.c
@@ -7,13 +7,13 @@
#include <mach/generic.h>
#include <debug_ll.h>
#include "sdram_config.h"
-#include <mach/sdram_config.h>
+#include <mach/cyclone5-sdram-config.h>
#include "pinmux_config.c"
#include "pll_config.h"
#include <mach/pll_config.h>
#include "sequencer_defines.h"
#include "sequencer_auto.h"
-#include <mach/sequencer.c>
+#include <mach/cyclone5-sequencer.c>
#include "sequencer_auto_inst_init.c"
#include "sequencer_auto_ac_init.c"
#include "iocsr_config_cyclone5.c"
diff --git a/arch/arm/boards/terasic-de0-nano-soc/board.c b/arch/arm/boards/terasic-de0-nano-soc/board.c
index 919bfc8c543a..8e69319d17b8 100644
--- a/arch/arm/boards/terasic-de0-nano-soc/board.c
+++ b/arch/arm/boards/terasic-de0-nano-soc/board.c
@@ -8,7 +8,7 @@
#include <linux/sizes.h>
#include <fcntl.h>
#include <fs.h>
-#include <mach/socfpga-regs.h>
+#include <mach/cyclone5-regs.h>
static int phy_fixup(struct phy_device *dev)
{
diff --git a/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
index 4e9ac7fb7721..d5098055ff63 100644
--- a/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
+++ b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c
@@ -27,7 +27,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include <mach/scan-manager.h>
+#include <mach/cyclone5-scan-manager.h>
static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
0x00000000,
diff --git a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
index 6d937abda589..1d5ea6b12a52 100644
--- a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
+++ b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
@@ -7,13 +7,13 @@
#include <debug_ll.h>
#include <asm/cache.h>
#include "sdram_config.h"
-#include <mach/sdram_config.h>
+#include <mach/cyclone5-sdram-config.h>
#include "pinmux_config.c"
#include "pll_config.h"
#include <mach/pll_config.h>
#include "sequencer_defines.h"
#include "sequencer_auto.h"
-#include <mach/sequencer.c>
+#include <mach/cyclone5-sequencer.c>
#include "sequencer_auto_inst_init.c"
#include "sequencer_auto_ac_init.c"
#include "iocsr_config_cyclone5.c"
diff --git a/arch/arm/boards/terasic-sockit/board.c b/arch/arm/boards/terasic-sockit/board.c
index 53cd36834fc1..ec6831599803 100644
--- a/arch/arm/boards/terasic-sockit/board.c
+++ b/arch/arm/boards/terasic-sockit/board.c
@@ -8,7 +8,6 @@
#include <linux/sizes.h>
#include <fcntl.h>
#include <fs.h>
-#include <mach/socfpga-regs.h>
static int phy_fixup(struct phy_device *dev)
{
diff --git a/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c
index 117d7f4ebcc9..9367b0d11072 100644
--- a/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c
+++ b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c
@@ -27,7 +27,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include <mach/scan-manager.h>
+#include <mach/cyclone5-scan-manager.h>
static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
0x00000000,
diff --git a/arch/arm/boards/terasic-sockit/lowlevel.c b/arch/arm/boards/terasic-sockit/lowlevel.c
index 8012783df3f8..0a6eb2136517 100644
--- a/arch/arm/boards/terasic-sockit/lowlevel.c
+++ b/arch/arm/boards/terasic-sockit/lowlevel.c
@@ -7,13 +7,13 @@
#include <debug_ll.h>
#include <asm/cache.h>
#include "sdram_config.h"
-#include <mach/sdram_config.h>
+#include <mach/cyclone5-sdram-config.h>
#include "pinmux_config.c"
#include "pll_config.h"
#include <mach/pll_config.h>
#include "sequencer_defines.h"
#include "sequencer_auto.h"
-#include <mach/sequencer.c>
+#include <mach/cyclone5-sequencer.c>
#include "sequencer_auto_inst_init.c"
#include "sequencer_auto_ac_init.c"
#include "iocsr_config_cyclone5.c"
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index dea0e075d145..30b796dd3b4f 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -1,4 +1,4 @@
-obj-y += generic.o nic301.o bootsource.o reset-manager.o
-pbl-y += init.o freeze-controller.o scan-manager.o system-manager.o
-pbl-y += clock-manager.o
+pbl-y += cyclone5-init.o cyclone5-freeze-controller.o cyclone5-scan-manager.o cyclone5-system-manager.o
+pbl-y += cyclone5-clock-manager.o
+obj-y += cyclone5-generic.o nic301.o cyclone5-bootsource.o cyclone5-reset-manager.o
obj-$(CONFIG_ARCH_SOCFPGA_XLOAD) += xload.o
diff --git a/arch/arm/mach-socfpga/bootsource.c b/arch/arm/mach-socfpga/cyclone5-bootsource.c
similarity index 79%
rename from arch/arm/mach-socfpga/bootsource.c
rename to arch/arm/mach-socfpga/cyclone5-bootsource.c
index 739f0b5c0e94..da4102c4f531 100644
--- a/arch/arm/mach-socfpga/bootsource.c
+++ b/arch/arm/mach-socfpga/cyclone5-bootsource.c
@@ -16,17 +16,17 @@
#include <environment.h>
#include <init.h>
#include <io.h>
-#include <mach/socfpga-regs.h>
-#include <mach/system-manager.h>
+#include <mach/cyclone5-system-manager.h>
+#include <mach/cyclone5-regs.h>
-#define SYSMGR_BOOTINFO 0x14
+#define CYCLONE5_SYSMGR_BOOTINFO 0x14
-static int socfpga_boot_save_loc(void)
+static int cyclone5_boot_save_loc(void)
{
enum bootsource src = BOOTSOURCE_UNKNOWN;
uint32_t val;
- val = readl(CYCLONE5_SYSMGR_ADDRESS + SYSMGR_BOOTINFO);
+ val = readl(CYCLONE5_SYSMGR_ADDRESS + CYCLONE5_SYSMGR_BOOTINFO);
switch (val & 0x7) {
case 0:
@@ -54,4 +54,4 @@ static int socfpga_boot_save_loc(void)
return 0;
}
-core_initcall(socfpga_boot_save_loc);
+core_initcall(cyclone5_boot_save_loc);
diff --git a/arch/arm/mach-socfpga/clock-manager.c b/arch/arm/mach-socfpga/cyclone5-clock-manager.c
similarity index 99%
rename from arch/arm/mach-socfpga/clock-manager.c
rename to arch/arm/mach-socfpga/cyclone5-clock-manager.c
index f17371365fe4..79c8b6bf2874 100644
--- a/arch/arm/mach-socfpga/clock-manager.c
+++ b/arch/arm/mach-socfpga/cyclone5-clock-manager.c
@@ -17,8 +17,8 @@
#include <common.h>
#include <io.h>
-#include <mach/clock-manager.h>
-#include <mach/socfpga-regs.h>
+#include <mach/cyclone5-clock-manager.h>
+#include <mach/cyclone5-regs.h>
#include <mach/generic.h>
static inline void cm_wait_for_lock(void __iomem *cm, uint32_t mask)
diff --git a/arch/arm/mach-socfpga/freeze-controller.c b/arch/arm/mach-socfpga/cyclone5-freeze-controller.c
similarity index 99%
rename from arch/arm/mach-socfpga/freeze-controller.c
rename to arch/arm/mach-socfpga/cyclone5-freeze-controller.c
index 570bdeb7353f..87160161b0e6 100644
--- a/arch/arm/mach-socfpga/freeze-controller.c
+++ b/arch/arm/mach-socfpga/cyclone5-freeze-controller.c
@@ -18,7 +18,7 @@
#include <common.h>
#include <io.h>
#include <mach/generic.h>
-#include <mach/freeze-controller.h>
+#include <mach/cyclone5-freeze-controller.h>
#define SYSMGR_FRZCTRL_LOOP_PARAM (1000)
#define SYSMGR_FRZCTRL_DELAY_LOOP_PARAM (10)
diff --git a/arch/arm/mach-socfpga/cyclone5-generic.c b/arch/arm/mach-socfpga/cyclone5-generic.c
new file mode 100644
index 000000000000..3f49a9a542eb
--- /dev/null
+++ b/arch/arm/mach-socfpga/cyclone5-generic.c
@@ -0,0 +1,210 @@
+#include <common.h>
+#include <malloc.h>
+#include <envfs.h>
+#include <init.h>
+#include <io.h>
+#include <fs.h>
+#include <mci.h>
+#include <linux/clkdev.h>
+#include <linux/clk.h>
+#include <linux/stat.h>
+#include <linux/sizes.h>
+#include <asm/memory.h>
+#include <mach/cyclone5-system-manager.h>
+#include <mach/cyclone5-reset-manager.h>
+#include <mach/cyclone5-regs.h>
+#include <mach/generic.h>
+#include <mach/nic301.h>
+#include <platform_data/dw_mmc.h>
+#include <platform_data/serial-ns16550.h>
+#include <platform_data/cadence_qspi.h>
+
+#define SYSMGR_SDMMCGRP_CTRL_REG (CYCLONE5_SYSMGR_ADDRESS + 0x108)
+#define SYSMGR_SDMMC_CTRL_SMPLSEL(smplsel) (((smplsel) & 0x7) << 3)
+#define SYSMGR_SDMMC_CTRL_DRVSEL(drvsel) ((drvsel) & 0x7)
+
+enum socfpga_clks {
+ timer, mmc, qspi_clk, uart, clk_max
+};
+
+static struct clk *clks[clk_max];
+
+#if defined(CONFIG_MCI_DW)
+static struct dw_mmc_platform_data mmc_pdata = {
+ .bus_width_caps = MMC_CAP_4_BIT_DATA,
+ .ciu_div = 3,
+};
+
+void socfpga_cyclone5_mmc_init(void)
+{
+ clks[mmc] = clk_fixed("mmc", 400000000);
+ clkdev_add_physbase(clks[mmc], CYCLONE5_SDMMC_ADDRESS, NULL);
+ add_generic_device("dw_mmc", 0, NULL, CYCLONE5_SDMMC_ADDRESS, SZ_4K,
+ IORESOURCE_MEM, &mmc_pdata);
+}
+#else
+void socfpga_cyclone5_mmc_init(void)
+{
+ pr_debug("%s: MMC support not compiled in!\n", __func__);
+
+ return;
+}
+#endif
+
+#if defined(CONFIG_SPI_CADENCE_QUADSPI)
+static struct cadence_qspi_platform_data qspi_pdata = {
+ .ext_decoder = 0,
+ .fifo_depth = 128,
+};
+
+static void add_cadence_qspi_device(int id, resource_size_t ctrl,
+ resource_size_t data, void *pdata)
+{
+ struct device_d *dev;
+ struct resource *res;
+
+ res = xzalloc(sizeof(struct resource) * 2);
+ res[0].start = ctrl;
+ res[0].end = ctrl + 0x100 - 1;
+ res[0].flags = IORESOURCE_MEM;
+ res[1].start = data;
+ res[1].end = data + 0x100 - 1;
+ res[1].flags = IORESOURCE_MEM;
+
+ dev = add_generic_device_res("cadence_qspi", id, res, 2, pdata);
+
+ dev_dbg(dev, "added resource\n");
+}
+
+void socfpga_cyclone5_qspi_init(void)
+{
+ clks[qspi_clk] = clk_fixed("qspi_clk", 370000000);
+ clkdev_add_physbase(clks[qspi_clk], CYCLONE5_QSPI_CTRL_ADDRESS, NULL);
+ clkdev_add_physbase(clks[qspi_clk], CYCLONE5_QSPI_DATA_ADDRESS, NULL);
+ add_cadence_qspi_device(0, CYCLONE5_QSPI_CTRL_ADDRESS,
+ CYCLONE5_QSPI_DATA_ADDRESS, &qspi_pdata);
+}
+#else
+void socfpga_cyclone5_qspi_init(void)
+{
+ pr_debug("%s: QSPI support not compiled in!\n", __func__);
+
+ return;
+}
+#endif
+
+static struct NS16550_plat uart_pdata = {
+ .clock = 100000000,
+ .shift = 2,
+};
+
+void socfpga_cyclone5_uart_init(void)
+{
+ struct device_d *dev;
+
+ clks[uart] = clk_fixed("uart", 100000000);
+ clkdev_add_physbase(clks[uart], CYCLONE5_UART0_ADDRESS, NULL);
+ clkdev_add_physbase(clks[uart], CYCLONE5_UART1_ADDRESS, NULL);
+ dev = add_ns16550_device(0, 0xffc02000, 1024, IORESOURCE_MEM |
+ IORESOURCE_MEM_8BIT, &uart_pdata);
+
+ dev_dbg(dev, "initialized\n");
+}
+
+void socfpga_cyclone5_timer_init(void)
+{
+ struct device_d *dev;
+
+ clks[timer] = clk_fixed("timer", 200000000);
+ clkdev_add_physbase(clks[timer], CYCLONE5_SMP_TWD_ADDRESS, NULL);
+ dev = add_generic_device("smp_twd", 0, NULL, CYCLONE5_SMP_TWD_ADDRESS, 0x100,
+ IORESOURCE_MEM, NULL);
+
+ dev_dbg(dev, "added smp_twd\n");
+}
+
+static int socfpga_detect_sdram(void)
+{
+ void __iomem *base = (void *)CYCLONE5_SDR_ADDRESS;
+ uint32_t dramaddrw, ctrlwidth, memsize;
+ int colbits, rowbits, bankbits;
+ int width_bytes;
+
+ dramaddrw = readl(base + 0x5000 + 0x2c);
+
+ colbits = dramaddrw & 0x1f;
+ rowbits = (dramaddrw >> 5) & 0x1f;
+ bankbits = (dramaddrw >> 10) & 0x7;
+
+ ctrlwidth = readl(base + 0x5000 + 0x60);
+
+ switch (ctrlwidth & 0x3) {
+ default:
+ case 0:
+ width_bytes = 1;
+ break;
+ case 1:
+ width_bytes = 2;
+ break;
+ case 2:
+ width_bytes = 4;
+ break;
+ }
+
+ memsize = (1 << colbits) * (1 << rowbits) * (1 << bankbits) * width_bytes;
+
+ pr_debug("%s: colbits: %d rowbits: %d bankbits: %d width: %d => memsize: 0x%08x\n",
+ __func__, colbits, rowbits, bankbits, width_bytes, memsize);
+
+ arm_add_mem_device("ram0", 0x0, memsize);
+
+ return 0;
+}
+
+/* Some initialization for the EMAC */
+static void socfpga_init_emac(void)
+{
+ uint32_t rst, val;
+
+ /* No need for this without network support, e.g. xloader build */
+ if (!IS_ENABLED(CONFIG_NET))
+ return;
+
+ /* According to Cyclone V datasheet, 17-60 "EMAC HPS Interface
+ * Initialization", changing PHYSEL should be done with EMAC in reset
+ * via permodrst. */
+
+ /* Everything, except L4WD0/1, is out of reset via socfpga_lowlevel_init() */
+ rst = readl(CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS);
+ rst |= RSTMGR_PERMODRST_EMAC0 | RSTMGR_PERMODRST_EMAC1;
+ writel(rst, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS);
+
+ /* Set emac0/1 PHY interface select to RGMII. We could read phy-mode
+ * from the device tree, if it was desired to support interfaces other
+ * than RGMII. */
+ val = readl(CONFIG_SYSMGR_EMAC_CTRL);
+ val &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB);
+ val &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB);
+ val |= SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
+ val |= SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
+ writel(val, CONFIG_SYSMGR_EMAC_CTRL);
+
+ /* Take emac0 and emac1 out of reset */
+ rst &= ~(RSTMGR_PERMODRST_EMAC0 | RSTMGR_PERMODRST_EMAC1);
+ writel(rst, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS);
+}
+
+static int socfpga_init(void)
+{
+ socfpga_init_emac();
+
+ writel(SYSMGR_SDMMC_CTRL_DRVSEL(3) | SYSMGR_SDMMC_CTRL_SMPLSEL(0),
+ SYSMGR_SDMMCGRP_CTRL_REG);
+
+ nic301_slave_ns();
+
+ socfpga_detect_sdram();
+
+ return 0;
+}
+core_initcall(socfpga_init);
diff --git a/arch/arm/mach-socfpga/init.c b/arch/arm/mach-socfpga/cyclone5-init.c
similarity index 89%
rename from arch/arm/mach-socfpga/init.c
rename to arch/arm/mach-socfpga/cyclone5-init.c
index 0c679e3d2dac..412808b8416f 100644
--- a/arch/arm/mach-socfpga/init.c
+++ b/arch/arm/mach-socfpga/cyclone5-init.c
@@ -2,11 +2,11 @@
#include <common.h>
#include <init.h>
#include <io.h>
-#include <mach/freeze-controller.h>
-#include <mach/system-manager.h>
-#include <mach/clock-manager.h>
-#include <mach/reset-manager.h>
-#include <mach/scan-manager.h>
+#include <mach/cyclone5-freeze-controller.h>
+#include <mach/cyclone5-system-manager.h>
+#include <mach/cyclone5-clock-manager.h>
+#include <mach/cyclone5-reset-manager.h>
+#include <mach/cyclone5-scan-manager.h>
#include <mach/generic.h>
void socfpga_lowlevel_init(struct socfpga_cm_config *cm_config,
diff --git a/arch/arm/mach-socfpga/reset-manager.c b/arch/arm/mach-socfpga/cyclone5-reset-manager.c
similarity index 96%
rename from arch/arm/mach-socfpga/reset-manager.c
rename to arch/arm/mach-socfpga/cyclone5-reset-manager.c
index 04522da4d1ae..4bbe1a8101f1 100644
--- a/arch/arm/mach-socfpga/reset-manager.c
+++ b/arch/arm/mach-socfpga/cyclone5-reset-manager.c
@@ -19,8 +19,8 @@
#include <io.h>
#include <init.h>
#include <restart.h>
-#include <mach/socfpga-regs.h>
-#include <mach/reset-manager.h>
+#include <mach/cyclone5-regs.h>
+#include <mach/cyclone5-reset-manager.h>
/* Disable the watchdog (toggle reset to watchdog) */
void watchdog_disable(void)
diff --git a/arch/arm/mach-socfpga/scan-manager.c b/arch/arm/mach-socfpga/cyclone5-scan-manager.c
similarity index 98%
rename from arch/arm/mach-socfpga/scan-manager.c
rename to arch/arm/mach-socfpga/cyclone5-scan-manager.c
index 57979b90a208..cf076c3885b3 100644
--- a/arch/arm/mach-socfpga/scan-manager.c
+++ b/arch/arm/mach-socfpga/cyclone5-scan-manager.c
@@ -17,8 +17,8 @@
#include <common.h>
#include <io.h>
-#include <mach/freeze-controller.h>
-#include <mach/scan-manager.h>
+#include <mach/cyclone5-freeze-controller.h>
+#include <mach/cyclone5-scan-manager.h>
/*
* @fn scan_mgr_io_scan_chain_engine_is_idle
diff --git a/arch/arm/mach-socfpga/system-manager.c b/arch/arm/mach-socfpga/cyclone5-system-manager.c
similarity index 93%
rename from arch/arm/mach-socfpga/system-manager.c
rename to arch/arm/mach-socfpga/cyclone5-system-manager.c
index 45db921f1a02..7e86692c397e 100644
--- a/arch/arm/mach-socfpga/system-manager.c
+++ b/arch/arm/mach-socfpga/cyclone5-system-manager.c
@@ -17,8 +17,8 @@
#include <common.h>
#include <io.h>
-#include <mach/system-manager.h>
-#include <mach/socfpga-regs.h>
+#include <mach/cyclone5-system-manager.h>
+#include <mach/cyclone5-regs.h>
void socfpga_sysmgr_pinmux_init(unsigned long *sys_mgr_init_table, int num)
{
diff --git a/arch/arm/mach-socfpga/include/mach/clock-manager.h b/arch/arm/mach-socfpga/include/mach/cyclone5-clock-manager.h
similarity index 99%
rename from arch/arm/mach-socfpga/include/mach/clock-manager.h
rename to arch/arm/mach-socfpga/include/mach/cyclone5-clock-manager.h
index 45800de79a7a..797aa5d3cfe8 100644
--- a/arch/arm/mach-socfpga/include/mach/clock-manager.h
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-clock-manager.h
@@ -15,8 +15,8 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef _CLOCK_MANAGER_H_
-#define _CLOCK_MANAGER_H_
+#ifndef _CLOCK_MANAGER_CYCLONE5_H_
+#define _CLOCK_MANAGER_CYCLONE5_H_
struct socfpga_cm_config {
/* main group */
@@ -197,4 +197,4 @@ void socfpga_cm_basic_init(const struct socfpga_cm_config *cfg);
CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
-#endif /* _CLOCK_MANAGER_H_ */
+#endif
diff --git a/arch/arm/mach-socfpga/include/mach/freeze-controller.h b/arch/arm/mach-socfpga/include/mach/cyclone5-freeze-controller.h
similarity index 96%
rename from arch/arm/mach-socfpga/include/mach/freeze-controller.h
rename to arch/arm/mach-socfpga/include/mach/cyclone5-freeze-controller.h
index 4253f5b38f92..93ce5152eda9 100644
--- a/arch/arm/mach-socfpga/include/mach/freeze-controller.h
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-freeze-controller.h
@@ -15,10 +15,10 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef _FREEZE_CONTROLLER_H_
-#define _FREEZE_CONTROLLER_H_
+#ifndef _CYCLONE5_FREEZE_CONTROLLER_H_
+#define _CYCLONE5_FREEZE_CONTROLLER_H_
-#include <mach/socfpga-regs.h>
+#include <mach/cyclone5-regs.h>
#define SYSMGR_FRZCTRL_ADDRESS 0x40
#define SYSMGR_FRZCTRL_VIOCTRL_ADDRESS 0x40
diff --git a/arch/arm/mach-socfpga/include/mach/socfpga-regs.h b/arch/arm/mach-socfpga/include/mach/cyclone5-regs.h
similarity index 100%
rename from arch/arm/mach-socfpga/include/mach/socfpga-regs.h
rename to arch/arm/mach-socfpga/include/mach/cyclone5-regs.h
diff --git a/arch/arm/mach-socfpga/include/mach/reset-manager.h b/arch/arm/mach-socfpga/include/mach/cyclone5-reset-manager.h
similarity index 100%
rename from arch/arm/mach-socfpga/include/mach/reset-manager.h
rename to arch/arm/mach-socfpga/include/mach/cyclone5-reset-manager.h
diff --git a/arch/arm/mach-socfpga/include/mach/scan-manager.h b/arch/arm/mach-socfpga/include/mach/cyclone5-scan-manager.h
similarity index 99%
rename from arch/arm/mach-socfpga/include/mach/scan-manager.h
rename to arch/arm/mach-socfpga/include/mach/cyclone5-scan-manager.h
index 568bedfde13c..df720a7e086c 100644
--- a/arch/arm/mach-socfpga/include/mach/scan-manager.h
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-scan-manager.h
@@ -19,7 +19,7 @@
#define _SCAN_MANAGER_H_
#include <io.h>
-#include <mach/socfpga-regs.h>
+#include <mach/cyclone5-regs.h>
/***********************************************************
* *
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_config.h b/arch/arm/mach-socfpga/include/mach/cyclone5-sdram-config.h
similarity index 98%
rename from arch/arm/mach-socfpga/include/mach/sdram_config.h
rename to arch/arm/mach-socfpga/include/mach/cyclone5-sdram-config.h
index 2af797a920d9..a19a837994e2 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_config.h
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-sdram-config.h
@@ -1,9 +1,9 @@
#ifndef __MACH_SDRAM_CONFIG_H
#define __MACH_SDRAM_CONFIG_H
-#include <mach/sdram.h>
-#include <mach/socfpga-regs.h>
-#include <mach/system-manager.h>
+#include <mach/cyclone5-sdram.h>
+#include <mach/cyclone5-regs.h>
+#include <mach/cyclone5-system-manager.h>
static inline void sdram_write(unsigned register_offset, unsigned val)
{
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/cyclone5-sdram.h
similarity index 100%
rename from arch/arm/mach-socfpga/include/mach/sdram.h
rename to arch/arm/mach-socfpga/include/mach/cyclone5-sdram.h
diff --git a/arch/arm/mach-socfpga/include/mach/sequencer.c b/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c
similarity index 99%
rename from arch/arm/mach-socfpga/include/mach/sequencer.c
rename to arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c
index d2338e640686..e5ecb0f1b8b5 100644
--- a/arch/arm/mach-socfpga/include/mach/sequencer.c
+++ b/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.c
@@ -26,11 +26,9 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "sequencer_defines.h"
-
#include "system.h"
#include "sdram_io.h"
-#include "sequencer.h"
+#include "cyclone5-sequencer.h"
#include "tclrpt.h"
/******************************************************************************
@@ -57,7 +55,7 @@ asm(".global __alt_stack_pointer");
asm("__alt_stack_pointer = " STRINGIFY(STACK_POINTER));
#endif
-#include <mach/sdram.h>
+#include <mach/cyclone5-sdram.h>
#define NEWVERSION_RDDESKEW 1
#define NEWVERSION_WRDESKEW 1
diff --git a/arch/arm/mach-socfpga/include/mach/sequencer.h b/arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.h
similarity index 100%
rename from arch/arm/mach-socfpga/include/mach/sequencer.h
rename to arch/arm/mach-socfpga/include/mach/cyclone5-sequencer.h
diff --git a/arch/arm/mach-socfpga/include/mach/system-manager.h b/arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h
similarity index 100%
rename from arch/arm/mach-socfpga/include/mach/system-manager.h
rename to arch/arm/mach-socfpga/include/mach/cyclone5-system-manager.h
diff --git a/arch/arm/mach-socfpga/include/mach/pll_config.h b/arch/arm/mach-socfpga/include/mach/pll_config.h
index bb491d82f12c..1a7e851eda43 100644
--- a/arch/arm/mach-socfpga/include/mach/pll_config.h
+++ b/arch/arm/mach-socfpga/include/mach/pll_config.h
@@ -1,5 +1,5 @@
-#include <mach/clock-manager.h>
+#include <mach/cyclone5-clock-manager.h>
static struct socfpga_cm_config cm_default_cfg = {
/* main group */
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_io.h b/arch/arm/mach-socfpga/include/mach/sdram_io.h
old mode 100755
new mode 100644
index 62698000f6d8..ef87bdaf63b3
--- a/arch/arm/mach-socfpga/include/mach/sdram_io.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_io.h
@@ -26,7 +26,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include <mach/sdram.h>
+#include <mach/cyclone5-sdram.h>
#define MGR_SELECT_MASK 0xf8000
diff --git a/arch/arm/mach-socfpga/include/mach/sequencer_defines.h b/arch/arm/mach-socfpga/include/mach/sequencer_defines.h
deleted file mode 100644
index 50598441069d..000000000000
--- a/arch/arm/mach-socfpga/include/mach/sequencer_defines.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#define TINIT_CNTR1_VAL 32
-#define TINIT_CNTR2_VAL 32
-#define TINIT_CNTR0_VAL 99
-#define TRESET_CNTR1_VAL 99
-#define TRESET_CNTR2_VAL 10
-#define TRESET_CNTR0_VAL 99
diff --git a/arch/arm/mach-socfpga/include/mach/system.h b/arch/arm/mach-socfpga/include/mach/system.h
old mode 100755
new mode 100644
diff --git a/arch/arm/mach-socfpga/include/mach/tclrpt.h b/arch/arm/mach-socfpga/include/mach/tclrpt.h
old mode 100755
new mode 100644
index 4345b23ba65c..6b332c875412
--- a/arch/arm/mach-socfpga/include/mach/tclrpt.h
+++ b/arch/arm/mach-socfpga/include/mach/tclrpt.h
@@ -28,7 +28,7 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "sequencer.h"
+#include "cyclone5-sequencer.h"
#define TCLRPT_SET(item, value)
diff --git a/arch/arm/mach-socfpga/nic301.c b/arch/arm/mach-socfpga/nic301.c
index 206dd48ff911..7069c6e5b9ae 100644
--- a/arch/arm/mach-socfpga/nic301.c
+++ b/arch/arm/mach-socfpga/nic301.c
@@ -18,7 +18,7 @@
#include <common.h>
#include <io.h>
#include <mach/nic301.h>
-#include <mach/socfpga-regs.h>
+#include <mach/cyclone5-regs.h>
/*
* Convert all slave from secure to non secure
diff --git a/arch/arm/mach-socfpga/xload.c b/arch/arm/mach-socfpga/xload.c
index d24944bbb85e..5d47bb9d3ea2 100644
--- a/arch/arm/mach-socfpga/xload.c
+++ b/arch/arm/mach-socfpga/xload.c
@@ -17,8 +17,8 @@
#include <linux/clk.h>
#include <mach/generic.h>
-#include <mach/system-manager.h>
-#include <mach/socfpga-regs.h>
+#include <mach/cyclone5-system-manager.h>
+#include <mach/cyclone5-regs.h>
static struct socfpga_barebox_part default_parts[] = {
{
diff --git a/drivers/firmware/socfpga.c b/drivers/firmware/socfpga.c
index a0cd2011cbce..c1eae98acc91 100644
--- a/drivers/firmware/socfpga.c
+++ b/drivers/firmware/socfpga.c
@@ -34,10 +34,10 @@
#include <fcntl.h>
#include <init.h>
#include <io.h>
-#include <mach/system-manager.h>
-#include <mach/reset-manager.h>
-#include <mach/socfpga-regs.h>
-#include <mach/sdram.h>
+#include <mach/cyclone5-system-manager.h>
+#include <mach/cyclone5-reset-manager.h>
+#include <mach/cyclone5-regs.h>
+#include <mach/cyclone5-sdram.h>
#define FPGAMGRREGS_STAT 0x0
#define FPGAMGRREGS_CTRL 0x4
diff --git a/scripts/socfpga_import_preloader b/scripts/socfpga_import_preloader
index b08262cb6c83..63ff30ec2a21 100755
--- a/scripts/socfpga_import_preloader
+++ b/scripts/socfpga_import_preloader
@@ -46,7 +46,7 @@ copy_source() {
echo " Fixing include pathes..."
# Fix include pathes
- sed -i 's/#include <iocsr_config_cyclone5.h>/#include <mach\/scan-manager.h>/g' $tgt
+ sed -i 's/#include <iocsr_config_cyclone5.h>/#include <mach\/cyclone5-scan-manager.h>/g' $tgt
sed -i 's/#include <pinmux_config.h>/#include <common.h>/g' $tgt
sed -i 's/#include "sequencer_auto.h"//g' $tgt
sed -i 's/#include "sequencer_defines.h"//g' $tgt
--
2.11.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/7] clk: socfpga: move driver to subdirectory
2017-04-03 10:55 [PATCH 0/7] SoCFPGA: add support for Arria10 Steffen Trumtrar
2017-04-03 10:55 ` [PATCH 1/7] ARM: socfpga: rename socfpga->cyclone5 Steffen Trumtrar
@ 2017-04-03 10:55 ` Steffen Trumtrar
2017-04-03 10:55 ` [PATCH 3/7] net: designware: add dwmac-3.72a compatible Steffen Trumtrar
` (5 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Steffen Trumtrar @ 2017-04-03 10:55 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
drivers/clk/Makefile | 2 +-
drivers/clk/socfpga/Makefile | 1 +
drivers/clk/{socfpga.c => socfpga/clk.c} | 0
3 files changed, 2 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/socfpga/Makefile
rename drivers/clk/{socfpga.c => socfpga/clk.c} (100%)
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5811d28b88ce..2a8c058d84e9 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -8,6 +8,6 @@ obj-$(CONFIG_ARCH_MVEBU) += mvebu/
obj-$(CONFIG_ARCH_MXS) += mxs/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
-obj-$(CONFIG_CLK_SOCFPGA) += socfpga.o
+obj-$(CONFIG_CLK_SOCFPGA) += socfpga/
obj-$(CONFIG_MACH_MIPS_ATH79) += clk-ar933x.o
obj-$(CONFIG_ARCH_IMX) += imx/
diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
new file mode 100644
index 000000000000..fc216adb744e
--- /dev/null
+++ b/drivers/clk/socfpga/Makefile
@@ -0,0 +1 @@
+obj-y += clk.o
diff --git a/drivers/clk/socfpga.c b/drivers/clk/socfpga/clk.c
similarity index 100%
rename from drivers/clk/socfpga.c
rename to drivers/clk/socfpga/clk.c
--
2.11.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/7] net: designware: add dwmac-3.72a compatible
2017-04-03 10:55 [PATCH 0/7] SoCFPGA: add support for Arria10 Steffen Trumtrar
2017-04-03 10:55 ` [PATCH 1/7] ARM: socfpga: rename socfpga->cyclone5 Steffen Trumtrar
2017-04-03 10:55 ` [PATCH 2/7] clk: socfpga: move driver to subdirectory Steffen Trumtrar
@ 2017-04-03 10:55 ` Steffen Trumtrar
2017-04-03 10:55 ` [PATCH 4/7] ARM: socfpga: add arria10 support Steffen Trumtrar
` (4 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Steffen Trumtrar @ 2017-04-03 10:55 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
drivers/net/designware.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index bd20a8793ae2..1d3a68384edb 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -520,6 +520,9 @@ static __maybe_unused struct of_device_id dwc_ether_compatible[] = {
.compatible = "snps,dwmac-3.70a",
.data = &dwmac_370a_drvdata,
}, {
+ .compatible = "snps,dwmac-3.72a",
+ .data = &dwmac_370a_drvdata,
+ }, {
/* sentinel */
}
};
--
2.11.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 4/7] ARM: socfpga: add arria10 support
2017-04-03 10:55 [PATCH 0/7] SoCFPGA: add support for Arria10 Steffen Trumtrar
` (2 preceding siblings ...)
2017-04-03 10:55 ` [PATCH 3/7] net: designware: add dwmac-3.72a compatible Steffen Trumtrar
@ 2017-04-03 10:55 ` Steffen Trumtrar
2017-04-04 18:58 ` Trent Piepho
2017-04-03 10:55 ` [PATCH 5/7] clk: socfpga: add arria10 clk drivers Steffen Trumtrar
` (3 subsequent siblings)
7 siblings, 1 reply; 12+ messages in thread
From: Steffen Trumtrar @ 2017-04-03 10:55 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/Kconfig | 6 +-
arch/arm/mach-socfpga/Kconfig | 18 +
arch/arm/mach-socfpga/Makefile | 10 +-
arch/arm/mach-socfpga/arria10-bootsource.c | 53 ++
arch/arm/mach-socfpga/arria10-clock-manager.c | 807 +++++++++++++++++++++
arch/arm/mach-socfpga/arria10-generic.c | 85 +++
arch/arm/mach-socfpga/arria10-init.c | 275 +++++++
arch/arm/mach-socfpga/arria10-reset-manager.c | 422 +++++++++++
arch/arm/mach-socfpga/arria10-sdram.c | 557 ++++++++++++++
arch/arm/mach-socfpga/cyclone5-bootsource.c | 45 +-
arch/arm/mach-socfpga/generic.c | 104 ---
.../include/mach/arria10-clock-manager.h | 249 +++++++
.../arm/mach-socfpga/include/mach/arria10-pinmux.h | 128 ++++
arch/arm/mach-socfpga/include/mach/arria10-regs.h | 114 +++
.../include/mach/arria10-reset-manager.h | 119 +++
arch/arm/mach-socfpga/include/mach/arria10-sdram.h | 353 +++++++++
.../include/mach/arria10-system-manager.h | 97 +++
arch/arm/mach-socfpga/include/mach/generic.h | 35 +
arch/arm/mach-socfpga/xload.c | 92 +--
images/Makefile.socfpga | 8 +
scripts/socfpga_mkimage.c | 1 +
scripts/socfpga_xml_to_config.sh | 86 +++
22 files changed, 3465 insertions(+), 199 deletions(-)
create mode 100644 arch/arm/mach-socfpga/arria10-bootsource.c
create mode 100644 arch/arm/mach-socfpga/arria10-clock-manager.c
create mode 100644 arch/arm/mach-socfpga/arria10-generic.c
create mode 100644 arch/arm/mach-socfpga/arria10-init.c
create mode 100644 arch/arm/mach-socfpga/arria10-reset-manager.c
create mode 100644 arch/arm/mach-socfpga/arria10-sdram.c
delete mode 100644 arch/arm/mach-socfpga/generic.c
create mode 100644 arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h
create mode 100644 arch/arm/mach-socfpga/include/mach/arria10-pinmux.h
create mode 100644 arch/arm/mach-socfpga/include/mach/arria10-regs.h
create mode 100644 arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h
create mode 100644 arch/arm/mach-socfpga/include/mach/arria10-sdram.h
create mode 100644 arch/arm/mach-socfpga/include/mach/arria10-system-manager.h
create mode 100755 scripts/socfpga_xml_to_config.sh
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e4663ea26872..61c7d6c275f8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -176,7 +176,7 @@ config ARCH_ROCKCHIP
select ARCH_HAS_L2X0
config ARCH_SOCFPGA
- bool "Altera SOCFPGA cyclone5"
+ bool "Altera SOCFPGA"
select HAS_DEBUG_LL
select ARM_SMP_TWD
select CPU_V7
@@ -184,8 +184,8 @@ config ARCH_SOCFPGA
select CLKDEV_LOOKUP
select GPIOLIB
select HAVE_PBL_MULTI_IMAGES
- select OFDEVICE if !ARCH_SOCFPGA_XLOAD
- select OFTREE if !ARCH_SOCFPGA_XLOAD
+ select OFDEVICE if !(ARCH_SOCFPGA_XLOAD && ARCH_SOCFPGA_CYCLONE5)
+ select OFTREE if !(ARCH_SOCFPGA_XLOAD && ARCH_SOCFPGA_CYCLONE5)
config ARCH_S3C24xx
bool "Samsung S3C2410, S3C2440"
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 04b5416b6452..003574ba8d65 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -12,16 +12,34 @@ config ARCH_TEXT_BASE
hex
default 0x00100000 if MACH_SOCFPGA_CYCLONE5
+comment "Altera SoCFPGA System-on-Chip"
+
+config ARCH_SOCFPGA_CYCLONE5
+ bool
+ select CPU_V7
+
+config ARCH_SOCFPGA_ARRIA10
+ bool
+ select CPU_V7
+
config MACH_SOCFPGA_ALTERA_SOCDK
+ select HAVE_DEFAULT_ENVIRONMENT_NEW
+ select ARCH_SOCFPGA_CYCLONE5
bool "Altera SoCFPGA Development Kit"
config MACH_SOCFPGA_EBV_SOCRATES
+ select HAVE_DEFAULT_ENVIRONMENT_NEW
+ select ARCH_SOCFPGA_CYCLONE5
bool "EBV Socrates"
config MACH_SOCFPGA_TERASIC_DE0_NANO_SOC
+ select HAVE_DEFAULT_ENVIRONMENT_NEW
+ select ARCH_SOCFPGA_CYCLONE5
bool "Terasic DE0-NANO-SoC aka Atlas"
config MACH_SOCFPGA_TERASIC_SOCKIT
+ select HAVE_DEFAULT_ENVIRONMENT_NEW
+ select ARCH_SOCFPGA_CYCLONE5
bool "Terasic SoCKit"
endif
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 30b796dd3b4f..cbb47fa206f2 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -1,4 +1,8 @@
-pbl-y += cyclone5-init.o cyclone5-freeze-controller.o cyclone5-scan-manager.o cyclone5-system-manager.o
-pbl-y += cyclone5-clock-manager.o
-obj-y += cyclone5-generic.o nic301.o cyclone5-bootsource.o cyclone5-reset-manager.o
+pbl-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-init.o cyclone5-freeze-controller.o cyclone5-scan-manager.o cyclone5-system-manager.o
+pbl-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-clock-manager.o
+obj-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-generic.o nic301.o cyclone5-bootsource.o cyclone5-reset-manager.o
+
+pbl-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += arria10-init.o arria10-clock-manager.o arria10-sdram.o arria10-reset-manager.o arria10-bootsource.o
+obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += arria10-bootsource.o arria10-generic.o arria10-reset-manager.o
+
obj-$(CONFIG_ARCH_SOCFPGA_XLOAD) += xload.o
diff --git a/arch/arm/mach-socfpga/arria10-bootsource.c b/arch/arm/mach-socfpga/arria10-bootsource.c
new file mode 100644
index 000000000000..26af64a1a408
--- /dev/null
+++ b/arch/arm/mach-socfpga/arria10-bootsource.c
@@ -0,0 +1,53 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <bootsource.h>
+#include <init.h>
+#include <io.h>
+#include <mach/arria10-system-manager.h>
+
+static int arria10_boot_save_loc(void)
+{
+ enum bootsource src = BOOTSOURCE_UNKNOWN;
+ uint32_t val;
+
+ val = readl(ARRIA10_SYSMGR_BOOTINFO);
+
+ switch ((val & 0x7000) >> 12) {
+ case 0:
+ /* reserved */
+ break;
+ case 1:
+ /* FPGA, currently not decoded */
+ break;
+ case 2:
+ case 3:
+ src = BOOTSOURCE_NAND;
+ break;
+ case 4:
+ case 5:
+ src = BOOTSOURCE_MMC;
+ break;
+ case 6:
+ case 7:
+ src = BOOTSOURCE_SPI;
+ break;
+ }
+
+ bootsource_set(src);
+ bootsource_set_instance(0);
+
+ return 0;
+}
+core_initcall(arria10_boot_save_loc);
diff --git a/arch/arm/mach-socfpga/arria10-clock-manager.c b/arch/arm/mach-socfpga/arria10-clock-manager.c
new file mode 100644
index 000000000000..d0c442ad1bf5
--- /dev/null
+++ b/arch/arm/mach-socfpga/arria10-clock-manager.c
@@ -0,0 +1,807 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/arria10-regs.h>
+#include <mach/arria10-clock-manager.h>
+
+static const struct arria10_clock_manager *arria10_clkmgr_base =
+ (void *)ARRIA10_CLKMGR_ADDR;
+
+static uint32_t eosc1_hz;
+static uint32_t cb_intosc_hz;
+static uint32_t f2s_free_hz;
+#define LOCKED_MASK (ARRIA10_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
+ ARRIA10_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
+
+static inline void arria10_cm_wait_for_lock(uint32_t mask)
+{
+ register uint32_t inter_val;
+
+ do {
+ inter_val = readl(&arria10_clkmgr_base->stat) & mask;
+ } while (inter_val != mask);
+}
+
+/* function to poll in the fsm busy bit */
+static inline void arria10_cm_wait4fsm(void)
+{
+ register uint32_t inter_val;
+
+ do {
+ inter_val = readl(&arria10_clkmgr_base->stat) &
+ ARRIA10_CLKMGR_CLKMGR_STAT_BUSY_SET_MSK;
+ } while (inter_val);
+}
+
+static uint32_t arria10_cm_get_main_vco(void)
+{
+ uint32_t vco1, src_hz, numer, denom, vco;
+ uint32_t clk_src = readl(&arria10_clkmgr_base->main_pll_vco0);
+
+ clk_src = (clk_src >> ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_LSB) &
+ ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_MSK;
+
+ if (clk_src == ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_EOSC) {
+ src_hz = eosc1_hz;
+ } else if (clk_src == ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC) {
+ src_hz = cb_intosc_hz;
+ } else if (clk_src == ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_F2S) {
+ src_hz = f2s_free_hz;
+ } else {
+ pr_err("arria10_cm_get_main_vco invalid clk_src %d\n", clk_src);
+ return 0;
+ }
+
+ vco1 = readl(&arria10_clkmgr_base->main_pll_vco1);
+ numer = vco1 & ARRIA10_CLKMGR_MAINPLL_VCO1_NUMER_MSK;
+ denom = (vco1 >> ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB) &
+ ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_MSK;
+ vco = src_hz;
+ vco /= (1 + denom);
+ vco *= (1 + numer);
+
+ return vco;
+}
+
+static uint32_t arria10_cm_get_peri_vco(void)
+{
+ uint32_t vco1, src_hz, numer, denom, vco;
+ uint32_t clk_src = readl(&arria10_clkmgr_base->per_pll_vco0);
+
+ clk_src = (clk_src >> ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_LSB) &
+ ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MSK;
+
+ if (clk_src == ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_EOSC) {
+ src_hz = eosc1_hz;
+ } else if (clk_src == ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC) {
+ src_hz = cb_intosc_hz;
+ } else if (clk_src == ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_F2S) {
+ src_hz = f2s_free_hz;
+ } else if (clk_src == ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MAIN) {
+ src_hz = arria10_cm_get_main_vco();
+ src_hz /= (readl(&arria10_clkmgr_base->main_pll_cntr15clk) &
+ ARRIA10_CLKMGR_MAINPLL_CNTRCLK_MSK) + 1;
+ } else {
+ pr_err("arria10_cm_get_peri_vco invalid clk_src %d\n", clk_src);
+ return 0;
+ }
+
+ vco1 = readl(&arria10_clkmgr_base->per_pll_vco1);
+ numer = vco1 & ARRIA10_CLKMGR_PERPLL_VCO1_NUMER_MSK;
+ denom = (vco1 >> ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB) &
+ ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_MSK;
+ vco = src_hz;
+ vco /= (1 + denom);
+ vco *= (1 + numer);
+
+ return vco;
+}
+
+unsigned int arria10_cm_get_mmc_controller_clk_hz(void)
+{
+ uint32_t clk_hz = 0;
+ uint32_t clk_input = readl(&arria10_clkmgr_base->per_pll_cntr6clk);
+ clk_input = (clk_input >> ARRIA10_CLKMGR_PERPLL_CNTR6CLK_SRC_LSB) &
+ ARRIA10_CLKMGR_PERPLLGRP_SRC_MSK;
+
+ switch (clk_input) {
+ case ARRIA10_CLKMGR_PERPLLGRP_SRC_MAIN:
+ clk_hz = arria10_cm_get_main_vco();
+ clk_hz /= 1 + (readl(&arria10_clkmgr_base->main_pll_cntr6clk) &
+ ARRIA10_CLKMGR_MAINPLL_CNTRCLK_MSK);
+ break;
+
+ case ARRIA10_CLKMGR_PERPLLGRP_SRC_PERI:
+ clk_hz = arria10_cm_get_peri_vco();
+ clk_hz /= 1 + (readl(&arria10_clkmgr_base->per_pll_cntr6clk) &
+ ARRIA10_CLKMGR_PERPLL_CNTRCLK_MSK);
+ break;
+
+ case ARRIA10_CLKMGR_PERPLLGRP_SRC_OSC1:
+ clk_hz = eosc1_hz;
+ break;
+
+ case ARRIA10_CLKMGR_PERPLLGRP_SRC_INTOSC:
+ clk_hz = cb_intosc_hz;
+ break;
+
+ case ARRIA10_CLKMGR_PERPLLGRP_SRC_FPGA:
+ clk_hz = f2s_free_hz;
+ break;
+ }
+
+ return clk_hz/4;
+}
+
+/* calculate the intended main VCO frequency based on handoff */
+static uint32_t arria10_cm_calc_handoff_main_vco_clk_hz(struct arria10_mainpll_cfg *main_cfg)
+{
+ uint32_t clk_hz;
+
+ /* Check main VCO clock source: eosc, intosc or f2s? */
+ switch (main_cfg->vco0_psrc) {
+ case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_EOSC:
+ clk_hz = eosc1_hz;
+ break;
+ case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC:
+ clk_hz = cb_intosc_hz;
+ break;
+ case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_F2S:
+ clk_hz = f2s_free_hz;
+ break;
+ default:
+ return 0;
+ }
+
+ /* calculate the VCO frequency */
+ clk_hz /= (1 + main_cfg->vco1_denom);
+ clk_hz *= (1 + main_cfg->vco1_numer);
+
+ return clk_hz;
+}
+
+/* calculate the intended periph VCO frequency based on handoff */
+static uint32_t arria10_cm_calc_handoff_periph_vco_clk_hz(struct arria10_mainpll_cfg *main_cfg,
+ struct arria10_perpll_cfg *per_cfg)
+{
+ uint32_t clk_hz;
+
+ /* Check periph VCO clock source: eosc, intosc, f2s or mainpll? */
+ switch (per_cfg->vco0_psrc) {
+ case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_EOSC:
+ clk_hz = eosc1_hz;
+ break;
+ case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC:
+ clk_hz = cb_intosc_hz;
+ break;
+ case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_F2S:
+ clk_hz = f2s_free_hz;
+ break;
+ case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MAIN:
+ clk_hz = arria10_cm_calc_handoff_main_vco_clk_hz(main_cfg);
+ clk_hz /= main_cfg->cntr15clk_cnt;
+ break;
+ default:
+ return 0;
+ }
+
+ /* calculate the VCO frequency */
+ clk_hz /= (1 + per_cfg->vco1_denom);
+ clk_hz *= (1 + per_cfg->vco1_numer);
+
+ return clk_hz;
+}
+
+/* calculate the intended MPU clock frequency based on handoff */
+static uint32_t arria10_cm_calc_handoff_mpu_clk_hz(struct arria10_mainpll_cfg *main_cfg,
+ struct arria10_perpll_cfg *per_cfg)
+{
+ uint32_t clk_hz;
+
+ /* Check MPU clock source: main, periph, osc1, intosc or f2s? */
+ switch (main_cfg->mpuclk_src) {
+ case ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN:
+ clk_hz = arria10_cm_calc_handoff_main_vco_clk_hz(main_cfg);
+ clk_hz /= ((main_cfg->mpuclk & ARRIA10_CLKMGR_MAINPLL_MPUCLK_CNT_MSK)
+ + 1);
+ break;
+ case ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI:
+ clk_hz = arria10_cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);
+ clk_hz /= (((main_cfg->mpuclk >>
+ ARRIA10_CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) &
+ ARRIA10_CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1);
+ break;
+ case ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_OSC1:
+ clk_hz = eosc1_hz;
+ break;
+ case ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC:
+ clk_hz = cb_intosc_hz;
+ break;
+ case ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_FPGA:
+ clk_hz = f2s_free_hz;
+ break;
+ default:
+ return 0;
+ }
+
+ clk_hz /= (main_cfg->mpuclk_cnt + 1);
+
+ return clk_hz;
+}
+
+/* calculate the intended NOC clock frequency based on handoff */
+static uint32_t arria10_cm_calc_handoff_noc_clk_hz(struct arria10_mainpll_cfg *main_cfg,
+ struct arria10_perpll_cfg *per_cfg)
+{
+ uint32_t clk_hz;
+
+ /* Check MPU clock source: main, periph, osc1, intosc or f2s? */
+ switch (main_cfg->nocclk_src) {
+ case ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN:
+ clk_hz = arria10_cm_calc_handoff_main_vco_clk_hz(main_cfg);
+ clk_hz /= ((main_cfg->nocclk & ARRIA10_CLKMGR_MAINPLL_NOCCLK_CNT_MSK)
+ + 1);
+ break;
+ case ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI:
+ clk_hz = arria10_cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);
+ clk_hz /= (((main_cfg->nocclk >>
+ ARRIA10_CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) &
+ ARRIA10_CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1);
+ break;
+ case ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_OSC1:
+ clk_hz = eosc1_hz;
+ break;
+ case ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC:
+ clk_hz = cb_intosc_hz;
+ break;
+ case ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_FPGA:
+ clk_hz = f2s_free_hz;
+ break;
+ default:
+ return 0;
+ }
+
+ clk_hz /= (main_cfg->nocclk_cnt + 1);
+
+ return clk_hz;
+}
+
+/* return 1 if PLL ramp is required */
+static int arria10_cm_is_pll_ramp_required(int main0periph1,
+ struct arria10_mainpll_cfg *main_cfg,
+ struct arria10_perpll_cfg *per_cfg)
+{
+
+ /* Check for main PLL */
+ if (main0periph1 == 0) {
+ /*
+ * PLL ramp is not required if both MPU clock and NOC clock are
+ * not sourced from main PLL
+ */
+ if (main_cfg->mpuclk_src != ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
+ main_cfg->nocclk_src != ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN)
+ return 0;
+
+ /*
+ * PLL ramp is required if MPU clock is sourced from main PLL
+ * and MPU clock is over 900MHz (as advised by HW team)
+ */
+ if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
+ (arria10_cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
+ ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
+ return 1;
+
+ /*
+ * PLL ramp is required if NOC clock is sourced from main PLL
+ * and NOC clock is over 300MHz (as advised by HW team)
+ */
+ if (main_cfg->nocclk_src == ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN &&
+ (arria10_cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
+ ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
+ return 1;
+
+ } else if (main0periph1 == 1) {
+ /*
+ * PLL ramp is not required if both MPU clock and NOC clock are
+ * not sourced from periph PLL
+ */
+ if (main_cfg->mpuclk_src != ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
+ main_cfg->nocclk_src != ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI)
+ return 0;
+
+ /*
+ * PLL ramp is required if MPU clock are source from periph PLL
+ * and MPU clock is over 900MHz (as advised by HW team)
+ */
+ if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
+ (arria10_cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
+ ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
+ return 1;
+
+ /*
+ * PLL ramp is required if NOC clock are source from periph PLL
+ * and NOC clock is over 300MHz (as advised by HW team)
+ */
+ if (main_cfg->nocclk_src == ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI &&
+ (arria10_cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
+ ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
+ return 1;
+ }
+
+ return 0;
+}
+
+/*
+ * Calculate the new PLL numerator which is based on existing DTS hand off and
+ * intended safe frequency (safe_hz). Note that PLL ramp is only modifying the
+ * numerator while maintaining denominator as denominator will influence the
+ * jitter condition. Please refer A10 HPS TRM for the jitter guide. Note final
+ * value for numerator is minus with 1 to cater our register value
+ * representation.
+ */
+static uint32_t arria10_cm_calc_safe_pll_numer(int main0periph1,
+ struct arria10_mainpll_cfg *main_cfg,
+ struct arria10_perpll_cfg *per_cfg,
+ uint32_t safe_hz)
+{
+ uint32_t clk_hz = 0;
+
+ /* Check for main PLL */
+ if (main0periph1 == 0) {
+ /* Check main VCO clock source: eosc, intosc or f2s? */
+ switch (main_cfg->vco0_psrc) {
+ case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_EOSC:
+ clk_hz = eosc1_hz;
+ break;
+ case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC:
+ clk_hz = cb_intosc_hz;
+ break;
+ case ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_F2S:
+ clk_hz = f2s_free_hz;
+ break;
+ default:
+ return 0;
+ }
+
+ /* Applicable if MPU clock is from main PLL */
+ if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) {
+ /* calculate the safe numer value */
+ clk_hz = (safe_hz / clk_hz) *
+ (main_cfg->mpuclk_cnt + 1) *
+ ((main_cfg->mpuclk &
+ ARRIA10_CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1) *
+ (1 + main_cfg->vco1_denom) - 1;
+ }
+ /* Reach here if MPU clk not from main PLL but NOC clk is */
+ else if (main_cfg->nocclk_src ==
+ ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) {
+ /* calculate the safe numer value */
+ clk_hz = (safe_hz / clk_hz) *
+ (main_cfg->nocclk_cnt + 1) *
+ ((main_cfg->nocclk &
+ ARRIA10_CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1) *
+ (1 + main_cfg->vco1_denom) - 1;
+ } else {
+ clk_hz = 0;
+ }
+
+ } else if (main0periph1 == 1) {
+ /* Check periph VCO clock source: eosc, intosc, f2s, mainpll */
+ switch (per_cfg->vco0_psrc) {
+ case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_EOSC:
+ clk_hz = eosc1_hz;
+ break;
+ case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC:
+ clk_hz = cb_intosc_hz;
+ break;
+ case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_F2S:
+ clk_hz = f2s_free_hz;
+ break;
+ case ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MAIN:
+ clk_hz = arria10_cm_calc_handoff_main_vco_clk_hz(
+ main_cfg);
+ clk_hz /= main_cfg->cntr15clk_cnt;
+ break;
+ default:
+ return 0;
+ }
+ /* Applicable if MPU clock is from periph PLL */
+ if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI) {
+ /* calculate the safe numer value */
+ clk_hz = (safe_hz / clk_hz) *
+ (main_cfg->mpuclk_cnt + 1) *
+ (((main_cfg->mpuclk >>
+ ARRIA10_CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) &
+ ARRIA10_CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1) *
+ (1 + per_cfg->vco1_denom) - 1;
+ }
+ /* Reach here if MPU clk not from periph PLL but NOC clk is */
+ else if (main_cfg->nocclk_src ==
+ ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI) {
+ /* calculate the safe numer value */
+ clk_hz = (safe_hz / clk_hz) *
+ (main_cfg->nocclk_cnt + 1) *
+ (((main_cfg->nocclk >>
+ ARRIA10_CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) &
+ ARRIA10_CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1) *
+ (1 + per_cfg->vco1_denom) - 1;
+ } else {
+ clk_hz = 0;
+ }
+ }
+
+ return clk_hz;
+}
+
+/* ramping the main PLL to final value */
+static void arria10_cm_pll_ramp_main(struct arria10_mainpll_cfg *main_cfg,
+ struct arria10_perpll_cfg *per_cfg,
+ uint32_t pll_ramp_main_hz)
+{
+ uint32_t clk_hz = 0;
+ uint32_t clk_incr_hz = 0;
+ uint32_t clk_final_hz = 0;
+
+ /* find out the increment value */
+ if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) {
+ clk_incr_hz = ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ;
+ clk_final_hz = arria10_cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg);
+ } else if (main_cfg->nocclk_src == ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) {
+ clk_incr_hz = ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ;
+ clk_final_hz = arria10_cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg);
+ }
+
+ /* execute the ramping here */
+ for (clk_hz = pll_ramp_main_hz + clk_incr_hz;
+ clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
+ writel((main_cfg->vco1_denom << ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
+ arria10_cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
+ &arria10_clkmgr_base->main_pll_vco1);
+ udelay(1000);
+ arria10_cm_wait_for_lock(LOCKED_MASK);
+ }
+
+ writel((main_cfg->vco1_denom << ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
+ main_cfg->vco1_numer, &arria10_clkmgr_base->main_pll_vco1);
+
+ udelay(1000);
+ arria10_cm_wait_for_lock(LOCKED_MASK);
+}
+
+/* ramping the periph PLL to final value */
+static void arria10_cm_pll_ramp_periph(struct arria10_mainpll_cfg *main_cfg,
+ struct arria10_perpll_cfg *per_cfg,
+ uint32_t pll_ramp_periph_hz)
+{
+ uint32_t clk_hz = 0;
+ uint32_t clk_incr_hz = 0;
+ uint32_t clk_final_hz = 0;
+
+ /* find out the increment value */
+ if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI) {
+ clk_incr_hz = ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ;
+ clk_final_hz = arria10_cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg);
+ } else if (main_cfg->nocclk_src == ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI) {
+ clk_incr_hz = ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ;
+ clk_final_hz = arria10_cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg);
+ }
+
+ /* execute the ramping here */
+ for (clk_hz = pll_ramp_periph_hz + clk_incr_hz;
+ clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
+ writel((per_cfg->vco1_denom << ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+ arria10_cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz),
+ &arria10_clkmgr_base->per_pll_vco1);
+ udelay(1000);
+ arria10_cm_wait_for_lock(LOCKED_MASK);
+ }
+
+ writel((per_cfg->vco1_denom << ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+ per_cfg->vco1_numer, &arria10_clkmgr_base->per_pll_vco1);
+ udelay(1000);
+ arria10_cm_wait_for_lock(LOCKED_MASK);
+}
+
+/*
+ * Setup clocks while making no assumptions of the
+ * previous state of the clocks.
+ *
+ * - Start by being paranoid and gate all sw managed clocks
+ * - Put all plls in bypass
+ * - Put all plls VCO registers back to reset value (bgpwr dwn).
+ * - Put peripheral and main pll src to reset value to avoid glitch.
+ * - Delay 5 us.
+ * - Deassert bg pwr dn and set numerator and denominator
+ * - Start 7 us timer.
+ * - set internal dividers
+ * - Wait for 7 us timer.
+ * - Enable plls
+ * - Set external dividers while plls are locking
+ * - Wait for pll lock
+ * - Assert/deassert outreset all.
+ * - Take all pll's out of bypass
+ * - Clear safe mode
+ * - set source main and peripheral clocks
+ * - Ungate clocks
+ */
+static int arria10_cm_full_cfg(struct arria10_mainpll_cfg *main_cfg,
+ struct arria10_perpll_cfg *per_cfg)
+{
+ uint32_t pll_ramp_main_hz = 0;
+ uint32_t pll_ramp_periph_hz = 0;
+
+ /* gate off all mainpll clock excpet HW managed clock */
+ writel(ARRIA10_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
+ ARRIA10_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
+ &arria10_clkmgr_base->main_pll_enr);
+
+ /* now we can gate off the rest of the peripheral clocks */
+ writel(0, &arria10_clkmgr_base->per_pll_en);
+
+ /* Put all plls in external bypass */
+ writel(ARRIA10_CLKMGR_MAINPLL_BYPASS_RESET,
+ &arria10_clkmgr_base->main_pll_bypasss);
+ writel(ARRIA10_CLKMGR_PERPLL_BYPASS_RESET,
+ &arria10_clkmgr_base->per_pll_bypasss);
+
+ /*
+ * Put all plls VCO registers back to reset value.
+ * Some code might have messed with them. At same time set the
+ * desired clock source
+ */
+ writel(ARRIA10_CLKMGR_MAINPLL_VCO0_RESET |
+ ARRIA10_CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK |
+ (main_cfg->vco0_psrc << ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_LSB),
+ &arria10_clkmgr_base->main_pll_vco0);
+
+ writel(ARRIA10_CLKMGR_PERPLL_VCO0_RESET |
+ ARRIA10_CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK |
+ (per_cfg->vco0_psrc << ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_LSB),
+ &arria10_clkmgr_base->per_pll_vco0);
+
+ writel(ARRIA10_CLKMGR_MAINPLL_VCO1_RESET,
+ &arria10_clkmgr_base->main_pll_vco1);
+ writel(ARRIA10_CLKMGR_PERPLL_VCO1_RESET,
+ &arria10_clkmgr_base->per_pll_vco1);
+
+ /* clear the interrupt register status register */
+ writel(ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
+ ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK |
+ ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK |
+ ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
+ ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
+ ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK |
+ ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK |
+ ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK,
+ &arria10_clkmgr_base->intr);
+
+ /* Program VCO “Numerator” and “Denominator” for main PLL */
+ if (arria10_cm_is_pll_ramp_required(0, main_cfg, per_cfg)) {
+ /* set main PLL to safe starting threshold frequency */
+ if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN)
+ pll_ramp_main_hz = ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ;
+ else if (main_cfg->nocclk_src == ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN)
+ pll_ramp_main_hz = ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
+
+ writel((main_cfg->vco1_denom << ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
+ arria10_cm_calc_safe_pll_numer(0, main_cfg, per_cfg,
+ pll_ramp_main_hz),
+ &arria10_clkmgr_base->main_pll_vco1);
+ } else {
+ writel((main_cfg->vco1_denom << ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
+ main_cfg->vco1_numer,
+ &arria10_clkmgr_base->main_pll_vco1);
+ }
+
+ /* Program VCO “Numerator” and “Denominator” for periph PLL */
+ if (arria10_cm_is_pll_ramp_required(1, main_cfg, per_cfg)) {
+ /* set periph PLL to safe starting threshold frequency */
+ if (main_cfg->mpuclk_src == ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI)
+ pll_ramp_periph_hz = ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ;
+ else if (main_cfg->nocclk_src == ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI)
+ pll_ramp_periph_hz = ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
+
+ writel((per_cfg->vco1_denom << ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+ arria10_cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
+ pll_ramp_periph_hz),
+ &arria10_clkmgr_base->per_pll_vco1);
+ } else {
+ writel((per_cfg->vco1_denom << ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+ per_cfg->vco1_numer, &arria10_clkmgr_base->per_pll_vco1);
+ }
+
+ /* Wait for at least 5 us */
+ udelay(5);
+
+ /* Now deassert BGPWRDN and PWRDN */
+ clrbits_le32(&arria10_clkmgr_base->main_pll_vco0,
+ ARRIA10_CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK |
+ ARRIA10_CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK);
+ clrbits_le32(&arria10_clkmgr_base->per_pll_vco0,
+ ARRIA10_CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK |
+ ARRIA10_CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
+
+ /* Wait for at least 7 us */
+ udelay(7);
+
+ /* enable the VCO and disable the external regulator to PLL */
+ writel((readl(&arria10_clkmgr_base->main_pll_vco0) &
+ ~ARRIA10_CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) |
+ ARRIA10_CLKMGR_MAINPLL_VCO0_EN_SET_MSK,
+ &arria10_clkmgr_base->main_pll_vco0);
+ writel((readl(&arria10_clkmgr_base->per_pll_vco0) &
+ ~ARRIA10_CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) |
+ ARRIA10_CLKMGR_PERPLL_VCO0_EN_SET_MSK,
+ &arria10_clkmgr_base->per_pll_vco0);
+
+ /* setup all the main PLL counter and clock source */
+ writel(main_cfg->nocclk,
+ ARRIA10_CLKMGR_ADDR + ARRIA10_CLKMGR_MAINPLL_NOC_CLK_OFFSET);
+ writel(main_cfg->mpuclk,
+ ARRIA10_CLKMGR_ADDR + ARRIA10_CLKMGR_ALTERAGRP_MPU_CLK_OFFSET);
+
+ /* main_emaca_clk divider */
+ writel(main_cfg->cntr2clk_cnt, &arria10_clkmgr_base->main_pll_cntr2clk);
+ /* main_emacb_clk divider */
+ writel(main_cfg->cntr3clk_cnt, &arria10_clkmgr_base->main_pll_cntr3clk);
+ /* main_emac_ptp_clk divider */
+ writel(main_cfg->cntr4clk_cnt, &arria10_clkmgr_base->main_pll_cntr4clk);
+ /* main_gpio_db_clk divider */
+ writel(main_cfg->cntr5clk_cnt, &arria10_clkmgr_base->main_pll_cntr5clk);
+ /* main_sdmmc_clk divider */
+ writel(main_cfg->cntr6clk_cnt, &arria10_clkmgr_base->main_pll_cntr6clk);
+ /* main_s2f_user0_clk divider */
+ writel(main_cfg->cntr7clk_cnt |
+ (main_cfg->cntr7clk_src << ARRIA10_CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB),
+ &arria10_clkmgr_base->main_pll_cntr7clk);
+ /* main_s2f_user1_clk divider */
+ writel(main_cfg->cntr8clk_cnt, &arria10_clkmgr_base->main_pll_cntr8clk);
+ /* main_hmc_pll_clk divider */
+ writel(main_cfg->cntr9clk_cnt |
+ (main_cfg->cntr9clk_src << ARRIA10_CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB),
+ &arria10_clkmgr_base->main_pll_cntr9clk);
+ /* main_periph_ref_clk divider */
+ writel(main_cfg->cntr15clk_cnt, &arria10_clkmgr_base->main_pll_cntr15clk);
+
+ /* setup all the peripheral PLL counter and clock source */
+ /* peri_emaca_clk divider */
+ writel(per_cfg->cntr2clk_cnt |
+ (per_cfg->cntr2clk_src << ARRIA10_CLKMGR_PERPLL_CNTR2CLK_SRC_LSB),
+ &arria10_clkmgr_base->per_pll_cntr2clk);
+ /* peri_emacb_clk divider */
+ writel(per_cfg->cntr3clk_cnt |
+ (per_cfg->cntr3clk_src << ARRIA10_CLKMGR_PERPLL_CNTR3CLK_SRC_LSB),
+ &arria10_clkmgr_base->per_pll_cntr3clk);
+ /* peri_emac_ptp_clk divider */
+ writel(per_cfg->cntr4clk_cnt |
+ (per_cfg->cntr4clk_src << ARRIA10_CLKMGR_PERPLL_CNTR4CLK_SRC_LSB),
+ &arria10_clkmgr_base->per_pll_cntr4clk);
+ /* peri_gpio_db_clk divider */
+ writel(per_cfg->cntr5clk_cnt |
+ (per_cfg->cntr5clk_src << ARRIA10_CLKMGR_PERPLL_CNTR5CLK_SRC_LSB),
+ &arria10_clkmgr_base->per_pll_cntr5clk);
+ /* peri_sdmmc_clk divider */
+ writel(per_cfg->cntr6clk_cnt |
+ (per_cfg->cntr6clk_src << ARRIA10_CLKMGR_PERPLL_CNTR6CLK_SRC_LSB),
+ &arria10_clkmgr_base->per_pll_cntr6clk);
+ /* peri_s2f_user0_clk divider */
+ writel(per_cfg->cntr7clk_cnt, &arria10_clkmgr_base->per_pll_cntr7clk);
+ /* peri_s2f_user1_clk divider */
+ writel(per_cfg->cntr8clk_cnt |
+ (per_cfg->cntr8clk_src << ARRIA10_CLKMGR_PERPLL_CNTR8CLK_SRC_LSB),
+ &arria10_clkmgr_base->per_pll_cntr8clk);
+ /* peri_hmc_pll_clk divider */
+ writel(per_cfg->cntr9clk_cnt, &arria10_clkmgr_base->per_pll_cntr9clk);
+
+ /* setup all the external PLL counter */
+ /* mpu wrapper / external divider */
+ writel(main_cfg->mpuclk_cnt |
+ (main_cfg->mpuclk_src << ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_LSB),
+ &arria10_clkmgr_base->main_pll_mpuclk);
+ /* NOC wrapper / external divider */
+ writel(main_cfg->nocclk_cnt |
+ (main_cfg->nocclk_src << ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_LSB),
+ &arria10_clkmgr_base->main_pll_nocclk);
+ /* NOC subclock divider such as l4 */
+ writel(main_cfg->nocdiv_l4mainclk |
+ (main_cfg->nocdiv_l4mpclk << ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) |
+ (main_cfg->nocdiv_l4spclk << ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB) |
+ (main_cfg->nocdiv_csatclk << ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB) |
+ (main_cfg->nocdiv_cstraceclk << ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) |
+ (main_cfg->nocdiv_cspdbgclk << ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB),
+ &arria10_clkmgr_base->main_pll_nocdiv);
+ /* gpio_db external divider */
+ writel(per_cfg->gpiodiv_gpiodbclk, &arria10_clkmgr_base->per_pll_gpiodiv);
+
+ /* setup the EMAC clock mux select */
+ writel((per_cfg->emacctl_emac0sel < ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB) |
+ (per_cfg->emacctl_emac1sel << ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) |
+ (per_cfg->emacctl_emac2sel << ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB),
+ &arria10_clkmgr_base->per_pll_emacctl);
+
+ /* at this stage, check for PLL lock status */
+ arria10_cm_wait_for_lock(LOCKED_MASK);
+
+ /*
+ * after locking, but before taking out of bypass,
+ * assert/deassert outresetall
+ */
+
+ /* assert mainpll outresetall */
+ setbits_le32(&arria10_clkmgr_base->main_pll_vco0,
+ ARRIA10_CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
+ /* assert perpll outresetall */
+ setbits_le32(&arria10_clkmgr_base->per_pll_vco0,
+ ARRIA10_CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
+ /* de-assert mainpll outresetall */
+ clrbits_le32(&arria10_clkmgr_base->main_pll_vco0,
+ ARRIA10_CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
+ /* de-assert perpll outresetall */
+ clrbits_le32(&arria10_clkmgr_base->per_pll_vco0,
+ ARRIA10_CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
+
+ /*
+ * Take all PLLs out of bypass when boot mode is cleared.
+ * release mainpll from bypass
+ */
+ writel(ARRIA10_CLKMGR_MAINPLL_BYPASS_RESET,
+ &arria10_clkmgr_base->main_pll_bypassr);
+ /* wait till Clock Manager is not busy */
+ arria10_cm_wait4fsm();
+
+ /* release perpll from bypass */
+ writel(ARRIA10_CLKMGR_PERPLL_BYPASS_RESET,
+ &arria10_clkmgr_base->per_pll_bypassr);
+ /* wait till Clock Manager is not busy */
+ arria10_cm_wait4fsm();
+
+ /* clear boot mode */
+ clrbits_le32(&arria10_clkmgr_base->ctrl,
+ ARRIA10_CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK);
+ /* wait till Clock Manager is not busy */
+ arria10_cm_wait4fsm();
+
+ /* At here, we need to ramp to final value if needed */
+ if (pll_ramp_main_hz != 0)
+ arria10_cm_pll_ramp_main(main_cfg, per_cfg, pll_ramp_main_hz);
+ if (pll_ramp_periph_hz != 0)
+ arria10_cm_pll_ramp_periph(main_cfg, per_cfg, pll_ramp_periph_hz);
+
+ /* Now ungate non-hw-managed clocks */
+ writel(ARRIA10_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
+ ARRIA10_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
+ &arria10_clkmgr_base->main_pll_ens);
+ writel(ARRIA10_CLKMGR_PERPLL_EN_RESET,
+ &arria10_clkmgr_base->per_pll_ens);
+
+ /*
+ * Clear the loss lock and slip bits as they might set during
+ * clock reconfiguration
+ */
+ writel(ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
+ ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK |
+ ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK |
+ ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
+ ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
+ ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK,
+ &arria10_clkmgr_base->intr);
+
+ return 0;
+}
+
+int arria10_cm_basic_init(struct arria10_mainpll_cfg *mainpll,
+ struct arria10_perpll_cfg *perpll)
+{
+ return arria10_cm_full_cfg(mainpll, perpll);
+}
+
+void arria10_cm_use_intosc(void)
+{
+ setbits_le32(&arria10_clkmgr_base->ctrl,
+ ARRIA10_CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK);
+}
diff --git a/arch/arm/mach-socfpga/arria10-generic.c b/arch/arm/mach-socfpga/arria10-generic.c
new file mode 100644
index 000000000000..b8129eaf23ff
--- /dev/null
+++ b/arch/arm/mach-socfpga/arria10-generic.c
@@ -0,0 +1,85 @@
+#include <common.h>
+#include <io.h>
+#include <init.h>
+#include <restart.h>
+#include <mach/generic.h>
+#include <mach/arria10-reset-manager.h>
+#include <mach/arria10-system-manager.h>
+#include <mach/arria10-regs.h>
+
+/* Some initialization for the EMAC */
+static void arria10_init_emac(void)
+{
+ uint32_t rst, val;
+
+ /* No need for this without network support, e.g. xloader build */
+ if (!IS_ENABLED(CONFIG_NET))
+ return;
+
+ rst = readl(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST);
+ rst |= ARRIA10_RSTMGR_PER0MODRST_EMAC0 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC1 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC2;
+
+ writel(rst, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST);
+ val = readl(ARRIA10_SYSMGR_EMAC0);
+ val &= ~(ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_MASK);
+ val |= ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+ writel(val, ARRIA10_SYSMGR_EMAC0);
+
+ val = readl(ARRIA10_SYSMGR_EMAC1);
+ val &= ~(ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_MASK);
+ val |= ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+ writel(val, ARRIA10_SYSMGR_EMAC1);
+
+ val = readl(ARRIA10_SYSMGR_EMAC2);
+ val &= ~(ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_MASK);
+ val |= ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+ writel(val, ARRIA10_SYSMGR_EMAC2);
+
+ val = readl(ARRIA10_SYSMGR_FPGAINTF_EN_3);
+ val &= ~(ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC0 |
+ ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC0_SW |
+ ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC1 |
+ ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC1_SW |
+ ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC2 |
+ ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC2_SW);
+
+ rst = readl(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST);
+ rst &= ~(ARRIA10_RSTMGR_PER0MODRST_EMAC0 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC1 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC2);
+ writel(rst, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST);
+}
+
+/* Write the reset manager register to cause reset */
+static void __noreturn arria10_restart_soc(struct restart_handler *rst)
+{
+ /* request a warm reset */
+ writel(ARRIA10_RSTMGR_CTL_SWWARMRSTREQ,
+ ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_CTRL);
+ /*
+ * infinite loop here as watchdog will trigger and reset
+ * the processor
+ */
+ hang();
+}
+
+static int arria10_generic_init(void)
+{
+ barebox_set_model("SoCFPGA Arria10");
+
+ pr_debug("Setting SDMMC phase shifts for Arria10\n");
+ writel(ARRIA10_SYSMGR_SDMMC_DRVSEL(3) |
+ ARRIA10_SYSMGR_SDMMC_SMPLSEL(0),
+ ARRIA10_SYSMGR_SDMMC);
+
+ pr_debug("Initialize EMACs\n");
+ arria10_init_emac();
+
+ pr_debug("Register restart handler\n");
+ restart_handler_register_fn(arria10_restart_soc);
+
+ return 0;
+}
+postcore_initcall(arria10_generic_init);
diff --git a/arch/arm/mach-socfpga/arria10-init.c b/arch/arm/mach-socfpga/arria10-init.c
new file mode 100644
index 000000000000..9bf986f398e9
--- /dev/null
+++ b/arch/arm/mach-socfpga/arria10-init.c
@@ -0,0 +1,275 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <debug_ll.h>
+#include <mach/arria10-regs.h>
+#include <mach/arria10-clock-manager.h>
+#include <mach/arria10-pinmux.h>
+#include <mach/arria10-reset-manager.h>
+#include <mach/arria10-system-manager.h>
+#include <mach/generic.h>
+#include <asm/io.h>
+#include <asm/cache-l2x0.h>
+#include <asm/system.h>
+
+#define L310_AUX_CTRL_EARLY_BRESP BIT(30) /* R2P0+ */
+#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26)
+#define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */
+
+static inline void set_auxcr(unsigned int val)
+{
+ asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR"
+ : : "r" (val));
+ isb();
+}
+
+static inline unsigned int get_auxcr(void)
+{
+ unsigned int val;
+
+ asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val));
+ return val;
+}
+
+static void l2c310_disable(void __iomem *base)
+{
+ u32 aux;
+ int ways = 8;
+
+ aux = readl(base + L2X0_AUX_CTRL);
+
+ /*
+ * If full-line-of-zeros is enabled, we must first disable it in the
+ * Cortex-A9 auxiliary control register before disabling the L2 cache.
+ */
+ if (aux & L310_AUX_CTRL_FULL_LINE_ZERO)
+ set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1)));
+
+ /* flush all ways */
+ writel((1 << ways) - 1, base + L2X0_INV_WAY);
+
+ while (readl(base + L2X0_INV_WAY) & ways)
+ ;
+
+ /* sync */
+ writel(0, base + L2X0_CACHE_SYNC);
+
+ /* disable */
+ writel(0, base + L2X0_CTRL);
+ dsb();
+}
+
+static void arria10_initialize_security_policies(void)
+{
+ void __iomem *l2x0_base = (void __iomem *) 0xfffff000;
+
+ /* BootROM leaves the L2X0 in a weird state. Always disable L2X0 for now. */
+ l2c310_disable(l2x0_base);
+
+ /* Put OCRAM in non-secure */
+ writel(0x003f0000, ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION0);
+ writel(0x1, ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN);
+
+ /* Put DDR in non-secure */
+ writel(0xffff0000, ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION0);
+ writel(0x1, ARRIA10_NOC_FW_DDR_L3_DDR_SCR_EN);
+
+ /* Enable priviledge and non priviledge access to L4 peripherals */
+ writel(0xffffffff, ARRIA10_NOC_L4_PRIV_L4_PRIV_L4_PRIV);
+
+ /* Enable secure and non secure transaction to bridges */
+ writel(0xffffffff, ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_LWSOC2FPGA);
+ writel(0xffffffff, ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_SOC2FPGA);
+
+ /* allow non-secure and secure transaction from/to all peripherals */
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_NAND_REG);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_NAND_DATA);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_QSPI_DATA);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_USB0_REG);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_USB1_REG);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SPIM0);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SPIM1);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SPIS0);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SPIS1);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_EMAC0);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_EMAC1);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_EMAC2);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_EMAC3);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_QSPI);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SDMMC);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_GPIO0);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_GPIO1);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_GPIO2);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_I2C0);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_I2C1);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_I2C2);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_I2C3);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_I2C4);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SPTIMER0);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_SPTIMER1);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_UART0);
+ writel(0xffffffff, ARRIA10_NOC_FW_L4_PER_SCR_UART1);
+
+ /* Return error instead of random data */
+ writel(0x1, ARRIA10_NOC_FW_DDR_L3_DDR_SCR_GLOBAL);
+}
+
+static void arria10_mask_ecc_errors(void)
+{
+ writel(0x0007FFFF, ARRIA10_SYSMGR_ADDR + 0x94);
+}
+
+/*
+ * First C function to initialize the critical hardware early
+ */
+void arria10_init(struct arria10_mainpll_cfg *mainpll,
+ struct arria10_perpll_cfg *perpll,
+ struct arria10_pinmux_cfg *pinmux)
+{
+ arria10_cm_use_intosc();
+
+ arria10_initialize_security_policies();
+
+ arria10_mask_ecc_errors();
+
+ /*
+ * Configure the L2 controller to make SDRAM start at 0.
+ * Set address filtering start to 0x0 (Bits [31:20]),
+ * Enable address filtering (Bit[0])
+ */
+ writel(0x00000001, ARRIA10_MPUL2_ADRFLTR_START);
+ writel(0x00000002, ARRIA10_SYSMGR_NOC_ADDR_REMAP_VALUE);
+
+ arria10_reset_peripherals();
+
+ /* timer init */
+ writel(0xffffffff, ARRIA10_OSC1TIMER0_ADDR);
+ writel(0xffffffff, ARRIA10_OSC1TIMER0_ADDR + 0x4);
+ writel(0x00000003, ARRIA10_OSC1TIMER0_ADDR + 0x8);
+
+ /* configuring the clock based on handoff */
+ arria10_cm_basic_init(mainpll, perpll);
+
+ /* dedicated pins */
+ writel(pinmux->dedicated_io_4, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x0c);
+ writel(pinmux->dedicated_io_5, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x10);
+ writel(pinmux->dedicated_io_6, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x14);
+ writel(pinmux->dedicated_io_7, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x18);
+ writel(pinmux->dedicated_io_8, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x1c);
+ writel(pinmux->dedicated_io_9, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x20);
+ writel(pinmux->dedicated_io_10, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x24);
+ writel(pinmux->dedicated_io_11, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x28);
+ writel(pinmux->dedicated_io_12, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x2c);
+ writel(pinmux->dedicated_io_13, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x30);
+ writel(pinmux->dedicated_io_14, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x34);
+ writel(pinmux->dedicated_io_15, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x38);
+ writel(pinmux->dedicated_io_16, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x3c);
+ writel(pinmux->dedicated_io_17, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x40);
+
+ writel(pinmux->cfg_dedicated_io_bank, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x00);
+ writel(pinmux->cfg_dedicated_io_1, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x04);
+ writel(pinmux->cfg_dedicated_io_2, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x08);
+ writel(pinmux->cfg_dedicated_io_3, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x0c);
+ writel(pinmux->cfg_dedicated_io_4, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x10);
+ writel(pinmux->cfg_dedicated_io_5, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x14);
+ writel(pinmux->cfg_dedicated_io_6, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x18);
+ writel(pinmux->cfg_dedicated_io_7, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x1c);
+ writel(pinmux->cfg_dedicated_io_8, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x20);
+ writel(pinmux->cfg_dedicated_io_9, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x24);
+ writel(pinmux->cfg_dedicated_io_10, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x28);
+ writel(pinmux->cfg_dedicated_io_11, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x2c);
+ writel(pinmux->cfg_dedicated_io_12, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x30);
+ writel(pinmux->cfg_dedicated_io_13, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x3c);
+ writel(pinmux->cfg_dedicated_io_14, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x38);
+ writel(pinmux->cfg_dedicated_io_15, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x3c);
+ writel(pinmux->cfg_dedicated_io_16, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x40);
+ writel(pinmux->cfg_dedicated_io_17, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x44);
+
+ /* deassert peripheral resets */
+ arria10_reset_deassert_dedicated_peripherals();
+
+ /* wait for fpga_usermode */
+ while ((readl(0xffd03080) & 0x6) == 0);
+
+ /* shared pins */
+ writel(pinmux->shared_io_q1_1, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x00);
+ writel(pinmux->shared_io_q1_2, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x04);
+ writel(pinmux->shared_io_q1_3, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x08);
+ writel(pinmux->shared_io_q1_4, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x0c);
+ writel(pinmux->shared_io_q1_5, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x10);
+ writel(pinmux->shared_io_q1_6, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x14);
+ writel(pinmux->shared_io_q1_7, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x18);
+ writel(pinmux->shared_io_q1_8, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x1c);
+ writel(pinmux->shared_io_q1_9, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x20);
+ writel(pinmux->shared_io_q1_10, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x24);
+ writel(pinmux->shared_io_q1_11, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x28);
+ writel(pinmux->shared_io_q1_12, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x2c);
+
+ writel(pinmux->shared_io_q2_1, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x30);
+ writel(pinmux->shared_io_q2_2, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x34);
+ writel(pinmux->shared_io_q2_3, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x38);
+ writel(pinmux->shared_io_q2_4, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x3c);
+ writel(pinmux->shared_io_q2_5, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x40);
+ writel(pinmux->shared_io_q2_6, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x44);
+ writel(pinmux->shared_io_q2_7, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x48);
+ writel(pinmux->shared_io_q2_8, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x4c);
+ writel(pinmux->shared_io_q2_9, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x50);
+ writel(pinmux->shared_io_q2_10, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x54);
+ writel(pinmux->shared_io_q2_11, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x58);
+ writel(pinmux->shared_io_q2_12, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x5c);
+
+ writel(pinmux->shared_io_q3_1, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x60);
+ writel(pinmux->shared_io_q3_2, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x64);
+ writel(pinmux->shared_io_q3_3, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x68);
+ writel(pinmux->shared_io_q3_4, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x6c);
+ writel(pinmux->shared_io_q3_5, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x70);
+ writel(pinmux->shared_io_q3_6, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x74);
+ writel(pinmux->shared_io_q3_7, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x78);
+ writel(pinmux->shared_io_q3_8, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x7c);
+ writel(pinmux->shared_io_q3_9, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x80);
+ writel(pinmux->shared_io_q3_10, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x84);
+ writel(pinmux->shared_io_q3_11, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x88);
+ writel(pinmux->shared_io_q3_12, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x8c);
+
+ writel(pinmux->shared_io_q4_1, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x90);
+ writel(pinmux->shared_io_q4_2, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x94);
+ writel(pinmux->shared_io_q4_3, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x98);
+ writel(pinmux->shared_io_q4_4, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0x9c);
+ writel(pinmux->shared_io_q4_5, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0xa0);
+ writel(pinmux->shared_io_q4_6, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0xa4);
+ writel(pinmux->shared_io_q4_7, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0xa8);
+ writel(pinmux->shared_io_q4_8, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0xac);
+ writel(pinmux->shared_io_q4_9, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0xb0);
+ writel(pinmux->shared_io_q4_10, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0xb4);
+ writel(pinmux->shared_io_q4_11, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0xb8);
+ writel(pinmux->shared_io_q4_12, ARRIA10_PINMUX_SHARED_3V_IO_ADDR + 0xbc);
+
+ arria10_reset_deassert_shared_peripherals();
+
+ /* usefpga: select source for signals: hps or fpga */
+ writel(pinmux->rgmii0_usefpga, ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + 0x00);
+ writel(pinmux->rgmii1_usefpga, ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + 0x04);
+ writel(pinmux->rgmii2_usefpga, ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + 0x08);
+ writel(pinmux->i2c0_usefpga, ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + 0x0c);
+ writel(pinmux->i2c1_usefpga, ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + 0x10);
+ writel(pinmux->i2cemac0_usefpga, ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + 0x14);
+ writel(pinmux->i2cemac1_usefpga, ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + 0x18);
+ writel(pinmux->i2cemac2_usefpga, ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + 0x1c);
+ writel(pinmux->nand_usefpga, ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + 0x20);
+ writel(pinmux->qspi_usefpga, ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + 0x24);
+ writel(pinmux->sdmmc_usefpga, ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + 0x28);
+ writel(pinmux->spim0_usefpga, ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + 0x2c);
+ writel(pinmux->spim1_usefpga, ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + 0x30);
+ writel(pinmux->spis0_usefpga, ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + 0x34);
+ writel(pinmux->spis1_usefpga, ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + 0x38);
+ writel(pinmux->uart0_usefpga, ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + 0x3c);
+ writel(pinmux->uart1_usefpga, ARRIA10_PINMUX_FPGA_INTERFACE_ADDR + 0x40);
+
+ arria10_reset_deassert_fpga_peripherals();
+
+ INIT_LL();
+}
diff --git a/arch/arm/mach-socfpga/arria10-reset-manager.c b/arch/arm/mach-socfpga/arria10-reset-manager.c
new file mode 100644
index 000000000000..7a7c224e9989
--- /dev/null
+++ b/arch/arm/mach-socfpga/arria10-reset-manager.c
@@ -0,0 +1,422 @@
+/*
+ * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <io.h>
+#include <mach/arria10-regs.h>
+#include <mach/arria10-reset-manager.h>
+#include <mach/arria10-system-manager.h>
+
+void arria10_reset_peripherals(void)
+{
+ unsigned mask_ecc_ocp = ARRIA10_RSTMGR_PER0MODRST_EMACECC0 |
+ ARRIA10_RSTMGR_PER0MODRST_EMACECC1 |
+ ARRIA10_RSTMGR_PER0MODRST_EMACECC2 |
+ ARRIA10_RSTMGR_PER0MODRST_USBECC0 |
+ ARRIA10_RSTMGR_PER0MODRST_USBECC1 |
+ ARRIA10_RSTMGR_PER0MODRST_NANDECC |
+ ARRIA10_RSTMGR_PER0MODRST_QSPIECC |
+ ARRIA10_RSTMGR_PER0MODRST_SDMMCECC;
+
+ /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
+ writel(0xffffffff, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST);
+ setbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST,
+ ~mask_ecc_ocp);
+
+ /* Finally disable the ECC_OCP */
+ setbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST,
+ mask_ecc_ocp);
+}
+
+void arria10_reset_deassert_dedicated_peripherals(void)
+{
+ uint32_t mask0 = 0;
+ uint32_t mask1 = 0;
+ uint32_t mask = 0;
+
+ mask |= ARRIA10_RSTMGR_PER0MODRST_SDMMCECC;
+ mask |= ARRIA10_RSTMGR_PER0MODRST_QSPIECC;
+ mask |= ARRIA10_RSTMGR_PER0MODRST_NANDECC;
+ mask |= ARRIA10_RSTMGR_PER0MODRST_DMAECC;
+
+ /* enable ECC OCP first */
+ clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask);
+
+ mask = 0;
+ mask |= ARRIA10_RSTMGR_PER0MODRST_SDMMC;
+ mask |= ARRIA10_RSTMGR_PER0MODRST_QSPI;
+ mask |= ARRIA10_RSTMGR_PER0MODRST_NAND;
+ mask |= ARRIA10_RSTMGR_PER0MODRST_DMA;
+
+ clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask);
+
+ mask = ARRIA10_RSTMGR_PER1MODRST_L4SYSTMR0;
+
+ mask |= ARRIA10_RSTMGR_PER1MODRST_UART1;
+ mask |= ARRIA10_RSTMGR_PER1MODRST_UART0;
+
+ clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST, mask);
+
+ mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C3;
+ mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C4;
+ mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C2;
+ mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMACECC1 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC1;
+ mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMACECC2 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC2;
+ mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMACECC0 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC0;
+ mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS0;
+ mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIM0;
+ mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART1;
+ mask1 |= ARRIA10_RSTMGR_PER1MODRST_GPIO2;
+
+ clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST,
+ mask & ECC_MASK);
+ clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST, mask1);
+ clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask0);
+}
+
+static const uint32_t per0fpgamasks[] = {
+ ARRIA10_RSTMGR_PER0MODRST_EMACECC0 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC0,
+ ARRIA10_RSTMGR_PER0MODRST_EMACECC1 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC1,
+ ARRIA10_RSTMGR_PER0MODRST_EMACECC2 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC2,
+ 0, /* i2c0 per1mod */
+ 0, /* i2c1 per1mod */
+ 0, /* i2c0_emac */
+ 0, /* i2c1_emac */
+ 0, /* i2c2_emac */
+ ARRIA10_RSTMGR_PER0MODRST_NANDECC |
+ ARRIA10_RSTMGR_PER0MODRST_NAND,
+ ARRIA10_RSTMGR_PER0MODRST_QSPIECC |
+ ARRIA10_RSTMGR_PER0MODRST_QSPI,
+ ARRIA10_RSTMGR_PER0MODRST_SDMMCECC |
+ ARRIA10_RSTMGR_PER0MODRST_SDMMC,
+ ARRIA10_RSTMGR_PER0MODRST_SPIM0,
+ ARRIA10_RSTMGR_PER0MODRST_SPIM1,
+ ARRIA10_RSTMGR_PER0MODRST_SPIS0,
+ ARRIA10_RSTMGR_PER0MODRST_SPIS1,
+ 0, /* uart0 per1mod */
+ 0, /* uart1 per1mod */
+};
+
+static const uint32_t per1fpgamasks[] = {
+ 0, /* emac0 per0mod */
+ 0, /* emac1 per0mod */
+ 0, /* emac2 per0mod */
+ ARRIA10_RSTMGR_PER1MODRST_I2C0,
+ ARRIA10_RSTMGR_PER1MODRST_I2C1,
+ ARRIA10_RSTMGR_PER1MODRST_I2C2, /* i2c0_emac */
+ ARRIA10_RSTMGR_PER1MODRST_I2C3, /* i2c1_emac */
+ ARRIA10_RSTMGR_PER1MODRST_I2C4, /* i2c2_emac */
+ 0, /* nand per0mod */
+ 0, /* qspi per0mod */
+ 0, /* sdmmc per0mod */
+ 0, /* spim0 per0mod */
+ 0, /* spim1 per0mod */
+ 0, /* spis0 per0mod */
+ 0, /* spis1 per0mod */
+ ARRIA10_RSTMGR_PER1MODRST_UART0,
+ ARRIA10_RSTMGR_PER1MODRST_UART1,
+};
+
+void arria10_reset_deassert_fpga_peripherals(void)
+{
+ uint32_t mask0 = 0;
+ uint32_t mask1 = 0;
+ uint32_t fpga_pinux_addr = ARRIA10_PINMUX_FPGA_INTERFACE_ADDR;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(per1fpgamasks); i++) {
+ if (readl(fpga_pinux_addr)) {
+ mask0 |= per0fpgamasks[i];
+ mask1 |= per1fpgamasks[i];
+ }
+ fpga_pinux_addr += sizeof(uint32_t);
+ }
+
+ clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST,
+ mask0 & ECC_MASK);
+ clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST, mask1);
+ clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask0);
+}
+
+void arria10_reset_deassert_shared_peripherals_q1(uint32_t *mask0,
+ uint32_t *mask1,
+ uint32_t *pinmux_addr)
+{
+ int i;
+
+ for (i = 1; i <= 12; i++, *pinmux_addr += sizeof(uint32_t)) {
+ switch (readl(*pinmux_addr)) {
+ case 15:
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_GPIO0;
+ break;
+ case 14:
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_NANDECC|
+ ARRIA10_RSTMGR_PER0MODRST_NAND;
+ break;
+ case 13:
+ if ((i >= 1) && (i <= 4))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART0;
+ else if ((i >= 5) && (i <= 8))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART1;
+ break;
+ case 12:
+ if ((i >= 5) && (i <= 6))
+ *mask0 |=
+ ARRIA10_RSTMGR_PER0MODRST_QSPIECC |
+ ARRIA10_RSTMGR_PER0MODRST_QSPI;
+ break;
+ case 8:
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_USBECC0 |
+ ARRIA10_RSTMGR_PER0MODRST_USB0;
+ break;
+ case 4:
+ if ((i >= 1) && (i <= 10))
+ *mask0 |=
+ ARRIA10_RSTMGR_PER0MODRST_SDMMCECC |
+ ARRIA10_RSTMGR_PER0MODRST_SDMMC;
+ break;
+ case 3:
+ if ((i == 1) || ((i >= 5) && (i <= 8)))
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIM0;
+ else if ((i == 2) || ((i >= 9) && (i <= 12)))
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIM1;
+ break;
+ case 2:
+ if ((i >= 1) && (i <= 4))
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS0;
+ else if ((i >= 9) && (i <= 12))
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS1;
+ break;
+ case 1:
+ if ((i == 7) || (i == 8))
+ *mask0 |=
+ ARRIA10_RSTMGR_PER0MODRST_EMACECC2 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC2;
+ else if ((i == 9) || (i == 10))
+ *mask0 |=
+ ARRIA10_RSTMGR_PER0MODRST_EMACECC1 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC1;
+ else if ((i == 11) || (1 == 12))
+ *mask0 |=
+ ARRIA10_RSTMGR_PER0MODRST_EMACECC0 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC0;
+ break;
+ case 0:
+ if ((i == 3) || (i == 4))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C1;
+ else if ((i == 5) || (i == 6))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C0;
+ else if ((i == 7) || (i == 8))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C4;
+ else if ((i == 9) || (i == 10))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C3;
+ else if ((i == 11) || (i == 12))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C2;
+ break;
+ }
+ }
+}
+
+void arria10_reset_deassert_shared_peripherals_q2(uint32_t *mask0,
+ uint32_t *mask1,
+ uint32_t *pinmux_addr)
+{
+ int i;
+
+ for (i = 1; i <= 12; i++, *pinmux_addr += sizeof(uint32_t)) {
+ switch (readl(*pinmux_addr)) {
+ case 15:
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_GPIO0;
+ break;
+ case 14:
+ if ((i != 4) && (i != 5))
+ *mask0 |=
+ ARRIA10_RSTMGR_PER0MODRST_NANDECC |
+ ARRIA10_RSTMGR_PER0MODRST_NAND;
+ break;
+ case 13:
+ if ((i >= 9) && (i <= 12))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART0;
+ break;
+ case 8:
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_USBECC1 |
+ ARRIA10_RSTMGR_PER0MODRST_USB1;
+ break;
+ case 4:
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMACECC0 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC0;
+ break;
+ case 3:
+ if ((i >= 8) && (i <= 12))
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIM1;
+ break;
+ case 2:
+ if ((i >= 9) && (i <= 12))
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS0;
+ break;
+ case 0:
+ if ((i == 9) || (i == 10))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C1;
+ else if ((i == 11) || (i == 12))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C0;
+ break;
+ }
+ }
+}
+
+void arria10_reset_deassert_shared_peripherals_q3(uint32_t *mask0,
+ uint32_t *mask1,
+ uint32_t *pinmux_addr)
+{
+ int i;
+
+ for (i = 1; i <= 12; i++, *pinmux_addr += sizeof(uint32_t)) {
+ switch (readl(*pinmux_addr)) {
+ case 15:
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_GPIO1;
+ break;
+ case 14:
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_NANDECC |
+ ARRIA10_RSTMGR_PER0MODRST_NAND;
+ break;
+ case 13:
+ if ((i >= 1) && (i <= 4))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART0;
+ else if ((i >= 5) && (i <= 8))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART1;
+ break;
+ case 8:
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMACECC1 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC1;
+ break;
+ case 3:
+ if ((i >= 1) && (i <= 5))
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIM1;
+ break;
+ case 2:
+ if ((i >= 5) && (i <= 8))
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS1;
+ else if ((i >= 9) && (i <= 12))
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS0;
+ break;
+ case 1:
+ if ((i == 9) || (i == 10))
+ *mask0 |=
+ ARRIA10_RSTMGR_PER0MODRST_EMACECC2 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC2;
+ else if ((i == 11) || (i == 12))
+ *mask0 |=
+ ARRIA10_RSTMGR_PER0MODRST_EMACECC0 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC0;
+ break;
+ case 0:
+ if ((i == 7) || (i == 8))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C1;
+ else if ((i == 3) || (i == 4))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C0;
+ else if ((i == 9) || (i == 10))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C4;
+ else if ((i == 11) || (i == 12))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C2;
+ break;
+ }
+ }
+}
+
+void arria10_reset_deassert_shared_peripherals_q4(uint32_t *mask0, uint32_t *mask1,
+ uint32_t *pinmux_addr)
+{
+ int i;
+
+ for (i = 1; i <= 12; i++, *pinmux_addr += sizeof(uint32_t)) {
+ switch (readl(*pinmux_addr)) {
+ case 15:
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_GPIO1;
+ break;
+ case 14:
+ if (i != 4)
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_NANDECC |
+ ARRIA10_RSTMGR_PER0MODRST_NAND;
+ break;
+ case 13:
+ if ((i >= 3) && (i <= 6))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART1;
+ break;
+ case 12:
+ if ((i == 5) || (i == 6))
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_QSPIECC |
+ ARRIA10_RSTMGR_PER0MODRST_QSPI;
+ break;
+ case 8:
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMACECC2 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC2;
+ break;
+ case 4:
+ if ((i >= 1) && (i <= 6))
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SDMMCECC |
+ ARRIA10_RSTMGR_PER0MODRST_SDMMC;
+ break;
+ case 3:
+ if ((i >= 6) && (i <= 12))
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIM0;
+ break;
+ case 2:
+ if ((i >= 9) && (i <= 12))
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS1;
+ break;
+ case 1:
+ if ((i == 7) || (i == 8))
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMACECC1 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC1;
+ else if ((i == 11) || (i == 12))
+ *mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMACECC0 |
+ ARRIA10_RSTMGR_PER0MODRST_EMAC0;
+ break;
+ case 0:
+ if ((i == 1) || (i == 2))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C1;
+ else if ((i == 7) || (i == 8))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C3;
+ else if ((i == 9) || (i == 10))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C4;
+ else if ((i == 11) || (i == 12))
+ *mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C2;
+ break;
+ }
+ }
+}
+
+void arria10_reset_deassert_shared_peripherals(void)
+{
+ uint32_t mask0 = 0;
+ uint32_t mask1 = 0;
+ uint32_t pinmux_addr = ARRIA10_PINMUX_SHARED_3V_IO_ADDR;
+
+ arria10_reset_deassert_shared_peripherals_q1(&mask0, &mask1,
+ &pinmux_addr);
+ arria10_reset_deassert_shared_peripherals_q2(&mask0, &mask1,
+ &pinmux_addr);
+ arria10_reset_deassert_shared_peripherals_q3(&mask0, &mask1,
+ &pinmux_addr);
+ arria10_reset_deassert_shared_peripherals_q4(&mask0, &mask1,
+ &pinmux_addr);
+ mask1 |= ARRIA10_RSTMGR_PER1MODRST_L4WD1 |
+ ARRIA10_RSTMGR_PER1MODRST_L4SYSTMR1 |
+ ARRIA10_RSTMGR_PER1MODRST_SPTMR0 |
+ ARRIA10_RSTMGR_PER1MODRST_SPTMR1;
+
+ clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST,
+ mask0 & ECC_MASK);
+ clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST, mask1);
+ clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask0);
+}
diff --git a/arch/arm/mach-socfpga/arria10-sdram.c b/arch/arm/mach-socfpga/arria10-sdram.c
new file mode 100644
index 000000000000..a18a0abf14bf
--- /dev/null
+++ b/arch/arm/mach-socfpga/arria10-sdram.c
@@ -0,0 +1,557 @@
+/*
+ * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <io.h>
+#include <debug_ll.h>
+#include <mach/arria10-sdram.h>
+#include <mach/arria10-regs.h>
+#include <mach/arria10-reset-manager.h>
+
+
+/* FAWBANK - Number of Bank of a given device involved in the FAW period. */
+#define ARRIA10_SDR_ACTIVATE_FAWBANK (0x1)
+
+#define ARRIA10_EMIF_RST 31
+#define ARRIA10_OCT_CAL_REQ 30
+#define ARRIA10_OCT_CAL_ACK 31
+
+#define ARRIA10_NIOS_OCT_DONE 7
+#define ARRIA10_NIOS_OCT_ACK 7
+
+/* Engineering sample silicon */
+#define ARRIA10_ES_SILICON_VER 0x00010001
+
+#define DDR_REG_SEQ2CORE 0xFFD0507C
+#define DDR_REG_CORE2SEQ 0xFFD05078
+#define DDR_REG_GPOUT 0xFFD03010
+#define DDR_REG_GPIN 0xFFD03014
+#define DDR_MAX_TRIES 0x00100000
+#define IO48_MMR_DRAMSTS 0xFFCFA0EC
+#define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110
+#define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114
+#define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118
+
+#define SEQ2CORE_MASK 0xF
+#define CORE2SEQ_INT_REQ 0xF
+#define SEQ2CORE_INT_RESP_BIT 3
+
+#define DDR_ECC_DMA_SIZE 1500
+#define DDR_READ_LATENCY_DELAY 40
+
+#define ARRIA_DDR_CONFIG(A, B, C, R) ((A<<24)|(B<<16)|(C<<8)|R)
+/* The followring are the supported configurations */
+uint32_t ddr_config[] = {
+ /* Chip - Row - Bank - Column Style */
+ /* All Types */
+ ARRIA_DDR_CONFIG(0, 3, 10, 12),
+ ARRIA_DDR_CONFIG(0, 3, 10, 13),
+ ARRIA_DDR_CONFIG(0, 3, 10, 14),
+ ARRIA_DDR_CONFIG(0, 3, 10, 15),
+ ARRIA_DDR_CONFIG(0, 3, 10, 16),
+ ARRIA_DDR_CONFIG(0, 3, 10, 17),
+ /* LPDDR x16 */
+ ARRIA_DDR_CONFIG(0, 3, 11, 14),
+ ARRIA_DDR_CONFIG(0, 3, 11, 15),
+ ARRIA_DDR_CONFIG(0, 3, 11, 16),
+ ARRIA_DDR_CONFIG(0, 3, 12, 15),
+ /* DDR4 Only */
+ ARRIA_DDR_CONFIG(0, 4, 10, 14),
+ ARRIA_DDR_CONFIG(0, 4, 10, 15),
+ ARRIA_DDR_CONFIG(0, 4, 10, 16),
+ ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */
+ /* Chip - Bank - Row - Column Style */
+ ARRIA_DDR_CONFIG(1, 3, 10, 12),
+ ARRIA_DDR_CONFIG(1, 3, 10, 13),
+ ARRIA_DDR_CONFIG(1, 3, 10, 14),
+ ARRIA_DDR_CONFIG(1, 3, 10, 15),
+ ARRIA_DDR_CONFIG(1, 3, 10, 16),
+ ARRIA_DDR_CONFIG(1, 3, 10, 17),
+ ARRIA_DDR_CONFIG(1, 3, 11, 14),
+ ARRIA_DDR_CONFIG(1, 3, 11, 15),
+ ARRIA_DDR_CONFIG(1, 3, 11, 16),
+ ARRIA_DDR_CONFIG(1, 3, 12, 15),
+ /* DDR4 Only */
+ ARRIA_DDR_CONFIG(1, 4, 10, 14),
+ ARRIA_DDR_CONFIG(1, 4, 10, 15),
+ ARRIA_DDR_CONFIG(1, 4, 10, 16),
+ ARRIA_DDR_CONFIG(1, 4, 10, 17),
+};
+#define DDR_CONFIG_ELEMENTS (sizeof(ddr_config)/sizeof(uint32_t))
+
+void udelay(unsigned long time)
+{
+ unsigned long i = 1000 * time;
+
+ while (i--)
+ ;
+}
+
+static int match_ddr_conf(uint32_t ddr_conf)
+{
+ int i;
+
+ for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
+ if (ddr_conf == ddr_config[i])
+ return i;
+ }
+ return 0;
+}
+
+/* Check whether SDRAM is successfully Calibrated */
+static int is_sdram_cal_success(void)
+{
+ return readl(ARRIA10_ECC_HMC_OCP_DDRCALSTAT);
+}
+
+static unsigned char ddr_get_bit(uint32_t ereg, unsigned char bit)
+{
+ unsigned int reg = readl(ereg);
+
+ return (reg & (1 << bit)) ? 1 : 0;
+}
+
+static unsigned char ddr_wait_bit(uint32_t ereg, uint32_t bit,
+ uint32_t expected, uint32_t timeout_usec)
+{
+ unsigned int tmr;
+
+ for (tmr = 0; tmr < timeout_usec; tmr += 100) {
+ udelay(100);
+ if (ddr_get_bit(ereg, bit) == expected)
+ return 0;
+ }
+
+ return 1;
+}
+
+static void ddr_set_bit(uint32_t ereg, uint32_t bit)
+{
+ unsigned int tmp = readl(ereg);
+
+ tmp |= (1 << bit);
+ writel(tmp, ereg);
+}
+
+static void ddr_clr_bit(uint32_t ereg, uint32_t bit)
+{
+ unsigned int tmp = readl(ereg);
+
+ tmp &= ~(1 << bit);
+ writel(tmp, ereg);
+}
+
+static void ddr_delay(uint32_t delay)
+{
+ int tmr;
+
+ for (tmr = 0; tmr < delay; tmr++)
+ udelay(1000);
+}
+
+/*
+ * Diagram of OCT Workaround:
+ *
+ * EMIF Core HPS Processor OCT FSM
+ * =================================================================
+ *
+ * seq2core ==============>
+ * [0x?????????] OCT Request [0xFFD0507C]
+ *
+ * core2seq
+ * [0x?????????] <==============
+ * OCT Ready [0xFFD05078]
+ *
+ * [0xFFD03010] ============> Request
+ * OCT Request
+ *
+ * [0xFFD03014] <============ Ready
+ * OCT Ready
+ * Signal definitions:
+ *
+ * seq2core[7] - OCT calibration request (act-high)
+ * core2seq[7] - Signals OCT FSM is ready (active high)
+ * gpout[31] - EMIF Reset override (active low)
+ * gpout[30] - OCT calibration request (act-high)
+ * gpin[31] - OCT calibration ready (act-high)
+ */
+
+static int ddr_calibration_es_workaround(void)
+{
+ ddr_delay(500);
+ /* Step 1 - Initiating Reset Sequence */
+ ddr_clr_bit(DDR_REG_GPOUT, ARRIA10_EMIF_RST); /* Reset EMIF */
+ ddr_delay(10);
+
+ /* Step 2 - Clearing registers to EMIF core */
+ writel(0, DDR_REG_CORE2SEQ); /*Clear the HPS->NIOS COM reg.*/
+
+ /* Step 3 - Clearing registers to OCT core */
+ ddr_clr_bit(DDR_REG_GPOUT, ARRIA10_OCT_CAL_REQ); /* OCT Cal Request */
+ ddr_delay(5);
+
+ /* Step 4 - Taking EMIF out of reset */
+ ddr_set_bit(DDR_REG_GPOUT, ARRIA10_EMIF_RST);
+ ddr_delay(10);
+
+ /* Step 5 - Waiting for OCT circuitry to come out of reset */
+ if (ddr_wait_bit(DDR_REG_GPIN, ARRIA10_OCT_CAL_ACK, 1, 1000000))
+ return -1;
+
+ /* Step 6 - Allowing EMIF to proceed with OCT calibration */
+ ddr_set_bit(DDR_REG_CORE2SEQ, ARRIA10_NIOS_OCT_DONE);
+
+ /* Step 7 - Waiting for EMIF request */
+ if (ddr_wait_bit(DDR_REG_SEQ2CORE, ARRIA10_NIOS_OCT_ACK, 1, 2000000))
+ return -2;
+
+ /* Step 8 - Acknowledging EMIF OCT request */
+ ddr_clr_bit(DDR_REG_CORE2SEQ, ARRIA10_NIOS_OCT_DONE);
+
+ /* Step 9 - Waiting for EMIF response */
+ if (ddr_wait_bit(DDR_REG_SEQ2CORE, ARRIA10_NIOS_OCT_ACK, 0, 2000000))
+ return -3;
+
+ /* Step 10 - Triggering OCT Calibration */
+ ddr_set_bit(DDR_REG_GPOUT, ARRIA10_OCT_CAL_REQ);
+
+ /* Step 11 - Waiting for OCT response */
+ if (ddr_wait_bit(DDR_REG_GPIN, ARRIA10_OCT_CAL_ACK, 0, 1000))
+ return -4;
+
+ /* Step 12 - Clearing OCT Request bit */
+ ddr_clr_bit(DDR_REG_GPOUT, ARRIA10_OCT_CAL_REQ);
+
+ /* Step 13 - Waiting for OCT Engine */
+ if (ddr_wait_bit(DDR_REG_GPIN, ARRIA10_OCT_CAL_ACK, 1, 200000))
+ return -5;
+
+ /* Step 14 - Proceeding with EMIF calibration */
+ ddr_set_bit(DDR_REG_CORE2SEQ, ARRIA10_NIOS_OCT_DONE);
+
+ ddr_delay(100);
+
+ return 0;
+}
+
+static int emif_clear(void)
+{
+ uint32_t s2c;
+ uint32_t i = DDR_MAX_TRIES;
+
+ writel(0, DDR_REG_CORE2SEQ);
+ do {
+ ddr_delay(50);
+ s2c = readl(DDR_REG_SEQ2CORE);
+ } while ((s2c & SEQ2CORE_MASK) && (--i > 0));
+
+ return !i;
+}
+static int emif_reset(void)
+{
+ uint32_t c2s, s2c;
+
+ c2s = readl(DDR_REG_CORE2SEQ);
+ s2c = readl(DDR_REG_SEQ2CORE);
+
+ pr_debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
+ c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
+ readl(IO48_MMR_NIOS2_RESERVE1),
+ readl(IO48_MMR_NIOS2_RESERVE2),
+ readl(IO48_MMR_DRAMSTS));
+
+ if ((s2c & SEQ2CORE_MASK) && emif_clear()) {
+ printf("failed emif_clear()\n");
+ return -1;
+ }
+
+ writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
+
+ if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {
+ printf("emif_reset failed to see interrupt acknowledge\n");
+ return -2;
+ } else {
+ printf("emif_reset interrupt acknowledged\n");
+ }
+
+ if (emif_clear()) {
+ printf("emif_clear() failed\n");
+ return -3;
+ }
+ pr_debug("emif_reset interrupt cleared\n");
+
+ pr_debug("nr0=%08x nr1=%08x nr2=%08x\n",
+ readl(IO48_MMR_NIOS2_RESERVE0),
+ readl(IO48_MMR_NIOS2_RESERVE1),
+ readl(IO48_MMR_NIOS2_RESERVE2));
+
+ return 0;
+}
+
+static int arria10_ddr_setup(void)
+{
+ int i, j, retcode, ddr_setup_complete = 0;
+ int chip_version = readl(ARRIA10_SYSMGR_SILICONID1);
+
+ /* Try 3 times to do a calibration */
+ for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
+ /* Only engineering sample needs calibration workaround */
+ if (ARRIA10_ES_SILICON_VER == chip_version) {
+ retcode = ddr_calibration_es_workaround();
+ if (retcode) {
+ printf("DDRCAL: Failure: %d\n", retcode);
+ continue;
+ }
+ }
+
+ /* A delay to wait for calibration bit to set */
+ for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
+ ddr_delay(500);
+ ddr_setup_complete = is_sdram_cal_success();
+ }
+
+ if (!ddr_setup_complete &&
+ (ARRIA10_ES_SILICON_VER != chip_version)) {
+ emif_reset();
+ }
+ }
+
+ if (!ddr_setup_complete) {
+ puts_ll("Error: Could Not Calibrate SDRAM\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+/* Function to startup the SDRAM*/
+static int arria10_sdram_startup(void)
+{
+ uint32_t val;
+ /* Release NOC ddr scheduler from reset */
+ val = readl(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_BRGMODRST);
+ val &= ~ARRIA10_RSTMGR_BRGMODRST_DDRSCH;
+ writel(val, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_BRGMODRST);
+
+ /* Bringup the DDR (calibration and configuration) */
+ return arria10_ddr_setup();
+}
+
+/* Function to initialize SDRAM MMR and NOC DDR scheduler*/
+static void arria10_sdram_mmr_init(void)
+{
+ uint32_t update_value, io48_value;
+ union ctrlcfg0_reg ctrlcfg0 =
+ (union ctrlcfg0_reg)readl(ARRIA10_IO48_HMC_MMR_CTRLCFG0);
+ union ctrlcfg1_reg ctrlcfg1 =
+ (union ctrlcfg1_reg)readl(ARRIA10_IO48_HMC_MMR_CTRLCFG1);
+ union dramaddrw_reg dramaddrw =
+ (union dramaddrw_reg)readl(ARRIA10_IO48_HMC_MMR_DRAMADDRW);
+ union caltiming0_reg caltim0 =
+ (union caltiming0_reg)readl(ARRIA10_IO48_HMC_MMR_CALTIMING0);
+ union caltiming1_reg caltim1 =
+ (union caltiming1_reg)readl(ARRIA10_IO48_HMC_MMR_CALTIMING1);
+ union caltiming2_reg caltim2 =
+ (union caltiming2_reg)readl(ARRIA10_IO48_HMC_MMR_CALTIMING2);
+ union caltiming3_reg caltim3 =
+ (union caltiming3_reg)readl(ARRIA10_IO48_HMC_MMR_CALTIMING3);
+ union caltiming4_reg caltim4 =
+ (union caltiming4_reg)readl(ARRIA10_IO48_HMC_MMR_CALTIMING4);
+ union caltiming9_reg caltim9 =
+ (union caltiming9_reg)readl(ARRIA10_IO48_HMC_MMR_CALTIMING9);
+ uint32_t ddrioctl;
+
+ /*
+ * Configure the DDR IO size [0xFFCFB008]
+ * niosreserve0: Used to indicate DDR width &
+ * bit[7:0] = Number of data bits (0x20 for 32bit)
+ * bit[8] = 1 if user-mode OCT is present
+ * bit[9] = 1 if warm reset compiled into EMIF Cal Code
+ * bit[10] = 1 if warm reset is on during generation in EMIF Cal
+ * niosreserve1: IP ADCDS version encoded as 16 bit value
+ * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
+ * 3=EAP, 4-6 are reserved)
+ * bit[5:3] = Service Pack # (e.g. 1)
+ * bit[9:6] = Minor Release #
+ * bit[14:10] = Major Release #
+ */
+ if ((readl(ARRIA10_IO48_HMC_MMR_NIOSRESERVE1) >> 6) & 0x1FF) {
+ update_value = readl(ARRIA10_IO48_HMC_MMR_NIOSRESERVE0);
+ writel(((update_value & 0xFF) >> 5),
+ ARRIA10_ECC_HMC_OCP_DDRIOCTRL);
+ }
+
+ ddrioctl = readl(ARRIA10_ECC_HMC_OCP_DDRIOCTRL);
+
+ /* Set the DDR Configuration [0xFFD12400] */
+ io48_value = ARRIA_DDR_CONFIG(ctrlcfg1.cfg_addr_order,
+ (dramaddrw.cfg_bank_addr_width +
+ dramaddrw.cfg_bank_group_addr_width),
+ dramaddrw.cfg_col_addr_width,
+ dramaddrw.cfg_row_addr_width);
+
+ update_value = match_ddr_conf(io48_value);
+ if (update_value)
+ writel(update_value, ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRCONF);
+
+ /*
+ * Configure DDR timing [0xFFD1240C]
+ * RDTOMISS = tRTP + tRP + tRCD - BL/2
+ * WRTOMISS = WL + tWR + tRP + tRCD and
+ * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so...
+ * First part of equation is in memory clock units so divide by 2
+ * for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
+ * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
+ */
+ update_value = (caltim2.cfg_rd_to_pch + caltim4.cfg_pch_to_valid +
+ caltim0.cfg_act_to_rdwr -
+ (ctrlcfg0.cfg_ctrl_burst_len >> 2));
+ io48_value = ((((readl(ARRIA10_IO48_HMC_MMR_DRAMTIMING0) &
+ ARRIA10_IO48_DRAMTIME_MEM_READ_LATENCY) + 2 + 15 +
+ (ctrlcfg0.cfg_ctrl_burst_len >> 1)) >> 1) -
+ /* Up to here was in memory cycles so divide by 2 */
+ caltim1.cfg_rd_to_wr + caltim0.cfg_act_to_rdwr +
+ caltim4.cfg_pch_to_valid);
+
+ writel(((caltim0.cfg_act_to_act <<
+ ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
+ (update_value <<
+ ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
+ (io48_value <<
+ ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
+ ((ctrlcfg0.cfg_ctrl_burst_len >> 2) <<
+ ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
+ (caltim1.cfg_rd_to_wr <<
+ ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
+ (caltim3.cfg_wr_to_rd <<
+ ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
+ (((ddrioctl == 1) ? 1 : 0) <<
+ ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
+ ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRTIMING);
+
+ /* Configure DDR mode [0xFFD12410] [precharge = 0] */
+ writel(((ddrioctl ? 0 : 1) <<
+ ARRIA10_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
+ ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRMODE);
+
+ /* Configure the read latency [0xFFD12414] */
+ writel(((readl(ARRIA10_IO48_HMC_MMR_DRAMTIMING0) &
+ ARRIA10_IO48_DRAMTIME_MEM_READ_LATENCY) >> 1) +
+ DDR_READ_LATENCY_DELAY,
+ ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_READLATENCY);
+
+ /*
+ * Configuring timing values concerning activate commands
+ * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
+ */
+ writel(((caltim0.cfg_act_to_act_db <<
+ ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
+ (caltim9.cfg_4_act_to_act <<
+ ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
+ (ARRIA10_SDR_ACTIVATE_FAWBANK <<
+ ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
+ ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_ACTIVATE);
+
+ /*
+ * Configuring timing values concerning device to device data bus
+ * ownership change [0xFFD1243C]
+ */
+ writel(((caltim1.cfg_rd_to_rd_dc <<
+ ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
+ (caltim1.cfg_rd_to_wr_dc <<
+ ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
+ (caltim3.cfg_wr_to_rd_dc <<
+ ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
+ ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DEVTODEV);
+
+ /* Enable or disable the SDRAM ECC */
+ if (ctrlcfg1.cfg_ctrl_enable_ecc) {
+ setbits_le32(ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL1,
+ (ARRIA10_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST |
+ ARRIA10_ECC_HMC_OCP_ECCCTL_CNT_RST |
+ ARRIA10_ECC_HMC_OCP_ECCCTL_ECC_EN));
+ clrbits_le32(ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL1,
+ (ARRIA10_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST |
+ ARRIA10_ECC_HMC_OCP_ECCCTL_CNT_RST));
+ setbits_le32(ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL2,
+ (ARRIA10_ECC_HMC_OCP_ECCCTL2_RMW_EN |
+ ARRIA10_ECC_HMC_OCP_ECCCTL2_AWB_EN));
+ } else {
+ clrbits_le32(ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL1,
+ (ARRIA10_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST |
+ ARRIA10_ECC_HMC_OCP_ECCCTL_CNT_RST |
+ ARRIA10_ECC_HMC_OCP_ECCCTL_ECC_EN));
+ clrbits_le32(ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL2,
+ (ARRIA10_ECC_HMC_OCP_ECCCTL2_RMW_EN |
+ ARRIA10_ECC_HMC_OCP_ECCCTL2_AWB_EN));
+ }
+}
+
+static int arria10_sdram_firewall_setup(void)
+{
+ uint32_t mpu_en = 0;
+
+ /* set to default state */
+ writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_EN);
+ writel(0x00000000, ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x00);
+
+ writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION0ADDR);
+
+ mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG0EN;
+
+ writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
+ writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION1ADDR);
+ writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION2ADDR);
+ writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION3ADDR);
+ writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION0ADDR);
+
+ mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG1EN;
+ writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
+
+ writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION1ADDR);
+ writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION2ADDR);
+ writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION3ADDR);
+ writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION0ADDR);
+
+ mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG2EN;
+ writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
+
+ writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION1ADDR);
+ writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION2ADDR);
+ writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION3ADDR);
+ writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION0ADDR);
+
+ mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG3EN;
+ writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
+
+ writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION1ADDR);
+ writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION2ADDR);
+ writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION3ADDR);
+
+ writel(0xffff0000, ARRIA10_NOC_FW_DDR_L3_HPSREGION0ADDR);
+ writel(ARRIA10_NOC_FW_DDR_L3_HPSREG0EN, ARRIA10_NOC_FW_DDR_L3_EN);
+
+ return 0;
+}
+
+int arria10_ddr_calibration_sequence(void)
+{
+ /* Check to see if SDRAM cal was success */
+ if (arria10_sdram_startup()) {
+ puts_ll("DDRCAL: Failed\n");
+ return -1;
+ }
+
+ puts_ll("DDRCAL: Success\n");
+
+ /* initialize the MMR register */
+ arria10_sdram_mmr_init();
+
+ if (arria10_sdram_firewall_setup())
+ puts_ll("FW: Error Configuring Firewall\n");
+
+ return 0;
+}
diff --git a/arch/arm/mach-socfpga/cyclone5-bootsource.c b/arch/arm/mach-socfpga/cyclone5-bootsource.c
index da4102c4f531..717a00342506 100644
--- a/arch/arm/mach-socfpga/cyclone5-bootsource.c
+++ b/arch/arm/mach-socfpga/cyclone5-bootsource.c
@@ -18,6 +18,7 @@
#include <io.h>
#include <mach/cyclone5-system-manager.h>
#include <mach/cyclone5-regs.h>
+#include <mach/arria10-system-manager.h>
#define CYCLONE5_SYSMGR_BOOTINFO 0x14
@@ -54,4 +55,46 @@ static int cyclone5_boot_save_loc(void)
return 0;
}
-core_initcall(cyclone5_boot_save_loc);
+
+static int arria10_boot_save_loc(void)
+{
+ enum bootsource src = BOOTSOURCE_UNKNOWN;
+ uint32_t val;
+
+ val = readl(ARRIA10_SYSMGR_BOOTINFO);
+
+ switch ((val & 0x7000) >> 12) {
+ case 0:
+ /* reserved */
+ break;
+ case 1:
+ /* FPGA, currently not decoded */
+ break;
+ case 2:
+ case 3:
+ src = BOOTSOURCE_NAND;
+ break;
+ case 4:
+ case 5:
+ src = BOOTSOURCE_MMC;
+ break;
+ case 6:
+ case 7:
+ src = BOOTSOURCE_SPI;
+ break;
+ }
+
+ bootsource_set(src);
+ bootsource_set_instance(0);
+
+ return 0;
+}
+
+static int socfpga_boot_save_loc(void)
+{
+ if (IS_ENABLED(CONFIG_ARCH_SOCFPGA_ARRIA10))
+ return arria10_boot_save_loc();
+ else
+ return cyclone5_boot_save_loc();
+}
+core_initcall(socfpga_boot_save_loc);
diff --git a/arch/arm/mach-socfpga/generic.c b/arch/arm/mach-socfpga/generic.c
deleted file mode 100644
index c920bd658fd7..000000000000
--- a/arch/arm/mach-socfpga/generic.c
+++ /dev/null
@@ -1,104 +0,0 @@
-#include <common.h>
-#include <malloc.h>
-#include <envfs.h>
-#include <init.h>
-#include <io.h>
-#include <fs.h>
-#include <linux/clkdev.h>
-#include <linux/clk.h>
-#include <linux/stat.h>
-#include <asm/memory.h>
-#include <mach/system-manager.h>
-#include <mach/reset-manager.h>
-#include <mach/socfpga-regs.h>
-#include <mach/nic301.h>
-
-#define SYSMGR_SDMMCGRP_CTRL_REG (CYCLONE5_SYSMGR_ADDRESS + 0x108)
-#define SYSMGR_SDMMC_CTRL_SMPLSEL(smplsel) (((smplsel) & 0x7) << 3)
-#define SYSMGR_SDMMC_CTRL_DRVSEL(drvsel) ((drvsel) & 0x7)
-
-static int socfpga_detect_sdram(void)
-{
- void __iomem *base = (void *)CYCLONE5_SDR_ADDRESS;
- uint32_t dramaddrw, ctrlwidth, memsize;
- int colbits, rowbits, bankbits;
- int width_bytes;
-
- dramaddrw = readl(base + 0x5000 + 0x2c);
-
- colbits = dramaddrw & 0x1f;
- rowbits = (dramaddrw >> 5) & 0x1f;
- bankbits = (dramaddrw >> 10) & 0x7;
-
- ctrlwidth = readl(base + 0x5000 + 0x60);
-
- switch (ctrlwidth & 0x3) {
- default:
- case 0:
- width_bytes = 1;
- break;
- case 1:
- width_bytes = 2;
- break;
- case 2:
- width_bytes = 4;
- break;
- }
-
- memsize = (1 << colbits) * (1 << rowbits) * (1 << bankbits) * width_bytes;
-
- pr_debug("%s: colbits: %d rowbits: %d bankbits: %d width: %d => memsize: 0x%08x\n",
- __func__, colbits, rowbits, bankbits, width_bytes, memsize);
-
- arm_add_mem_device("ram0", 0x0, memsize);
-
- return 0;
-}
-
-/* Some initialization for the EMAC */
-static void socfpga_init_emac(void)
-{
- uint32_t rst, val;
-
- /* No need for this without network support, e.g. xloader build */
- if (!IS_ENABLED(CONFIG_NET))
- return;
-
- /* According to Cyclone V datasheet, 17-60 "EMAC HPS Interface
- * Initialization", changing PHYSEL should be done with EMAC in reset
- * via permodrst. */
-
- /* Everything, except L4WD0/1, is out of reset via socfpga_lowlevel_init() */
- rst = readl(CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS);
- rst |= RSTMGR_PERMODRST_EMAC0 | RSTMGR_PERMODRST_EMAC1;
- writel(rst, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS);
-
- /* Set emac0/1 PHY interface select to RGMII. We could read phy-mode
- * from the device tree, if it was desired to support interfaces other
- * than RGMII. */
- val = readl(CONFIG_SYSMGR_EMAC_CTRL);
- val &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB);
- val &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB);
- val |= SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
- val |= SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
- writel(val, CONFIG_SYSMGR_EMAC_CTRL);
-
- /* Take emac0 and emac1 out of reset */
- rst &= ~(RSTMGR_PERMODRST_EMAC0 | RSTMGR_PERMODRST_EMAC1);
- writel(rst, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS);
-}
-
-static int socfpga_init(void)
-{
- socfpga_init_emac();
-
- writel(SYSMGR_SDMMC_CTRL_DRVSEL(3) | SYSMGR_SDMMC_CTRL_SMPLSEL(0),
- SYSMGR_SDMMCGRP_CTRL_REG);
-
- nic301_slave_ns();
-
- socfpga_detect_sdram();
-
- return 0;
-}
-core_initcall(socfpga_init);
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h b/arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h
new file mode 100644
index 000000000000..ee2b9b3c5ec1
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/arria10-clock-manager.h
@@ -0,0 +1,249 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ARRIA10_CLOCK_MANAGER_H_
+#define _ARRIA10_CLOCK_MANAGER_H_
+
+struct arria10_clock_manager {
+ /* clkmgr */
+ volatile uint32_t ctrl;
+ volatile uint32_t intr;
+ volatile uint32_t intrs;
+ volatile uint32_t intrr;
+ volatile uint32_t intren;
+ volatile uint32_t intrens;
+ volatile uint32_t intrenr;
+ volatile uint32_t stat;
+ volatile uint32_t testioctrl;
+ volatile uint32_t _pad_0x24_0x40[7];
+
+ /* mainpllgrp*/
+ volatile uint32_t main_pll_vco0;
+ volatile uint32_t main_pll_vco1;
+ volatile uint32_t main_pll_en;
+ volatile uint32_t main_pll_ens;
+ volatile uint32_t main_pll_enr;
+ volatile uint32_t main_pll_bypass;
+ volatile uint32_t main_pll_bypasss;
+ volatile uint32_t main_pll_bypassr;
+ volatile uint32_t main_pll_mpuclk;
+ volatile uint32_t main_pll_nocclk;
+ volatile uint32_t main_pll_cntr2clk;
+ volatile uint32_t main_pll_cntr3clk;
+ volatile uint32_t main_pll_cntr4clk;
+ volatile uint32_t main_pll_cntr5clk;
+ volatile uint32_t main_pll_cntr6clk;
+ volatile uint32_t main_pll_cntr7clk;
+ volatile uint32_t main_pll_cntr8clk;
+ volatile uint32_t main_pll_cntr9clk;
+ volatile uint32_t main_pll__pad_0x48_0x5b[5];
+ volatile uint32_t main_pll_cntr15clk;
+ volatile uint32_t main_pll_outrst;
+ volatile uint32_t main_pll_outrststat;
+ volatile uint32_t main_pll_nocdiv;
+ volatile uint32_t main_pll__pad_0x6c_0x80[5];
+
+ /* perpllgrp*/
+ volatile uint32_t per_pll_vco0;
+ volatile uint32_t per_pll_vco1;
+ volatile uint32_t per_pll_en;
+ volatile uint32_t per_pll_ens;
+ volatile uint32_t per_pll_enr;
+ volatile uint32_t per_pll_bypass;
+ volatile uint32_t per_pll_bypasss;
+ volatile uint32_t per_pll_bypassr;
+ volatile uint32_t per_pll__pad_0x20_0x27[2];
+ volatile uint32_t per_pll_cntr2clk;
+ volatile uint32_t per_pll_cntr3clk;
+ volatile uint32_t per_pll_cntr4clk;
+ volatile uint32_t per_pll_cntr5clk;
+ volatile uint32_t per_pll_cntr6clk;
+ volatile uint32_t per_pll_cntr7clk;
+ volatile uint32_t per_pll_cntr8clk;
+ volatile uint32_t per_pll_cntr9clk;
+ volatile uint32_t per_pll__pad_0x48_0x5f[6];
+ volatile uint32_t per_pll_outrst;
+ volatile uint32_t per_pll_outrststat;
+ volatile uint32_t per_pll_emacctl;
+ volatile uint32_t per_pll_gpiodiv;
+ volatile uint32_t per_pll__pad_0x70_0x80[4];
+};
+
+struct arria10_mainpll_cfg {
+ uint32_t vco0_psrc;
+ uint32_t vco1_denom;
+ uint32_t vco1_numer;
+ uint32_t mpuclk;
+ uint32_t mpuclk_cnt;
+ uint32_t mpuclk_src;
+ uint32_t nocclk;
+ uint32_t nocclk_cnt;
+ uint32_t nocclk_src;
+ uint32_t cntr2clk_cnt;
+ uint32_t cntr3clk_cnt;
+ uint32_t cntr4clk_cnt;
+ uint32_t cntr5clk_cnt;
+ uint32_t cntr6clk_cnt;
+ uint32_t cntr7clk_cnt;
+ uint32_t cntr7clk_src;
+ uint32_t cntr8clk_cnt;
+ uint32_t cntr9clk_cnt;
+ uint32_t cntr9clk_src;
+ uint32_t cntr15clk_cnt;
+ uint32_t nocdiv_l4mainclk;
+ uint32_t nocdiv_l4mpclk;
+ uint32_t nocdiv_l4spclk;
+ uint32_t nocdiv_csatclk;
+ uint32_t nocdiv_cstraceclk;
+ uint32_t nocdiv_cspdbgclk;
+};
+
+struct arria10_perpll_cfg {
+ uint32_t vco0_psrc;
+ uint32_t vco1_denom;
+ uint32_t vco1_numer;
+ uint32_t cntr2clk_cnt;
+ uint32_t cntr2clk_src;
+ uint32_t cntr3clk_cnt;
+ uint32_t cntr3clk_src;
+ uint32_t cntr4clk_cnt;
+ uint32_t cntr4clk_src;
+ uint32_t cntr5clk_cnt;
+ uint32_t cntr5clk_src;
+ uint32_t cntr6clk_cnt;
+ uint32_t cntr6clk_src;
+ uint32_t cntr7clk_cnt;
+ uint32_t cntr8clk_cnt;
+ uint32_t cntr8clk_src;
+ uint32_t cntr9clk_cnt;
+ uint32_t cntr9clk_src;
+ uint32_t emacctl_emac0sel;
+ uint32_t emacctl_emac1sel;
+ uint32_t emacctl_emac2sel;
+ uint32_t gpiodiv_gpiodbclk;
+};
+
+extern int arria10_cm_basic_init(struct arria10_mainpll_cfg *mainpll_cfg,
+ struct arria10_perpll_cfg *perpll_cfg);
+extern unsigned int cm_get_mmc_controller_clk_hz(void);
+extern void arria10_cm_use_intosc(void);
+extern uint32_t cm_l4_main_clk_hz;
+extern uint32_t cm_l4_sp_clk_hz;
+extern uint32_t cm_l4_mp_clk_hz;
+extern uint32_t cm_l4_sys_free_clk_hz;
+
+#define ARRIA10_CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140
+#define ARRIA10_CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144
+
+/* value */
+#define ARRIA10_CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_RESET 0x00010053
+#define ARRIA10_CLKMGR_MAINPLL_VCO1_RESET 0x00010001
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_EOSC 0x0
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_F2S 0x2
+#define ARRIA10_CLKMGR_PERPLL_BYPASS_RESET 0x000000ff
+#define ARRIA10_CLKMGR_PERPLL_VCO0_RESET 0x00010053
+#define ARRIA10_CLKMGR_PERPLL_VCO1_RESET 0x00010001
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_EOSC 0x0
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC 0x1
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_F2S 0x2
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MAIN 0x3
+
+/* mask */
+#define ARRIA10_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK 0x00000040
+#define ARRIA10_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK 0x00000080
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK 0x00000001
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK 0x00000002
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_EN_SET_MSK 0x00000004
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK 0x00000008
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK 0x00000010
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_MSK 0x00000003
+#define ARRIA10_CLKMGR_MAINPLL_VCO1_NUMER_MSK 0x00001fff
+#define ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_MSK 0x0000003f
+#define ARRIA10_CLKMGR_MAINPLL_CNTRCLK_MSK 0x000003ff
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_CNT_MSK 0x000003ff
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_MAIN 0
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_PERI 1
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_OSC1 2
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC 3
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_FPGA 4
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_MSK 0x00000003
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_CNT_MSK 0x000003ff
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MSK 0x00000007
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_MAIN 0
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_PERI 1
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_OSC1 2
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC 3
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_FPGA 4
+#define ARRIA10_CLKMGR_CLKMGR_STAT_BUSY_SET_MSK 0x00000001
+#define ARRIA10_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK 0x00000100
+#define ARRIA10_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK 0x00000200
+#define ARRIA10_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK 0x00020000
+#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK 0x00000800
+#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK 0x00000400
+#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK 0x00000200
+#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK 0x00000100
+#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK 0x00000008
+#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK 0x00000004
+#define ARRIA10_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK 0x00000001
+#define ARRIA10_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK 0x00000002
+#define ARRIA10_CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK 0x00000001
+#define ARRIA10_CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK 0x00000300
+#define ARRIA10_CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK 0x00000001
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK 0x00000002
+#define ARRIA10_CLKMGR_PERPLL_VCO0_EN_SET_MSK 0x00000004
+#define ARRIA10_CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK 0x00000008
+#define ARRIA10_CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK 0x00000010
+#define ARRIA10_CLKMGR_PERPLL_EN_RESET 0x00000f7f
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_MSK 0x00000003
+#define ARRIA10_CLKMGR_PERPLL_VCO1_NUMER_MSK 0x00001fff
+#define ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_MSK 0x0000003f
+#define ARRIA10_CLKMGR_PERPLL_CNTRCLK_MSK 0x000003ff
+
+#define ARRIA10_CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020
+#define ARRIA10_CLKMGR_PERPLLGRP_SRC_MSK 0x00000007
+#define ARRIA10_CLKMGR_PERPLLGRP_SRC_MAIN 0
+#define ARRIA10_CLKMGR_PERPLLGRP_SRC_PERI 1
+#define ARRIA10_CLKMGR_PERPLLGRP_SRC_OSC1 2
+#define ARRIA10_CLKMGR_PERPLLGRP_SRC_INTOSC 3
+#define ARRIA10_CLKMGR_PERPLLGRP_SRC_FPGA 4
+
+/* bit shifting macro */
+#define ARRIA10_CLKMGR_MAINPLL_VCO0_PSRC_LSB 8
+#define ARRIA10_CLKMGR_MAINPLL_VCO1_DENOM_LSB 16
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB 16
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB 0
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB 8
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB 16
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB 24
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB 26
+#define ARRIA10_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB 28
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB 16
+#define ARRIA10_CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_PERPLL_VCO1_DENOM_LSB 16
+#define ARRIA10_CLKMGR_PERPLL_VCO0_PSRC_LSB 8
+#define ARRIA10_CLKMGR_PERPLL_CNTR2CLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_PERPLL_CNTR3CLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_PERPLL_CNTR4CLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_PERPLL_CNTR5CLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_PERPLL_CNTR6CLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_PERPLL_CNTR8CLK_SRC_LSB 16
+#define ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB 26
+#define ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB 27
+#define ARRIA10_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB 28
+
+/* PLL ramping work around */
+#define ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ 900000000
+#define ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ 300000000
+#define ARRIA10_CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ 100000000
+#define ARRIA10_CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ 33000000
+
+#endif /* _ARRIA10_CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-pinmux.h b/arch/arm/mach-socfpga/include/mach/arria10-pinmux.h
new file mode 100644
index 000000000000..804fae0309be
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/arria10-pinmux.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2017 Pengutronix, Steffen Trumtrar <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _ARRIA10_PINMUX_H_
+#define _ARRIA10_PINMUX_H_
+
+struct arria10_pinmux_cfg {
+ uint32_t shared_io_q1_1;
+ uint32_t shared_io_q1_2;
+ uint32_t shared_io_q1_3;
+ uint32_t shared_io_q1_4;
+ uint32_t shared_io_q1_5;
+ uint32_t shared_io_q1_6;
+ uint32_t shared_io_q1_7;
+ uint32_t shared_io_q1_8;
+ uint32_t shared_io_q1_9;
+ uint32_t shared_io_q1_10;
+ uint32_t shared_io_q1_11;
+ uint32_t shared_io_q1_12;
+
+ uint32_t shared_io_q2_1;
+ uint32_t shared_io_q2_2;
+ uint32_t shared_io_q2_3;
+ uint32_t shared_io_q2_4;
+ uint32_t shared_io_q2_5;
+ uint32_t shared_io_q2_6;
+ uint32_t shared_io_q2_7;
+ uint32_t shared_io_q2_8;
+ uint32_t shared_io_q2_9;
+ uint32_t shared_io_q2_10;
+ uint32_t shared_io_q2_11;
+ uint32_t shared_io_q2_12;
+
+ uint32_t shared_io_q3_1;
+ uint32_t shared_io_q3_2;
+ uint32_t shared_io_q3_3;
+ uint32_t shared_io_q3_4;
+ uint32_t shared_io_q3_5;
+ uint32_t shared_io_q3_6;
+ uint32_t shared_io_q3_7;
+ uint32_t shared_io_q3_8;
+ uint32_t shared_io_q3_9;
+ uint32_t shared_io_q3_10;
+ uint32_t shared_io_q3_11;
+ uint32_t shared_io_q3_12;
+
+ uint32_t shared_io_q4_1;
+ uint32_t shared_io_q4_2;
+ uint32_t shared_io_q4_3;
+ uint32_t shared_io_q4_4;
+ uint32_t shared_io_q4_5;
+ uint32_t shared_io_q4_6;
+ uint32_t shared_io_q4_7;
+ uint32_t shared_io_q4_8;
+ uint32_t shared_io_q4_9;
+ uint32_t shared_io_q4_10;
+ uint32_t shared_io_q4_11;
+ uint32_t shared_io_q4_12;
+
+ uint32_t dedicated_io_4;
+ uint32_t dedicated_io_5;
+ uint32_t dedicated_io_6;
+ uint32_t dedicated_io_7;
+ uint32_t dedicated_io_8;
+ uint32_t dedicated_io_9;
+ uint32_t dedicated_io_10;
+ uint32_t dedicated_io_11;
+ uint32_t dedicated_io_12;
+ uint32_t dedicated_io_13;
+ uint32_t dedicated_io_14;
+ uint32_t dedicated_io_15;
+ uint32_t dedicated_io_16;
+ uint32_t dedicated_io_17;
+
+ uint32_t cfg_dedicated_io_bank;
+ uint32_t cfg_dedicated_io_1;
+ uint32_t cfg_dedicated_io_2;
+ uint32_t cfg_dedicated_io_3;
+ uint32_t cfg_dedicated_io_4;
+ uint32_t cfg_dedicated_io_5;
+ uint32_t cfg_dedicated_io_6;
+ uint32_t cfg_dedicated_io_7;
+ uint32_t cfg_dedicated_io_8;
+ uint32_t cfg_dedicated_io_9;
+ uint32_t cfg_dedicated_io_10;
+ uint32_t cfg_dedicated_io_11;
+ uint32_t cfg_dedicated_io_12;
+ uint32_t cfg_dedicated_io_13;
+ uint32_t cfg_dedicated_io_14;
+ uint32_t cfg_dedicated_io_15;
+ uint32_t cfg_dedicated_io_16;
+ uint32_t cfg_dedicated_io_17;
+
+ bool rgmii0_usefpga;
+ bool rgmii1_usefpga;
+ bool rgmii2_usefpga;
+ bool nand_usefpga;
+ bool qspi_usefpga;
+ bool sdmmc_usefpga;
+ bool usb0_usefpga;
+ bool usb1_usefpga;
+ bool spim0_usefpga;
+ bool spim1_usefpga;
+ bool spis0_usefpga;
+ bool spis1_usefpga;
+ bool uart0_usefpga;
+ bool uart1_usefpga;
+ bool i2c0_usefpga;
+ bool i2c1_usefpga;
+ bool i2cemac0_usefpga;
+ bool i2cemac1_usefpga;
+ bool i2cemac2_usefpga;
+ bool pll_clock_out_usefpga;
+};
+
+#endif
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-regs.h b/arch/arm/mach-socfpga/include/mach/arria10-regs.h
new file mode 100644
index 000000000000..44a3f69c24c9
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/arria10-regs.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ARRIA10_HARDWARE_H_
+#define _ARRIA10_HARDWARE_H_
+
+#define ARRIA10_EMAC0_ADDR (0xff800000)
+#define ARRIA10_EMAC1_ADDR (0xff802000)
+#define ARRIA10_EMAC2_ADDR (0xff804000)
+#define ARRIA10_SDMMC_ADDR (0xff808000)
+#define ARRIA10_QSPIREGS_ADDR (0xff809000)
+#define ARRIA10_ECC_OCRAM_ADDR (0xff8c3000)
+#define ARRIA10_QSPIDATA_ADDR (0xffa00000)
+#define ARRIA10_UART0_ADDR (0xffc02000)
+#define ARRIA10_UART1_ADDR (0xffc02100)
+#define ARRIA10_I2C0_ADDR (0xffc02200)
+#define ARRIA10_I2C1_ADDR (0xffc02300)
+#define ARRIA10_GPIO0_ADDR (0xffc02900)
+#define ARRIA10_GPIO1_ADDR (0xffc02a00)
+#define ARRIA10_GPIO2_ADDR (0xffc02b00)
+#define ARRIA10_HMC_MMR_IO48_ADDR (0xffcfa000)
+#define ARRIA10_SDR_ADDR (0xffcfb000)
+#define ARRIA10_FPGAMGRDATA_ADDR (0xffcfe400)
+#define ARRIA10_OSC1TIMER0_ADDR (0xffd00000)
+#define ARRIA10_L4WD0_ADDR (0xffd00200)
+#define ARRIA10_FPGAMGRREGS_ADDR (0xffd03000)
+#define ARRIA10_CLKMGR_ADDR (0xffd04000)
+#define ARRIA10_RSTMGR_ADDR (0xffd05000)
+#define ARRIA10_SYSMGR_ADDR (0xffd06000)
+#define ARRIA10_PINMUX_SHARED_3V_IO_ADDR (0xffd07000)
+#define ARRIA10_PINMUX_DEDICATED_IO_ADDR (0xffd07200)
+#define ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR (0xffd07300)
+#define ARRIA10_PINMUX_FPGA_INTERFACE_ADDR (0xffd07400)
+#define ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR (0xffd11000)
+#define ARRIA10_SDR_SCHEDULER_ADDR (0xffd12400)
+#define ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR (0xffd13000)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR (0xffd13200)
+#define ARRIA10_SDR_FW_MPU_FPGA_ADDR (0xffd13300)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR (0xffd13400)
+#define ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_ADDR (0xffd13500)
+#define ARRIA10_DMANONSECURE_ADDR (0xffda0000)
+#define ARRIA10_DMASECURE_ADDR (0xffda1000)
+#define ARRIA10_MPUSCU_ADDR (0xffffc000)
+#define ARRIA10_MPUL2_ADDR (0xfffff000)
+
+/* L2 cache controller */
+#define ARRIA10_MPUL2_ADRFLTR_START (ARRIA10_MPUL2_ADDR + 0xC00)
+
+/* NOC L4 Priv */
+#define ARRIA10_NOC_L4_PRIV_L4_PRIV_L4_PRIV (ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR + 0x00)
+#define ARRIA10_NOC_L4_PRIV_L4_PRIV_L4_PRIV_SET (ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR + 0x04)
+#define ARRIA10_NOC_L4_PRIV_L4_PRIV_L4_PRIV_CLR (ARRIA10_NOC_L4_PRIV_L4_PRIV_FILTER_ADDR + 0x08)
+
+/* NOC L4 Permissions */
+#define ARRIA10_NOC_FW_L4_PER_SCR_NAND_REG (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x00)
+#define ARRIA10_NOC_FW_L4_PER_SCR_NAND_DATA (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x04)
+#define ARRIA10_NOC_FW_L4_PER_SCR_QSPI_DATA (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x08)
+#define ARRIA10_NOC_FW_L4_PER_SCR_USB0_REG (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x0c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_USB1_REG (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x10)
+#define ARRIA10_NOC_FW_L4_PER_SCR_DMA_NONSECURE (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x14)
+#define ARRIA10_NOC_FW_L4_PER_SCR_DMA_SECURE (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x18)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SPIM0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x1c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SPIM1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x20)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SPIS0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x24)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SPIS1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x28)
+#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x2c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x30)
+#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC2 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x34)
+#define ARRIA10_NOC_FW_L4_PER_SCR_EMAC3 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x38)
+#define ARRIA10_NOC_FW_L4_PER_SCR_QSPI (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x3c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SDMMC (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x40)
+#define ARRIA10_NOC_FW_L4_PER_SCR_GPIO0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x44)
+#define ARRIA10_NOC_FW_L4_PER_SCR_GPIO1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x48)
+#define ARRIA10_NOC_FW_L4_PER_SCR_GPIO2 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x4c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_I2C0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x50)
+#define ARRIA10_NOC_FW_L4_PER_SCR_I2C1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x54)
+#define ARRIA10_NOC_FW_L4_PER_SCR_I2C2 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x58)
+#define ARRIA10_NOC_FW_L4_PER_SCR_I2C3 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x5c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_I2C4 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x60)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SPTIMER0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x64)
+#define ARRIA10_NOC_FW_L4_PER_SCR_SPTIMER1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x68)
+#define ARRIA10_NOC_FW_L4_PER_SCR_UART0 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x6c)
+#define ARRIA10_NOC_FW_L4_PER_SCR_UART1 (ARRIA10_NOC_L4_PER_L4_PER_SCR_ADDR + 0x70)
+
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x00)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN_SET (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x04)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN_CLR (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x08)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION0 (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x0c)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION1 (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x10)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION2 (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x14)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION3 (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x18)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION4 (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x1c)
+#define ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION5 (ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_ADDR + 0x20)
+
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_EN (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x00)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_EN_SET (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x04)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_EN_CLR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x08)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION0 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x0c)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION1 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x10)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION2 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x14)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION3 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x18)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION4 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x1c)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION5 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x20)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION6 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x24)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_REGION7 (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x28)
+#define ARRIA10_NOC_FW_DDR_L3_DDR_SCR_GLOBAL (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x2c)
+
+#define ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_LWSOC2FPGA (ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_ADDR + 0x00)
+#define ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_SOC2FPGA (ARRIA10_NOC_FW_SOC2FPGA_SOC2FPGA_SCR_ADDR + 0x04)
+
+#endif
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h b/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h
new file mode 100644
index 000000000000..9814d18d5547
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/arria10-reset-manager.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ARRIA10_RESET_MANAGER_H_
+#define _ARRIA10_RESET_MANAGER_H_
+
+#define ARRIA10_RSTMGR_STATUS 0x0
+#define ARRIA10_RSTMGR_RAMSTAT 0x4
+#define ARRIA10_RSTMGR_MISCSTAT 0x8
+#define ARRIA10_RSTMGR_CTRL 0xc
+#define ARRIA10_RSTMGR_HDSKEN 0x10
+#define ARRIA10_RSTMGR_HDSKREQ 0x14
+#define ARRIA10_RSTMGR_HDSKACK 0x18
+#define ARRIA10_RSTMGR_COUNTS 0x1c
+#define ARRIA10_RSTMGR_MPUMODRST 0x20
+#define ARRIA10_RSTMGR_PER0MODRST 0x24
+#define ARRIA10_RSTMGR_PER1MODRST 0x28
+#define ARRIA10_RSTMGR_BRGMODRST 0x2c
+#define ARRIA10_RSTMGR_SYSMODRST 0x30
+#define ARRIA10_RSTMGR_COLDMODRST 0x34
+#define ARRIA10_RSTMGR_NRSTMODRST 0x38
+#define ARRIA10_RSTMGR_DBGMODRST 0x3c
+#define ARRIA10_RSTMGR_MPUWARMMASK 0x40
+#define ARRIA10_RSTMGR_PER0WARMMASK 0x44
+#define ARRIA10_RSTMGR_PER1WARMMASK 0x48
+#define ARRIA10_RSTMGR_BRGWARMMASK 0x4c
+#define ARRIA10_RSTMGR_SYSWARMMASK 0x50
+#define ARRIA10_RSTMGR_NRSTWARMMASK 0x54
+#define ARRIA10_RSTMGR_L3WARMMASK 0x58
+#define ARRIA10_RSTMGR_TSTSTA 0x5c
+#define ARRIA10_RSTMGR_TSTSCRATCH 0x60
+#define ARRIA10_RSTMGR_HDSKTIMEOUT 0x64
+#define ARRIA10_RSTMGR_HMCINTR 0x68
+#define ARRIA10_RSTMGR_HMCINTREN 0x6c
+#define ARRIA10_RSTMGR_HMCINTRENS 0x70
+#define ARRIA10_RSTMGR_HMCINTRENR 0x74
+#define ARRIA10_RSTMGR_HMCGPOUT 0x78
+#define ARRIA10_RSTMGR_HMCGPIN 0x7c
+
+#define ARRIA10_RSTMGR_CTL_SWWARMRSTREQ 0x00000002
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC0 0x00000001
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC1 0x00000002
+#define ARRIA10_RSTMGR_PER0MODRST_EMAC2 0x00000004
+#define ARRIA10_RSTMGR_PER0MODRST_USB0 0x00000008
+#define ARRIA10_RSTMGR_PER0MODRST_USB1 0x00000010
+#define ARRIA10_RSTMGR_PER0MODRST_NAND 0x00000020
+#define ARRIA10_RSTMGR_PER0MODRST_QSPI 0x00000040
+#define ARRIA10_RSTMGR_PER0MODRST_SDMMC 0x00000080
+#define ARRIA10_RSTMGR_PER0MODRST_EMACECC0 0x00000100
+#define ARRIA10_RSTMGR_PER0MODRST_EMACECC1 0x00000200
+#define ARRIA10_RSTMGR_PER0MODRST_EMACECC2 0x00000400
+#define ARRIA10_RSTMGR_PER0MODRST_USBECC0 0x00000800
+#define ARRIA10_RSTMGR_PER0MODRST_USBECC1 0x00001000
+#define ARRIA10_RSTMGR_PER0MODRST_NANDECC 0x00002000
+#define ARRIA10_RSTMGR_PER0MODRST_QSPIECC 0x00004000
+#define ARRIA10_RSTMGR_PER0MODRST_SDMMCECC 0x00008000
+#define ARRIA10_RSTMGR_PER0MODRST_DMA 0x00010000
+#define ARRIA10_RSTMGR_PER0MODRST_SPIM0 0x00020000
+#define ARRIA10_RSTMGR_PER0MODRST_SPIM1 0x00040000
+#define ARRIA10_RSTMGR_PER0MODRST_SPIS0 0x00080000
+#define ARRIA10_RSTMGR_PER0MODRST_SPIS1 0x00100000
+#define ARRIA10_RSTMGR_PER0MODRST_DMAECC 0x00200000
+#define ARRIA10_RSTMGR_PER0MODRST_EMACPTP 0x00400000
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF0 0x01000000
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF1 0x02000000
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF2 0x04000000
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF3 0x08000000
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF4 0x10000000
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF5 0x20000000
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF6 0x40000000
+#define ARRIA10_RSTMGR_PER0MODRST_DMAIF7 0x80000000
+
+#define ARRIA10_RSTMGR_PER1MODRST_L4WD0 0x00000001
+#define ARRIA10_RSTMGR_PER1MODRST_L4WD1 0x00000002
+#define ARRIA10_RSTMGR_PER1MODRST_L4SYSTMR0 0x00000004
+#define ARRIA10_RSTMGR_PER1MODRST_L4SYSTMR1 0x00000008
+#define ARRIA10_RSTMGR_PER1MODRST_SPTMR0 0x00000010
+#define ARRIA10_RSTMGR_PER1MODRST_SPTMR1 0x00000020
+#define ARRIA10_RSTMGR_PER1MODRST_I2C0 0x00000100
+#define ARRIA10_RSTMGR_PER1MODRST_I2C1 0x00000200
+#define ARRIA10_RSTMGR_PER1MODRST_I2C2 0x00000400
+#define ARRIA10_RSTMGR_PER1MODRST_I2C3 0x00000800
+#define ARRIA10_RSTMGR_PER1MODRST_I2C4 0x00001000
+#define ARRIA10_RSTMGR_PER1MODRST_UART0 0x00010000
+#define ARRIA10_RSTMGR_PER1MODRST_UART1 0x00020000
+#define ARRIA10_RSTMGR_PER1MODRST_GPIO0 0x01000000
+#define ARRIA10_RSTMGR_PER1MODRST_GPIO1 0x02000000
+#define ARRIA10_RSTMGR_PER1MODRST_GPIO2 0x04000000
+
+#define ARRIA10_RSTMGR_BRGMODRST_H2F 0x00000001
+#define ARRIA10_RSTMGR_BRGMODRST_LWH2F 0x00000002
+#define ARRIA10_RSTMGR_BRGMODRST_F2H 0x00000004
+#define ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM0 0x00000008
+#define ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM1 0x00000010
+#define ARRIA10_RSTMGR_BRGMODRST_F2SSDRAM2 0x00000020
+#define ARRIA10_RSTMGR_BRGMODRST_DDRSCH 0x00000040
+
+#define ARRIA10_RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001
+#define ARRIA10_RSTMGR_HDSKEN_FPGAMGRHSEN 0x00000002
+#define ARRIA10_RSTMGR_HDSKEN_FPGAHSEN 0x00000004
+#define ARRIA10_RSTMGR_HDSKEN_ETRSTALLEN 0x00000008
+
+#define ECC_MASK (ARRIA10_RSTMGR_PER0MODRST_EMACECC0 | \
+ ARRIA10_RSTMGR_PER0MODRST_EMACECC1 | \
+ ARRIA10_RSTMGR_PER0MODRST_EMACECC2 | \
+ ARRIA10_RSTMGR_PER0MODRST_NANDECC | \
+ ARRIA10_RSTMGR_PER0MODRST_QSPIECC | \
+ ARRIA10_RSTMGR_PER0MODRST_SDMMCECC)
+
+void arria10_reset_peripherals(void);
+void arria10_reset_deassert_dedicated_peripherals(void);
+void arria10_reset_deassert_shared_peripherals(void);
+void arria10_reset_deassert_fpga_peripherals(void);
+
+#endif
+
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-sdram.h b/arch/arm/mach-socfpga/include/mach/arria10-sdram.h
new file mode 100644
index 000000000000..07e4dd013089
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/arria10-sdram.h
@@ -0,0 +1,353 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <mach/arria10-system-manager.h>
+
+#ifndef _ARRIA10_SDRAM_H_
+#define _ARRIA10_SDRAM_H_
+
+#define ARRIA10_ECC_HMC_OCP_IP_REV_ID (ARRIA10_SDR_ADDR + 0x00)
+#define ARRIA10_ECC_HMC_OCP_DDRIOCTRL (ARRIA10_SDR_ADDR + 0x08)
+#define ARRIA10_ECC_HMC_OCP_DDRCALSTAT (ARRIA10_SDR_ADDR + 0x0c)
+#define ARRIA10_ECC_HMC_OCP_MPR_OBEAT1 (ARRIA10_SDR_ADDR + 0x10)
+#define ARRIA10_ECC_HMC_OCP_MPR_1BEAT1 (ARRIA10_SDR_ADDR + 0x14)
+#define ARRIA10_ECC_HMC_OCP_MPR_2BEAT1 (ARRIA10_SDR_ADDR + 0x18)
+#define ARRIA10_ECC_HMC_OCP_MPR_3BEAT1 (ARRIA10_SDR_ADDR + 0x1c)
+#define ARRIA10_ECC_HMC_OCP_MPR_4BEAT1 (ARRIA10_SDR_ADDR + 0x20)
+#define ARRIA10_ECC_HMC_OCP_MPR_5BEAT1 (ARRIA10_SDR_ADDR + 0x24)
+#define ARRIA10_ECC_HMC_OCP_MPR_6BEAT1 (ARRIA10_SDR_ADDR + 0x28)
+#define ARRIA10_ECC_HMC_OCP_MPR_7BEAT1 (ARRIA10_SDR_ADDR + 0x2c)
+#define ARRIA10_ECC_HMC_OCP_MPR_8BEAT1 (ARRIA10_SDR_ADDR + 0x30)
+#define ARRIA10_ECC_HMC_OCP_MPR_OBEAT2 (ARRIA10_SDR_ADDR + 0x34)
+#define ARRIA10_ECC_HMC_OCP_MPR_1BEAT2 (ARRIA10_SDR_ADDR + 0x38)
+#define ARRIA10_ECC_HMC_OCP_MPR_2BEAT2 (ARRIA10_SDR_ADDR + 0x3c)
+#define ARRIA10_ECC_HMC_OCP_MPR_3BEAT2 (ARRIA10_SDR_ADDR + 0x40)
+#define ARRIA10_ECC_HMC_OCP_MPR_4BEAT2 (ARRIA10_SDR_ADDR + 0x44)
+#define ARRIA10_ECC_HMC_OCP_MPR_5BEAT2 (ARRIA10_SDR_ADDR + 0x48)
+#define ARRIA10_ECC_HMC_OCP_MPR_6BEAT2 (ARRIA10_SDR_ADDR + 0x4c)
+#define ARRIA10_ECC_HMC_OCP_MPR_7BEAT2 (ARRIA10_SDR_ADDR + 0x50)
+#define ARRIA10_ECC_HMC_OCP_MPR_8BEAT2 (ARRIA10_SDR_ADDR + 0x54)
+#define ARRIA10_ECC_HMC_OCP_MPR_AUTO_PRECHARGE (ARRIA10_SDR_ADDR + 0x60)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL1 (ARRIA10_SDR_ADDR + 0x100)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECCCTRL2 (ARRIA10_SDR_ADDR + 0x104)
+#define ARRIA10_ECC_HMC_OCP_MPR_ERRINTEN (ARRIA10_SDR_ADDR + 0x110)
+#define ARRIA10_ECC_HMC_OCP_MPR_ERRINTENS (ARRIA10_SDR_ADDR + 0x114)
+#define ARRIA10_ECC_HMC_OCP_MPR_ERRINTENR (ARRIA10_SDR_ADDR + 0x118)
+#define ARRIA10_ECC_HMC_OCP_MPR_INTMODE (ARRIA10_SDR_ADDR + 0x11c)
+#define ARRIA10_ECC_HMC_OCP_MPR_INTSTAT (ARRIA10_SDR_ADDR + 0x120)
+#define ARRIA10_ECC_HMC_OCP_MPR_DIAGINTTEST (ARRIA10_SDR_ADDR + 0x124)
+#define ARRIA10_ECC_HMC_OCP_MPR_MODSTAT (ARRIA10_SDR_ADDR + 0x128)
+#define ARRIA10_ECC_HMC_OCP_MPR_DERRADDRA (ARRIA10_SDR_ADDR + 0x12c)
+#define ARRIA10_ECC_HMC_OCP_MPR_SERRADDRA (ARRIA10_SDR_ADDR + 0x130)
+#define ARRIA10_ECC_HMC_OCP_MPR_AUTOWB_CORRADDR (ARRIA10_SDR_ADDR + 0x138)
+#define ARRIA10_ECC_HMC_OCP_MPR_SERRCNTREG (ARRIA10_SDR_ADDR + 0x13c)
+#define ARRIA10_ECC_HMC_OCP_MPR_AUTOWB_DROP_CNTREG (ARRIA10_SDR_ADDR + 0x140)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2WRECCDATABUS (ARRIA10_SDR_ADDR + 0x144)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_RDECCDATA2REGBUS (ARRIA10_SDR_ADDR + 0x148)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDECCDATABUS (ARRIA10_SDR_ADDR + 0x14c)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_DIAGON (ARRIA10_SDR_ADDR + 0x150)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_DECSTAT (ARRIA10_SDR_ADDR + 0x154)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_0 (ARRIA10_SDR_ADDR + 0x160)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_1 (ARRIA10_SDR_ADDR + 0x164)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_2 (ARRIA10_SDR_ADDR + 0x168)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_ERRGENADDR_3 (ARRIA10_SDR_ADDR + 0x16c)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT0 (ARRIA10_SDR_ADDR + 0x170)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT1 (ARRIA10_SDR_ADDR + 0x174)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT2 (ARRIA10_SDR_ADDR + 0x178)
+#define ARRIA10_ECC_HMC_OCP_MPR_ECC_REG2RDDATABUS_BEAT3 (ARRIA10_SDR_ADDR + 0x17c)
+
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_ID_COREID (ARRIA10_SDR_SCHEDULER_ADDR + 0x00)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_ID_REVISIONID (ARRIA10_SDR_SCHEDULER_ADDR + 0x04)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRCONF (ARRIA10_SDR_SCHEDULER_ADDR + 0x08)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRTIMING (ARRIA10_SDR_SCHEDULER_ADDR + 0x0c)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DDRMODE (ARRIA10_SDR_SCHEDULER_ADDR + 0x10)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_READLATENCY (ARRIA10_SDR_SCHEDULER_ADDR + 0x14)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_ACTIVATE (ARRIA10_SDR_SCHEDULER_ADDR + 0x38)
+#define ARRIA10_NOC_DDR_T_MAIN_SCHEDULER_DEVTODEV (ARRIA10_SDR_SCHEDULER_ADDR + 0x3c)
+
+#define ARRIA10_IO48_HMC_MMR_DBGCFG0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x00)
+#define ARRIA10_IO48_HMC_MMR_DBGCFG1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x04)
+#define ARRIA10_IO48_HMC_MMR_DBGCFG2 (ARRIA10_HMC_MMR_IO48_ADDR + 0x08)
+#define ARRIA10_IO48_HMC_MMR_DBGCFG3 (ARRIA10_HMC_MMR_IO48_ADDR + 0x0c)
+#define ARRIA10_IO48_HMC_MMR_DBGCFG4 (ARRIA10_HMC_MMR_IO48_ADDR + 0x10)
+#define ARRIA10_IO48_HMC_MMR_DBGCFG5 (ARRIA10_HMC_MMR_IO48_ADDR + 0x14)
+#define ARRIA10_IO48_HMC_MMR_DBGCFG6 (ARRIA10_HMC_MMR_IO48_ADDR + 0x18)
+#define ARRIA10_IO48_HMC_MMR_RESERVE0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x1c)
+#define ARRIA10_IO48_HMC_MMR_RESERVE1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x20)
+#define ARRIA10_IO48_HMC_MMR_RESERVE2 (ARRIA10_HMC_MMR_IO48_ADDR + 0x24)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x28)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x2c)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG2 (ARRIA10_HMC_MMR_IO48_ADDR + 0x30)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG3 (ARRIA10_HMC_MMR_IO48_ADDR + 0x34)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG4 (ARRIA10_HMC_MMR_IO48_ADDR + 0x38)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG5 (ARRIA10_HMC_MMR_IO48_ADDR + 0x3c)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG6 (ARRIA10_HMC_MMR_IO48_ADDR + 0x40)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG7 (ARRIA10_HMC_MMR_IO48_ADDR + 0x44)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG8 (ARRIA10_HMC_MMR_IO48_ADDR + 0x48)
+#define ARRIA10_IO48_HMC_MMR_CTRLCFG9 (ARRIA10_HMC_MMR_IO48_ADDR + 0x4c)
+#define ARRIA10_IO48_HMC_MMR_DRAMTIMING0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x50)
+#define ARRIA10_IO48_HMC_MMR_DRAMODT0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x54)
+#define ARRIA10_IO48_HMC_MMR_DRAMODT1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x58)
+#define ARRIA10_IO48_HMC_MMR_SBCFG0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x5c)
+#define ARRIA10_IO48_HMC_MMR_SBCFG1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x60)
+#define ARRIA10_IO48_HMC_MMR_SBCFG2 (ARRIA10_HMC_MMR_IO48_ADDR + 0x64)
+#define ARRIA10_IO48_HMC_MMR_SBCFG3 (ARRIA10_HMC_MMR_IO48_ADDR + 0x68)
+#define ARRIA10_IO48_HMC_MMR_SBCFG4 (ARRIA10_HMC_MMR_IO48_ADDR + 0x6c)
+#define ARRIA10_IO48_HMC_MMR_SBCFG5 (ARRIA10_HMC_MMR_IO48_ADDR + 0x70)
+#define ARRIA10_IO48_HMC_MMR_SBCFG6 (ARRIA10_HMC_MMR_IO48_ADDR + 0x74)
+#define ARRIA10_IO48_HMC_MMR_SBCFG7 (ARRIA10_HMC_MMR_IO48_ADDR + 0x78)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x7c)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x80)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING2 (ARRIA10_HMC_MMR_IO48_ADDR + 0x84)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING3 (ARRIA10_HMC_MMR_IO48_ADDR + 0x88)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING4 (ARRIA10_HMC_MMR_IO48_ADDR + 0x8c)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING5 (ARRIA10_HMC_MMR_IO48_ADDR + 0x90)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING6 (ARRIA10_HMC_MMR_IO48_ADDR + 0x94)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING7 (ARRIA10_HMC_MMR_IO48_ADDR + 0x98)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING8 (ARRIA10_HMC_MMR_IO48_ADDR + 0x9c)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING9 (ARRIA10_HMC_MMR_IO48_ADDR + 0xa0)
+#define ARRIA10_IO48_HMC_MMR_CALTIMING10 (ARRIA10_HMC_MMR_IO48_ADDR + 0xa4)
+#define ARRIA10_IO48_HMC_MMR_DRAMADDRW (ARRIA10_HMC_MMR_IO48_ADDR + 0xa8)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND0 (ARRIA10_HMC_MMR_IO48_ADDR + 0xac)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND1 (ARRIA10_HMC_MMR_IO48_ADDR + 0xb0)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND2 (ARRIA10_HMC_MMR_IO48_ADDR + 0xb4)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND3 (ARRIA10_HMC_MMR_IO48_ADDR + 0xb8)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND4 (ARRIA10_HMC_MMR_IO48_ADDR + 0xbc)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND5 (ARRIA10_HMC_MMR_IO48_ADDR + 0xc0)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND6 (ARRIA10_HMC_MMR_IO48_ADDR + 0xc4)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND7 (ARRIA10_HMC_MMR_IO48_ADDR + 0xc8)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND8 (ARRIA10_HMC_MMR_IO48_ADDR + 0xcc)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND9 (ARRIA10_HMC_MMR_IO48_ADDR + 0xd0)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND10 (ARRIA10_HMC_MMR_IO48_ADDR + 0xd4)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND11 (ARRIA10_HMC_MMR_IO48_ADDR + 0xd8)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND12 (ARRIA10_HMC_MMR_IO48_ADDR + 0xdc)
+#define ARRIA10_IO48_HMC_MMR_SIDEBANB13 (ARRIA10_HMC_MMR_IO48_ADDR + 0xe0)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND14 (ARRIA10_HMC_MMR_IO48_ADDR + 0xe4)
+#define ARRIA10_IO48_HMC_MMR_SIDEBAND15 (ARRIA10_HMC_MMR_IO48_ADDR + 0xe8)
+#define ARRIA10_IO48_HMC_MMR_DRAMSTS (ARRIA10_HMC_MMR_IO48_ADDR + 0xec)
+#define ARRIA10_IO48_HMC_MMR_DBGDONE (ARRIA10_HMC_MMR_IO48_ADDR + 0xf0)
+#define ARRIA10_IO48_HMC_MMR_DBGSIGNALS (ARRIA10_HMC_MMR_IO48_ADDR + 0xf4)
+#define ARRIA10_IO48_HMC_MMR_DBGRESET (ARRIA10_HMC_MMR_IO48_ADDR + 0xf8)
+#define ARRIA10_IO48_HMC_MMR_DBGMATCH (ARRIA10_HMC_MMR_IO48_ADDR + 0xfc)
+#define ARRIA10_IO48_HMC_MMR_COUNTER0MASK (ARRIA10_HMC_MMR_IO48_ADDR + 0x100)
+#define ARRIA10_IO48_HMC_MMR_COUNTER1MASK (ARRIA10_HMC_MMR_IO48_ADDR + 0x104)
+#define ARRIA10_IO48_HMC_MMR_COUNTER0MATCH (ARRIA10_HMC_MMR_IO48_ADDR + 0x108)
+#define ARRIA10_IO48_HMC_MMR_COUNTER1MATCH (ARRIA10_HMC_MMR_IO48_ADDR + 0x10c)
+#define ARRIA10_IO48_HMC_MMR_NIOSRESERVE0 (ARRIA10_HMC_MMR_IO48_ADDR + 0x110)
+#define ARRIA10_IO48_HMC_MMR_NIOSRESERVE1 (ARRIA10_HMC_MMR_IO48_ADDR + 0x114)
+#define ARRIA10_IO48_HMC_MMR_NIOSRESERVE2 (ARRIA10_HMC_MMR_IO48_ADDR + 0x118)
+
+union dramaddrw_reg {
+ struct {
+ u32 cfg_col_addr_width:5;
+ u32 cfg_row_addr_width:5;
+ u32 cfg_bank_addr_width:4;
+ u32 cfg_bank_group_addr_width:2;
+ u32 cfg_cs_addr_width:3;
+ u32 reserved:13;
+ };
+ u32 word;
+};
+
+union ctrlcfg0_reg {
+ struct {
+ u32 cfg_mem_type:4;
+ u32 cfg_dimm_type:3;
+ u32 cfg_ac_pos:2;
+ u32 cfg_ctrl_burst_len:5;
+ u32 reserved:18; /* Other fields unused */
+ };
+ u32 word;
+};
+
+union ctrlcfg1_reg {
+ struct {
+ u32 cfg_dbc3_burst_len:5;
+ u32 cfg_addr_order:2;
+ u32 cfg_ctrl_enable_ecc:1;
+ u32 reserved:24; /* Other fields unused */
+ };
+ u32 word;
+};
+
+union caltiming0_reg {
+ struct {
+ u32 cfg_act_to_rdwr:6;
+ u32 cfg_act_to_pch:6;
+ u32 cfg_act_to_act:6;
+ u32 cfg_act_to_act_db:6;
+ u32 reserved:8; /* Other fields unused */
+ };
+ u32 word;
+};
+
+union caltiming1_reg {
+ struct {
+ u32 cfg_rd_to_rd:6;
+ u32 cfg_rd_to_rd_dc:6;
+ u32 cfg_rd_to_rd_db:6;
+ u32 cfg_rd_to_wr:6;
+ u32 cfg_rd_to_wr_dc:6;
+ u32 reserved:2;
+ };
+ u32 word;
+};
+
+union caltiming2_reg {
+ struct {
+ u32 cfg_rd_to_wr_db:6;
+ u32 cfg_rd_to_pch:6;
+ u32 cfg_rd_ap_to_valid:6;
+ u32 cfg_wr_to_wr:6;
+ u32 cfg_wr_to_wr_dc:6;
+ u32 reserved:2;
+ };
+ u32 word;
+};
+
+union caltiming3_reg {
+ struct {
+ u32 cfg_wr_to_wr_db:6;
+ u32 cfg_wr_to_rd:6;
+ u32 cfg_wr_to_rd_dc:6;
+ u32 cfg_wr_to_rd_db:6;
+ u32 cfg_wr_to_pch:6;
+ u32 reserved:2;
+ };
+ u32 word;
+};
+
+union caltiming4_reg {
+ struct {
+ u32 cfg_wr_ap_to_valid:6;
+ u32 cfg_pch_to_valid:6;
+ u32 cfg_pch_all_to_valid:6;
+ u32 cfg_arf_to_valid:8;
+ u32 cfg_pdn_to_valid:6;
+ };
+ u32 word;
+};
+
+union caltiming9_reg {
+ struct {
+ u32 cfg_4_act_to_act:8;
+ u32 reserved:24;
+ };
+ u32 word;
+};
+
+#define IRQ_ECC_SERR 34
+#define IRQ_ECC_DERR 32
+
+#define ARRIA10_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE 0x00000001
+
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_SERRPENA 0x00000001
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_DERRPENA 0x00000002
+#define ARRIA10_ECC_HMC_OCP_ERRINTEN_SERRINTEN 0x00000001
+#define ARRIA10_ECC_HMC_OCP_ERRINTEN_DERRINTEN 0x00000002
+#define ARRIA10_ECC_HMC_OCP_INTMOD_INTONCMP 0x00010000
+#define ARRIA10_ECC_HMC_OCP_INTMOD_SERR 0x00000001
+#define ARRIA10_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY 0x00000100
+#define ARRIA10_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST 0x00010000
+#define ARRIA10_ECC_HMC_OCP_ECCCTL_CNT_RST 0x00000100
+#define ARRIA10_ECC_HMC_OCP_ECCCTL_ECC_EN 0x00000000
+#define ARRIA10_ECC_HMC_OCP_ECCCTL2_RMW_EN 0x00000100
+#define ARRIA10_ECC_HMC_OCP_ECCCTL2_AWB_EN 0x00000001
+#define ARRIA10_ECC_HMC_OCP_ERRINTEN_SERR 0x00000001
+#define ARRIA10_ECC_HMC_OCP_ERRINTEN_DERR 0x00000002
+#define ARRIA10_ECC_HMC_OCP_ERRINTEN_HMI 0x00000004
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_SERR 0x00000001
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_DERR 0x00000002
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_HMI 0x00000004
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG 0x00010000
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_ADDRPARFLG 0x00020000
+#define ARRIA10_ECC_HMC_OCP_INTSTAT_DERRBUSFLG 0x00040000
+
+#define ARRIA10_ECC_HMC_OCP_SERRCNTREG_VALUE 8
+
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB 22
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB 0
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB 0
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB 2
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB 6
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB 15
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB 0
+
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_LSB 0
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB 0
+
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB 4
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB 13
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB 4
+
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB 4
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB 6
+#define ARRIA10_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB 6
+
+#define ARRIA10_SDR_FW_MPU_FPGA_EN (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x00)
+#define ARRIA10_SDR_FW_MPU_FPGA_EN_SET (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x04)
+#define ARRIA10_SDR_FW_MPU_FPGA_EN_CLR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x08)
+#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION0ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x10)
+#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION1ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x14)
+#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION2ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x18)
+#define ARRIA10_SDR_FW_MPU_FPGA_MPUREGION3ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x1c)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION0ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x20)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION1ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x24)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION2ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x28)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION3ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x2c)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION0ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x30)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION1ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x34)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION2ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x38)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION3ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x3c)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION0ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x40)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION1ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x44)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION2ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x48)
+#define ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION3ADDR (ARRIA10_SDR_FW_MPU_FPGA_ADDR + 0x4c)
+
+#define ARRIA10_NOC_FW_DDR_MPU_MPUREG0EN BIT(0)
+#define ARRIA10_NOC_FW_DDR_MPU_MPUREG1EN BIT(1)
+#define ARRIA10_NOC_FW_DDR_MPU_MPUREG2EN BIT(2)
+#define ARRIA10_NOC_FW_DDR_MPU_MPUREG3EN BIT(3)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG0EN BIT(4)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG1EN BIT(5)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG2EN BIT(6)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG3EN BIT(7)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG0EN BIT(8)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG1EN BIT(9)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG2EN BIT(10)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG3EN BIT(11)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG0EN BIT(12)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG1EN BIT(13)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG2EN BIT(14)
+#define ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG3EN BIT(15)
+
+#define ARRIA10_NOC_FW_DDR_L3_EN (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x00)
+#define ARRIA10_NOC_FW_DDR_L3_EN_SET (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x04)
+#define ARRIA10_NOC_FW_DDR_L3_EN_CLR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x08)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION0ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x0c)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION1ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x10)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION2ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x14)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION3ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x18)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION4ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x1c)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION5ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x20)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION6ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x24)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREGION7ADDR (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x28)
+#define ARRIA10_NOC_FW_DDR_L3_GLOBAL (ARRIA10_NOC_FW_DDR_L3_DDR_SCR_ADDR + 0x2c)
+
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG0EN BIT(0)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG1EN BIT(1)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG2EN BIT(2)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG3EN BIT(3)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG4EN BIT(4)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG5EN BIT(5)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG6EN BIT(6)
+#define ARRIA10_NOC_FW_DDR_L3_HPSREG7EN BIT(7)
+
+#define ARRIA10_IO48_DRAMTIME_MEM_READ_LATENCY 0x0000003f
+
+int arria10_ddr_calibration_sequence(void);
+
+#endif
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-system-manager.h b/arch/arm/mach-socfpga/include/mach/arria10-system-manager.h
new file mode 100644
index 000000000000..f98cc36c7664
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/arria10-system-manager.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ARRIA10_SYSTEM_MANAGER_H_
+#define _ARRIA10_SYSTEM_MANAGER_H_
+
+#include <mach/arria10-regs.h>
+
+#define ARRIA10_SYSMGR_SILICONID1 (ARRIA10_SYSMGR_ADDR + 0x00)
+#define ARRIA10_SYSMGR_SILICONID2 (ARRIA10_SYSMGR_ADDR + 0x04)
+#define ARRIA10_SYSMGR_WDDBG (ARRIA10_SYSMGR_ADDR + 0x08)
+#define ARRIA10_SYSMGR_BOOTINFO (ARRIA10_SYSMGR_ADDR + 0x0c)
+#define ARRIA10_SYSMGR_MPU_CTRL_L2_ECC (ARRIA10_SYSMGR_ADDR + 0x10)
+#define ARRIA10_SYSMGR_DMA (ARRIA10_SYSMGR_ADDR + 0x20)
+#define ARRIA10_SYSMGR_DMA_PERIPH (ARRIA10_SYSMGR_ADDR + 0x24)
+#define ARRIA10_SYSMGR_SDMMC (ARRIA10_SYSMGR_ADDR + 0x28)
+#define ARRIA10_SYSMGR_SDMMC_L3MASTER (ARRIA10_SYSMGR_ADDR + 0x2c)
+#define ARRIA10_SYSMGR_NAND_BOOTSTRAP (ARRIA10_SYSMGR_ADDR + 0x30)
+#define ARRIA10_SYSMGR_NAND_L3MASTER (ARRIA10_SYSMGR_ADDR + 0x34)
+#define ARRIA10_SYSMGR_USB0_L3MASTER (ARRIA10_SYSMGR_ADDR + 0x38)
+#define ARRIA10_SYSMGR_USB1_L3MASTER (ARRIA10_SYSMGR_ADDR + 0x3c)
+#define ARRIA10_SYSMGR_EMAC_GLOBAL (ARRIA10_SYSMGR_ADDR + 0x40)
+#define ARRIA10_SYSMGR_EMAC0 (ARRIA10_SYSMGR_ADDR + 0x44)
+#define ARRIA10_SYSMGR_EMAC1 (ARRIA10_SYSMGR_ADDR + 0x48)
+#define ARRIA10_SYSMGR_EMAC2 (ARRIA10_SYSMGR_ADDR + 0x4c)
+#define ARRIA10_SYSMGR_FPGAINTF_GLOBAL (ARRIA10_SYSMGR_ADDR + 0x60)
+#define ARRIA10_SYSMGR_FPGAINTF_EN_0 (ARRIA10_SYSMGR_ADDR + 0x64)
+#define ARRIA10_SYSMGR_FPGAINTF_EN_1 (ARRIA10_SYSMGR_ADDR + 0x68)
+#define ARRIA10_SYSMGR_FPGAINTF_EN_2 (ARRIA10_SYSMGR_ADDR + 0x6c)
+#define ARRIA10_SYSMGR_FPGAINTF_EN_3 (ARRIA10_SYSMGR_ADDR + 0x70)
+#define ARRIA10_SYSMGR_NOC_ADDR_REMAP_VALUE (ARRIA10_SYSMGR_ADDR + 0x80)
+#define ARRIA10_SYSMGR_NOC_ADDR_REMAP_SET (ARRIA10_SYSMGR_ADDR + 0x84)
+#define ARRIA10_SYSMGR_NOC_ADDR_REMAP_CLEAR (ARRIA10_SYSMGR_ADDR + 0x88)
+#define ARRIA10_SYSMGR_ECC_INTMASK_VALUE (ARRIA10_SYSMGR_ADDR + 0x90)
+#define ARRIA10_SYSMGR_ECC_INTMASK_SET (ARRIA10_SYSMGR_ADDR + 0x94)
+#define ARRIA10_SYSMGR_ECC_INTMASK_CLR (ARRIA10_SYSMGR_ADDR + 0x98)
+#define ARRIA10_SYSMGR_ECC_INTSTATUS_SERR (ARRIA10_SYSMGR_ADDR + 0x9c)
+#define ARRIA10_SYSMGR_ECC_INTSTATUS_DERR (ARRIA10_SYSMGR_ADDR + 0xa0)
+#define ARRIA10_SYSMGR_MPU_STATUS_L2_ECC (ARRIA10_SYSMGR_ADDR + 0xa4)
+#define ARRIA10_SYSMGR_MPU_CLEAR_L2_ECC (ARRIA10_SYSMGR_ADDR + 0xa8)
+#define ARRIA10_SYSMGR_MPU_STATUS_L1_PARITY (ARRIA10_SYSMGR_ADDR + 0xac)
+#define ARRIA10_SYSMGR_MPU_CLEAR_L1_PARITY (ARRIA10_SYSMGR_ADDR + 0xb0)
+#define ARRIA10_SYSMGR_MPU_SET_L1_PARITY (ARRIA10_SYSMGR_ADDR + 0xb4)
+#define ARRIA10_SYSMGR_NOC_TIMEOUT (ARRIA10_SYSMGR_ADDR + 0xc0)
+#define ARRIA10_SYSMGR_NOC_IDLEREQ_SET (ARRIA10_SYSMGR_ADDR + 0xc4)
+#define ARRIA10_SYSMGR_NOC_IDLEREQ_CLR (ARRIA10_SYSMGR_ADDR + 0xc8)
+#define ARRIA10_SYSMGR_NOC_IDLEREQ_VALUE (ARRIA10_SYSMGR_ADDR + 0xcc)
+#define ARRIA10_SYSMGR_NOC_IDLEACK (ARRIA10_SYSMGR_ADDR + 0xd0)
+#define ARRIA10_SYSMGR_NOC_IDLESTATUS (ARRIA10_SYSMGR_ADDR + 0xd4)
+#define ARRIA10_SYSMGR_FPGA2SOC_CTRL (ARRIA10_SYSMGR_ADDR + 0xd8)
+
+/* pin mux */
+#define ARRIA10_SYSMGR_PINMUXGRP (ARRIA10_SYSMGR_ADDR + 0x400)
+#define ARRIA10_SYSMGR_PINMUXGRP_NANDUSEFPGA (ARRIA10_SYSMGR_PINMUXGRP + 0x2F0)
+#define ARRIA10_SYSMGR_PINMUXGRP_EMAC1USEFPGA (ARRIA10_SYSMGR_PINMUXGRP + 0x2F8)
+#define ARRIA10_SYSMGR_PINMUXGRP_SDMMCUSEFPGA (ARRIA10_SYSMGR_PINMUXGRP + 0x308)
+#define ARRIA10_SYSMGR_PINMUXGRP_EMAC0USEFPGA (ARRIA10_SYSMGR_PINMUXGRP + 0x314)
+#define ARRIA10_SYSMGR_PINMUXGRP_SPIM1USEFPGA (ARRIA10_SYSMGR_PINMUXGRP + 0x330)
+#define ARRIA10_SYSMGR_PINMUXGRP_SPIM0USEFPGA (ARRIA10_SYSMGR_PINMUXGRP + 0x338)
+
+/* bit fields */
+#define ARRIA10_SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
+#define ARRIA10_SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1)
+#define ARRIA10_SYSMGR_ECC_OCRAM_EN BIT(0)
+#define ARRIA10_SYSMGR_ECC_OCRAM_SERR BIT(3)
+#define ARRIA10_SYSMGR_ECC_OCRAM_DERR BIT(4)
+#define ARRIA10_SYSMGR_FPGAINTF_USEFPGA BIT(1)
+#define ARRIA10_SYSMGR_FPGAINTF_SPIM0 BIT(0)
+#define ARRIA10_SYSMGR_FPGAINTF_SPIM1 BIT(1)
+#define ARRIA10_SYSMGR_FPGAINTF_EMAC0 BIT(2)
+#define ARRIA10_SYSMGR_FPGAINTF_EMAC1 BIT(3)
+#define ARRIA10_SYSMGR_FPGAINTF_NAND BIT(4)
+#define ARRIA10_SYSMGR_FPGAINTF_SDMMC BIT(5)
+
+#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
+#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
+#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
+#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_LSB 0
+#define ARRIA10_SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
+
+#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC0 BIT(0)
+#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC0_SW BIT(4)
+#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC1 BIT(8)
+#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC1_SW BIT(12)
+#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC2 BIT(16)
+#define ARRIA10_SYSMGR_FPGAINTF_EN3_EMAC2_SW BIT(20)
+
+#define ARRIA10_SYSMGR_SDMMC_SMPLSEL(smplsel) (((smplsel) & 0x7) << 4)
+#define ARRIA10_SYSMGR_SDMMC_DRVSEL(drvsel) ((drvsel) & 0x7)
+
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
+ ((drvsel << 0) & 0x7) | ((smplsel << 4) & 0x70)
+
+#endif
diff --git a/arch/arm/mach-socfpga/include/mach/generic.h b/arch/arm/mach-socfpga/include/mach/generic.h
index 2a7e0ea499af..4a5b1bbc2843 100644
--- a/arch/arm/mach-socfpga/include/mach/generic.h
+++ b/arch/arm/mach-socfpga/include/mach/generic.h
@@ -5,9 +5,44 @@ struct socfpga_cm_config;
struct socfpga_io_config;
+struct arria10_mainpll_cfg;
+struct arria10_perpll_cfg;
+struct arria10_pinmux_cfg;
+
+void arria10_init(struct arria10_mainpll_cfg *mainpll,
+ struct arria10_perpll_cfg *perpll,
+ struct arria10_pinmux_cfg *pinmux);
+
void socfpga_lowlevel_init(struct socfpga_cm_config *cm_config,
struct socfpga_io_config *io_config);
+#if defined(CONFIG_ARCH_SOCFPGA_CYCLONE5)
+void socfpga_cyclone5_mmc_init(void);
+void socfpga_cyclone5_uart_init(void);
+void socfpga_cyclone5_timer_init(void);
+void socfpga_cyclone5_qspi_init(void);
+#else
+static inline void socfpga_cyclone5_mmc_init(void)
+{
+ return;
+}
+
+static inline void socfpga_cyclone5_uart_init(void)
+{
+ return;
+}
+
+static inline void socfpga_cyclone5_timer_init(void)
+{
+ return;
+}
+
+static inline void socfpga_cyclone5_qspi_init(void)
+{
+ return;
+}
+#endif
+
static inline void __udelay(unsigned us)
{
volatile unsigned int i;
diff --git a/arch/arm/mach-socfpga/xload.c b/arch/arm/mach-socfpga/xload.c
index 5d47bb9d3ea2..ee7d194427ec 100644
--- a/arch/arm/mach-socfpga/xload.c
+++ b/arch/arm/mach-socfpga/xload.c
@@ -1,8 +1,5 @@
-#include <platform_data/cadence_qspi.h>
-#include <platform_data/dw_mmc.h>
#include <bootsource.h>
#include <bootstrap.h>
-#include <platform_data/serial-ns16550.h>
#include <common.h>
#include <malloc.h>
#include <init.h>
@@ -10,7 +7,6 @@
#include <linux/sizes.h>
#include <fs.h>
#include <io.h>
-#include <mci.h>
#include <linux/clkdev.h>
#include <linux/stat.h>
@@ -30,84 +26,6 @@ static struct socfpga_barebox_part default_parts[] = {
};
const struct socfpga_barebox_part *barebox_parts = default_parts;
-enum socfpga_clks {
- timer, mmc, qspi_clk, uart, clk_max
-};
-
-static struct clk *clks[clk_max];
-
-static struct dw_mmc_platform_data mmc_pdata = {
- .bus_width_caps = MMC_CAP_4_BIT_DATA,
- .ciu_div = 3,
-};
-
-static void socfpga_mmc_init(void)
-{
- clks[mmc] = clk_fixed("mmc", 400000000);
- clkdev_add_physbase(clks[mmc], CYCLONE5_SDMMC_ADDRESS, NULL);
- add_generic_device("dw_mmc", 0, NULL, CYCLONE5_SDMMC_ADDRESS, SZ_4K,
- IORESOURCE_MEM, &mmc_pdata);
-}
-
-#if defined(CONFIG_SPI_CADENCE_QUADSPI)
-static struct cadence_qspi_platform_data qspi_pdata = {
- .ext_decoder = 0,
- .fifo_depth = 128,
-};
-
-static __maybe_unused void add_cadence_qspi_device(int id, resource_size_t ctrl,
- resource_size_t data, void *pdata)
-{
- struct resource *res;
-
- res = xzalloc(sizeof(struct resource) * 2);
- res[0].start = ctrl;
- res[0].end = ctrl + 0x100 - 1;
- res[0].flags = IORESOURCE_MEM;
- res[1].start = data;
- res[1].end = data + 0x100 - 1;
- res[1].flags = IORESOURCE_MEM;
-
- add_generic_device_res("cadence_qspi", id, res, 2, pdata);
-}
-
-static __maybe_unused void socfpga_qspi_init(void)
-{
- clks[qspi_clk] = clk_fixed("qspi_clk", 370000000);
- clkdev_add_physbase(clks[qspi_clk], CYCLONE5_QSPI_CTRL_ADDRESS, NULL);
- clkdev_add_physbase(clks[qspi_clk], CYCLONE5_QSPI_DATA_ADDRESS, NULL);
- add_cadence_qspi_device(0, CYCLONE5_QSPI_CTRL_ADDRESS,
- CYCLONE5_QSPI_DATA_ADDRESS, &qspi_pdata);
-}
-#else
-static void socfpga_qspi_init(void)
-{
- return;
-}
-#endif
-
-static struct NS16550_plat uart_pdata = {
- .clock = 100000000,
- .shift = 2,
-};
-
-static void socfpga_uart_init(void)
-{
- clks[uart] = clk_fixed("uart", 100000000);
- clkdev_add_physbase(clks[uart], CYCLONE5_UART0_ADDRESS, NULL);
- clkdev_add_physbase(clks[uart], CYCLONE5_UART1_ADDRESS, NULL);
- add_ns16550_device(0, 0xffc02000, 1024, IORESOURCE_MEM |
- IORESOURCE_MEM_8BIT, &uart_pdata);
-}
-
-static void socfpga_timer_init(void)
-{
- clks[timer] = clk_fixed("timer", 200000000);
- clkdev_add_physbase(clks[timer], CYCLONE5_SMP_TWD_ADDRESS, NULL);
- add_generic_device("smp_twd", 0, NULL, CYCLONE5_SMP_TWD_ADDRESS, 0x100,
- IORESOURCE_MEM, NULL);
-}
-
static __noreturn int socfpga_xload(void)
{
enum bootsource bootsource = bootsource_get();
@@ -116,7 +34,7 @@ static __noreturn int socfpga_xload(void)
switch (bootsource) {
case BOOTSOURCE_MMC:
- socfpga_mmc_init();
+ socfpga_cyclone5_mmc_init();
for (part = barebox_parts; part->mmc_disk; part++) {
buf = bootstrap_read_disk(barebox_parts->mmc_disk, "fat");
@@ -132,8 +50,7 @@ static __noreturn int socfpga_xload(void)
}
break;
case BOOTSOURCE_SPI:
- socfpga_qspi_init();
-
+ socfpga_cyclone5_qspi_init();
for (part = barebox_parts; part->nor_size; part++) {
buf = bootstrap_read_devfs("mtd0", false,
part->nor_offset, part->nor_size, SZ_1M);
@@ -142,7 +59,6 @@ static __noreturn int socfpga_xload(void)
part->nor_offset);
continue;
}
-
break;
}
@@ -167,8 +83,8 @@ static __noreturn int socfpga_xload(void)
static int socfpga_devices_init(void)
{
barebox_set_model("SoCFPGA");
- socfpga_timer_init();
- socfpga_uart_init();
+ socfpga_cyclone5_timer_init();
+ socfpga_cyclone5_uart_init();
barebox_main = socfpga_xload;
diff --git a/images/Makefile.socfpga b/images/Makefile.socfpga
index 21804d93df72..d210a6cc2318 100644
--- a/images/Makefile.socfpga
+++ b/images/Makefile.socfpga
@@ -4,11 +4,19 @@
# %.socfpgaimg - convert into socfpga image
# ----------------------------------------------------------------
+ifdef CONFIG_ARCH_SOCFPGA_ARRIA10
+quiet_cmd_socfpga_image = SOCFPGA-IMG $@
+ cmd_socfpga_image = scripts/socfpga_mkimage -o $@ -b -v1 $<
+
+$(obj)/%.socfpgaimg: $(obj)/% FORCE
+ $(call if_changed,socfpga_image)
+else
quiet_cmd_socfpga_image = SOCFPGA-IMG $@
cmd_socfpga_image = scripts/socfpga_mkimage -o $@ $<
$(obj)/%.socfpgaimg: $(obj)/% FORCE
$(call if_changed,socfpga_image)
+endif
# ----------------------- Cyclone5 based boards ---------------------------
pblx-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += start_socfpga_socdk_xload
diff --git a/scripts/socfpga_mkimage.c b/scripts/socfpga_mkimage.c
index d7fe1b1b69f7..3763044aacab 100644
--- a/scripts/socfpga_mkimage.c
+++ b/scripts/socfpga_mkimage.c
@@ -62,6 +62,7 @@ static uint32_t bb_header[] = {
0x00000000, /* socfpga header */
0x00000000, /* socfpga header */
0x00000000, /* socfpga header */
+ 0x00000000, /* socfpga header */
0xea00006b, /* entry. b 0x200 (offset may be adjusted) */
};
diff --git a/scripts/socfpga_xml_to_config.sh b/scripts/socfpga_xml_to_config.sh
new file mode 100755
index 000000000000..154ddda720f9
--- /dev/null
+++ b/scripts/socfpga_xml_to_config.sh
@@ -0,0 +1,86 @@
+#!/bin/bash
+
+## TODO:
+## - read in mpuclk and nocclk, must be calculated by hand at the moment
+## - read in cfg_dedicated_io_*, must be calculated by hand at the moment
+
+if [ "$#" -lt "2" ]
+then
+ echo "USAGE: $0 <boarddir> <HPS.xml>"
+ exit 1
+fi
+
+dir=$1
+xml=$2
+
+pll_config() {
+ local src
+ local tgt
+ src=$1
+ tgt=$2
+
+ MAINPLL=`grep mainpll "$src" | \
+ sed -e 's/^.*mainpllgrp\.//g' | \
+ sed -e 's/\./_/g' | \
+ sed -e "s/' value/ /g" | \
+ sed -e "s/'/ /g" | \
+ sed -e "s# />#,#g" | \
+ sed -e "s/^/./g"`
+
+ PERPLL=`grep perpll "$src" | \
+ sed -e 's/^.*perpllgrp\.//g' | \
+ sed -e 's/\./_/g' | \
+ sed -e "s/' value/ /g" | \
+ sed -e "s/'/ /g" | \
+ sed -e "s# />#,#g" | \
+ sed -e "s/^/./g"`
+
+ echo "#include <mach/clock-manager-arria10.h>" > $tgt
+ echo >> $tgt
+ echo "static struct arria10_mainpll_cfg mainpll_cfg = {" >> $tgt
+ echo "$MAINPLL" >> $tgt
+ echo "};" >> $tgt
+ echo >> $tgt
+ echo "static struct arria10_perpll_cfg perpll_cfg = {" >> $tgt
+ echo "$PERPLL" >> $tgt
+ echo "};" >> $tgt
+
+ dos2unix $tgt
+}
+
+pinmux_config() {
+ local src
+ local tgt
+ src=$1
+ tgt=$2
+
+ SHARED=`grep pinmux_shared "$src" | \
+ sed -e 's/^.*pinmux_/\./g' | \
+ sed -e "s/\.sel' value='/=/g" | \
+ sed -e "s/' \/>/,/g"`
+
+ DEDICATED=`grep pinmux_dedicated "$src" | \
+ sed -e 's/^.*pinmux_/\./g' | \
+ sed -e "s/\.sel' value='/=/g" | \
+ sed -e "s/' \/>/,/g"`
+
+ FPGA=`grep _fpga_interface_ "$src" | \
+ sed -e 's/^.*pinmux_/\./g' | \
+ sed -e "s/\.sel' value='/=/g" | \
+ sed -e "s/' \/>/,/g"`
+
+ echo "#include <mach/arria10-pinmux.h>" > $tgt
+ echo >> $tgt
+ echo "static struct arria10_pinmux_cfg pinmux = {" >> $tgt
+ echo "$SHARED" >> $tgt
+ echo "$DEDICATED" >> $tgt
+ echo "$FPGA" >> $tgt
+ echo "};" >> $tgt
+ echo >> $tgt
+
+ dos2unix $tgt
+}
+
+pll_config $xml $dir/pll-config-arria10.c
+
+pinmux_config $xml $dir/pinmux-config-arria10.c
--
2.11.0
_______________________________________________
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 5/7] clk: socfpga: add arria10 clk drivers
2017-04-03 10:55 [PATCH 0/7] SoCFPGA: add support for Arria10 Steffen Trumtrar
` (3 preceding siblings ...)
2017-04-03 10:55 ` [PATCH 4/7] ARM: socfpga: add arria10 support Steffen Trumtrar
@ 2017-04-03 10:55 ` Steffen Trumtrar
2017-04-03 10:55 ` [PATCH 6/7] ARM: socfpga: add support for reflex achilles board Steffen Trumtrar
` (2 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Steffen Trumtrar @ 2017-04-03 10:55 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
drivers/clk/socfpga/Makefile | 2 +
drivers/clk/socfpga/clk-gate-a10.c | 197 +++++++++++++++++++++++++++++++++++
drivers/clk/socfpga/clk-periph-a10.c | 130 +++++++++++++++++++++++
drivers/clk/socfpga/clk-pll-a10.c | 143 +++++++++++++++++++++++++
drivers/clk/socfpga/clk.c | 11 +-
drivers/clk/socfpga/clk.h | 90 ++++++++++++++++
6 files changed, 572 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/socfpga/clk-gate-a10.c
create mode 100644 drivers/clk/socfpga/clk-periph-a10.c
create mode 100644 drivers/clk/socfpga/clk-pll-a10.c
create mode 100644 drivers/clk/socfpga/clk.h
diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
index fc216adb744e..341e6433e560 100644
--- a/drivers/clk/socfpga/Makefile
+++ b/drivers/clk/socfpga/Makefile
@@ -1 +1,3 @@
obj-y += clk.o
+
+obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += clk-gate-a10.o clk-periph-a10.o clk-pll-a10.o
diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c
new file mode 100644
index 000000000000..07f6026c2e8d
--- /dev/null
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2015 Altera Corporation. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <io.h>
+#include <malloc.h>
+#include <regmap.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <mach/arria10-regs.h>
+#include <mach/arria10-system-manager.h>
+
+#include "clk.h"
+
+#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, clk)
+
+/* SDMMC Group for System Manager defines */
+#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x28
+
+static unsigned long socfpga_gate_clk_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(clk);
+ u32 div = 1, val;
+
+ if (socfpgaclk->fixed_div)
+ div = socfpgaclk->fixed_div;
+ else if (socfpgaclk->div_reg) {
+ val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
+ val &= GENMASK(socfpgaclk->width - 1, 0);
+ div = (1 << val);
+ }
+
+ return parent_rate / div;
+}
+
+static int socfpga_clk_prepare(struct clk *clk)
+{
+ struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(clk);
+ int i;
+ u32 hs_timing;
+ u32 clk_phase[2];
+
+ if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
+ for (i = 0; i < ARRAY_SIZE(clk_phase); i++) {
+ switch (socfpgaclk->clk_phase[i]) {
+ case 0:
+ clk_phase[i] = 0;
+ break;
+ case 45:
+ clk_phase[i] = 1;
+ break;
+ case 90:
+ clk_phase[i] = 2;
+ break;
+ case 135:
+ clk_phase[i] = 3;
+ break;
+ case 180:
+ clk_phase[i] = 4;
+ break;
+ case 225:
+ clk_phase[i] = 5;
+ break;
+ case 270:
+ clk_phase[i] = 6;
+ break;
+ case 315:
+ clk_phase[i] = 7;
+ break;
+ default:
+ clk_phase[i] = 0;
+ break;
+ }
+ }
+
+ hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
+ writel(hs_timing, ARRIA10_SYSMGR_SDMMC);
+ }
+ return 0;
+}
+
+static int clk_socfpga_enable(struct clk *clk)
+{
+ struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(clk);
+ u32 val;
+
+ socfpga_clk_prepare(clk);
+
+ val = readl(socfpga_clk->reg);
+ val |= 1 << socfpga_clk->bit_idx;
+ writel(val, socfpga_clk->reg);
+
+ return 0;
+}
+
+static void clk_socfpga_disable(struct clk *clk)
+{
+ struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(clk);
+ u32 val;
+
+ val = readl(socfpga_clk->reg);
+ val &= ~(1 << socfpga_clk->shift);
+ writel(val, socfpga_clk->reg);
+}
+
+static struct clk_ops gateclk_ops = {
+ .recalc_rate = socfpga_gate_clk_recalc_rate,
+};
+
+static struct clk *__socfpga_gate_init(struct device_node *node,
+ const struct clk_ops *ops)
+{
+ u32 clk_gate[2];
+ u32 div_reg[3];
+ u32 clk_phase[2];
+ u32 fixed_div;
+ struct socfpga_gate_clk *socfpga_clk;
+ const char *clk_name = node->name;
+ int rc;
+ int i;
+
+ socfpga_clk = xzalloc(sizeof(*socfpga_clk));
+
+ rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
+ if (rc)
+ clk_gate[0] = 0;
+
+ if (clk_gate[0]) {
+ socfpga_clk->reg = clk_mgr_base_addr + clk_gate[0];
+ socfpga_clk->bit_idx = clk_gate[1];
+
+ gateclk_ops.enable = clk_socfpga_enable;
+ gateclk_ops.disable = clk_socfpga_disable;
+ }
+
+ rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
+ if (rc)
+ socfpga_clk->fixed_div = 0;
+ else
+ socfpga_clk->fixed_div = fixed_div;
+
+ rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
+ if (!rc) {
+ socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
+ socfpga_clk->shift = div_reg[1];
+ socfpga_clk->width = div_reg[2];
+ } else {
+ socfpga_clk->div_reg = NULL;
+ }
+
+ rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
+ if (!rc) {
+ socfpga_clk->clk_phase[0] = clk_phase[0];
+ socfpga_clk->clk_phase[1] = clk_phase[1];
+ }
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ socfpga_clk->clk.name = xstrdup(clk_name);
+ socfpga_clk->clk.ops = ops;
+
+ for (i = 0; i < SOCFPGA_MAX_PARENTS; i++) {
+ socfpga_clk->parent_names[i] = of_clk_get_parent_name(node, i);
+ if (!socfpga_clk->parent_names[i])
+ break;
+ }
+
+ socfpga_clk->clk.num_parents = i;
+ socfpga_clk->clk.parent_names = socfpga_clk->parent_names;
+
+ rc = clk_register(&socfpga_clk->clk);
+ if (rc) {
+ free(socfpga_clk);
+ return ERR_PTR(rc);
+ }
+
+ return &socfpga_clk->clk;
+}
+
+struct clk *socfpga_a10_gate_init(struct device_node *node)
+{
+ return __socfpga_gate_init(node, &gateclk_ops);
+}
diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c
new file mode 100644
index 000000000000..9dd7fc9c2552
--- /dev/null
+++ b/drivers/clk/socfpga/clk-periph-a10.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2015 Altera Corporation. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <io.h>
+#include <malloc.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+
+#include "clk.h"
+
+#define CLK_MGR_FREE_SHIFT 16
+#define CLK_MGR_FREE_MASK 0x7
+
+#define SOCFPGA_MPU_FREE_CLK "mpu_free_clk"
+#define SOCFPGA_NOC_FREE_CLK "noc_free_clk"
+#define SOCFPGA_SDMMC_FREE_CLK "sdmmc_free_clk"
+#define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, clk)
+
+static unsigned long clk_periclk_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(clk);
+ u32 div;
+
+ if (socfpgaclk->fixed_div) {
+ div = socfpgaclk->fixed_div;
+ } else if (socfpgaclk->div_reg) {
+ div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
+ div &= GENMASK(socfpgaclk->width - 1, 0);
+ div += 1;
+ } else {
+ div = ((readl(socfpgaclk->reg) & 0x7ff) + 1);
+ }
+
+ return parent_rate / div;
+}
+
+static int clk_periclk_get_parent(struct clk *clk)
+{
+ struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(clk);
+ u32 clk_src;
+
+ clk_src = readl(socfpgaclk->reg);
+ if (streq(clk->name, SOCFPGA_MPU_FREE_CLK) ||
+ streq(clk->name, SOCFPGA_NOC_FREE_CLK) ||
+ streq(clk->name, SOCFPGA_SDMMC_FREE_CLK))
+ return (clk_src >> CLK_MGR_FREE_SHIFT) &
+ CLK_MGR_FREE_MASK;
+ else
+ return 0;
+}
+
+static const struct clk_ops periclk_ops = {
+ .recalc_rate = clk_periclk_recalc_rate,
+ .get_parent = clk_periclk_get_parent,
+};
+
+static struct clk *__socfpga_periph_init(struct device_node *node,
+ const struct clk_ops *ops)
+{
+ u32 reg;
+ struct socfpga_periph_clk *periph_clk;
+ const char *clk_name = node->name;
+ int rc;
+ u32 fixed_div;
+ u32 div_reg[3];
+ int i;
+
+ of_property_read_u32(node, "reg", ®);
+
+ periph_clk = xzalloc(sizeof(*periph_clk));
+
+ periph_clk->reg = clk_mgr_base_addr + reg;
+
+ rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
+ if (!rc) {
+ periph_clk->div_reg = clk_mgr_base_addr + div_reg[0];
+ periph_clk->shift = div_reg[1];
+ periph_clk->width = div_reg[2];
+ } else {
+ periph_clk->div_reg = NULL;
+ }
+
+ rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
+ if (rc)
+ periph_clk->fixed_div = 0;
+ else
+ periph_clk->fixed_div = fixed_div;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ for (i = 0; i < SOCFPGA_MAX_PARENTS; i++) {
+ periph_clk->parent_names[i] = of_clk_get_parent_name(node, i);
+ if (!periph_clk->parent_names[i])
+ break;
+ }
+
+ periph_clk->clk.num_parents = i;
+ periph_clk->clk.parent_names = periph_clk->parent_names;
+
+ periph_clk->clk.name = xstrdup(clk_name);
+ periph_clk->clk.ops = ops;
+
+ rc = clk_register(&periph_clk->clk);
+ if (rc) {
+ free(periph_clk);
+ return ERR_PTR(rc);
+ }
+
+ return &periph_clk->clk;
+}
+
+struct clk *socfpga_a10_periph_init(struct device_node *node)
+{
+ return __socfpga_periph_init(node, &periclk_ops);
+}
diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c
new file mode 100644
index 000000000000..4dae3e537bc2
--- /dev/null
+++ b/drivers/clk/socfpga/clk-pll-a10.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2015 Altera Corporation. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <common.h>
+#include <io.h>
+#include <malloc.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <asm-generic/div64.h>
+
+#include "clk.h"
+
+/* Clock Manager offsets */
+#define CLK_MGR_PLL_CLK_SRC_SHIFT 8
+#define CLK_MGR_PLL_CLK_SRC_MASK 0x3
+
+/* Clock bypass bits */
+#define SOCFPGA_PLL_BG_PWRDWN 0
+#define SOCFPGA_PLL_PWR_DOWN 1
+#define SOCFPGA_PLL_EXT_ENA 2
+#define SOCFPGA_PLL_DIVF_MASK 0x00001FFF
+#define SOCFPGA_PLL_DIVF_SHIFT 0
+#define SOCFPGA_PLL_DIVQ_MASK 0x003F0000
+#define SOCFPGA_PLL_DIVQ_SHIFT 16
+#define SOCFGPA_MAX_PARENTS 5
+
+#define SOCFPGA_MAIN_PLL_CLK "main_pll"
+#define SOCFPGA_PERIP_PLL_CLK "periph_pll"
+
+#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, clk)
+
+static unsigned long clk_pll_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct socfpga_pll *socfpgaclk = to_socfpga_clk(clk);
+ unsigned long divf, divq, reg;
+ unsigned long long vco_freq;
+
+ /* read VCO1 reg for numerator and denominator */
+ reg = readl(socfpgaclk->reg + 0x4);
+ divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
+ divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
+ vco_freq = (unsigned long long)parent_rate * (divf + 1);
+ do_div(vco_freq, (1 + divq));
+ return (unsigned long)vco_freq;
+}
+
+static int clk_pll_get_parent(struct clk *clk)
+{
+ struct socfpga_pll *socfpgaclk = to_socfpga_clk(clk);
+ u32 pll_src;
+
+ pll_src = readl(socfpgaclk->reg);
+
+ return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
+ CLK_MGR_PLL_CLK_SRC_MASK;
+}
+
+static int clk_socfpga_enable(struct clk *clk)
+{
+ struct socfpga_pll *socfpga_clk = to_socfpga_clk(clk);
+ u32 val;
+
+ val = readl(socfpga_clk->reg);
+ val |= 1 << socfpga_clk->bit_idx;
+ writel(val, socfpga_clk->reg);
+
+ return 0;
+}
+
+static void clk_socfpga_disable(struct clk *clk)
+{
+ struct socfpga_pll *socfpga_clk = to_socfpga_clk(clk);
+ u32 val;
+
+ val = readl(socfpga_clk->reg);
+ val &= ~(1 << socfpga_clk->bit_idx);
+ writel(val, socfpga_clk->reg);
+}
+
+static struct clk_ops clk_pll_ops = {
+ .recalc_rate = clk_pll_recalc_rate,
+ .get_parent = clk_pll_get_parent,
+};
+
+static struct clk *__socfpga_pll_init(struct device_node *node,
+ const struct clk_ops *ops)
+{
+ u32 reg;
+ struct socfpga_pll *pll_clk;
+ const char *clk_name = node->name;
+ int rc;
+ int i;
+
+ of_property_read_u32(node, "reg", ®);
+
+ pll_clk = xzalloc(sizeof(*pll_clk));
+
+ pll_clk->reg = clk_mgr_base_addr + reg;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ pll_clk->clk.name = xstrdup(clk_name);
+ pll_clk->clk.ops = ops;
+
+ for (i = 0; i < SOCFPGA_MAX_PARENTS; i++) {
+ pll_clk->parent_names[i] = of_clk_get_parent_name(node, i);
+ if (!pll_clk->parent_names[i])
+ break;
+ }
+
+ pll_clk->bit_idx = SOCFPGA_PLL_EXT_ENA;
+ pll_clk->clk.num_parents = i;
+ pll_clk->clk.parent_names = pll_clk->parent_names;
+
+ clk_pll_ops.enable = clk_socfpga_enable;
+ clk_pll_ops.disable = clk_socfpga_disable;
+
+ rc = clk_register(&pll_clk->clk);
+ if (rc) {
+ free(pll_clk);
+ return NULL;
+ }
+
+ return &pll_clk->clk;
+}
+
+struct clk *socfpga_a10_pll_init(struct device_node *node)
+{
+ return __socfpga_pll_init(node, &clk_pll_ops);
+}
diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
index 6af0632cafc2..ade608ffe314 100644
--- a/drivers/clk/socfpga/clk.c
+++ b/drivers/clk/socfpga/clk.c
@@ -12,6 +12,7 @@
*/
#include <common.h>
+#include <debug_ll.h>
#include <init.h>
#include <driver.h>
#include <linux/clk.h>
@@ -20,6 +21,8 @@
#include <linux/clkdev.h>
#include <linux/err.h>
+#include "clk.h"
+
/* Clock Manager offsets */
#define CLKMGR_CTRL 0x0
#define CLKMGR_BYPASS 0x4
@@ -52,7 +55,7 @@
#define div_mask(width) ((1 << (width)) - 1)
#define streq(a, b) (strcmp((a), (b)) == 0)
-static void __iomem *clk_mgr_base_addr;
+void __iomem *clk_mgr_base_addr;
struct clk_pll {
struct clk clk;
@@ -385,6 +388,12 @@ static void socfpga_register_clocks(struct device_d *dev, struct device_node *no
clk = socfpga_periph_clk(node);
else if (of_device_is_compatible(node, "altr,socfpga-gate-clk"))
clk = socfpga_gate_clk(node);
+ else if (of_device_is_compatible(node, "altr,socfpga-a10-pll-clock"))
+ clk = socfpga_a10_pll_init(node);
+ else if (of_device_is_compatible(node, "altr,socfpga-a10-perip-clk"))
+ clk = socfpga_a10_periph_init(node);
+ else if (of_device_is_compatible(node, "altr,socfpga-a10-gate-clk"))
+ clk = socfpga_a10_gate_init(node);
else
return;
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
new file mode 100644
index 000000000000..6d6c28344df4
--- /dev/null
+++ b/drivers/clk/socfpga/clk.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * based on drivers/clk/tegra/clk.h
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#ifndef __SOCFPGA_CLK_H
+#define __SOCFPGA_CLK_H
+
+#include <linux/clk.h>
+
+/* Clock Manager offsets */
+#define CLKMGR_CTRL 0x0
+#define CLKMGR_BYPASS 0x4
+#define CLKMGR_DBCTRL 0x10
+#define CLKMGR_L4SRC 0x70
+#define CLKMGR_PERPLL_SRC 0xAC
+
+#define SOCFPGA_MAX_PARENTS 5
+
+#define streq(a, b) (strcmp((a), (b)) == 0)
+
+extern void __iomem *clk_mgr_base_addr;
+
+void __init socfpga_pll_init(struct device_node *node);
+void __init socfpga_periph_init(struct device_node *node);
+void __init socfpga_gate_init(struct device_node *node);
+
+#ifdef CONFIG_ARCH_SOCFPGA_ARRIA10
+struct clk *socfpga_a10_pll_init(struct device_node *node);
+struct clk *socfpga_a10_periph_init(struct device_node *node);
+struct clk *socfpga_a10_gate_init(struct device_node *node);
+#else
+struct clk *socfpga_a10_pll_init(struct device_node *node)
+{
+ return ERR_PTR(-ENOSYS);
+}
+struct clk *socfpga_a10_periph_init(struct device_node *node)
+{
+ return ERR_PTR(-ENOSYS);
+}
+struct clk *socfpga_a10_gate_init(struct device_node *node)
+{
+ return ERR_PTR(-ENOSYS);
+}
+#endif
+
+struct socfpga_pll {
+ struct clk clk;
+ void __iomem *reg;
+ u32 bit_idx;
+ const char *parent_names[SOCFPGA_MAX_PARENTS];
+};
+
+struct socfpga_gate_clk {
+ struct clk clk;
+ char *parent_name;
+ u32 fixed_div;
+ void __iomem *div_reg;
+ struct regmap *sys_mgr_base_addr;
+ u32 width; /* only valid if div_reg != 0 */
+ u32 shift; /* only valid if div_reg != 0 */
+ u32 bit_idx;
+ void __iomem *reg;
+ u32 clk_phase[2];
+ const char *parent_names[SOCFPGA_MAX_PARENTS];
+};
+
+struct socfpga_periph_clk {
+ struct clk clk;
+ void __iomem *reg;
+ char *parent_name;
+ u32 fixed_div;
+ void __iomem *div_reg;
+ u32 width; /* only valid if div_reg != 0 */
+ u32 shift; /* only valid if div_reg != 0 */
+ const char *parent_names[SOCFPGA_MAX_PARENTS];
+};
+
+#endif /* SOCFPGA_CLK_H */
--
2.11.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 6/7] ARM: socfpga: add support for reflex achilles board
2017-04-03 10:55 [PATCH 0/7] SoCFPGA: add support for Arria10 Steffen Trumtrar
` (4 preceding siblings ...)
2017-04-03 10:55 ` [PATCH 5/7] clk: socfpga: add arria10 clk drivers Steffen Trumtrar
@ 2017-04-03 10:55 ` Steffen Trumtrar
2017-04-03 10:55 ` [PATCH 7/7] ARM: socfpga: add arria10 defconfig Steffen Trumtrar
2017-04-04 17:52 ` [PATCH 0/7] SoCFPGA: add support for Arria10 Trent Piepho
7 siblings, 0 replies; 12+ messages in thread
From: Steffen Trumtrar @ 2017-04-03 10:55 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/boards/Makefile | 1 +
arch/arm/boards/reflex-achilles/Makefile | 2 +
arch/arm/boards/reflex-achilles/hps.xml | 351 +++++++++++++++++++++
arch/arm/boards/reflex-achilles/lowlevel.c | 48 +++
.../boards/reflex-achilles/pinmux-config-arria10.c | 105 ++++++
.../boards/reflex-achilles/pll-config-arria10.c | 55 ++++
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_arria10_achilles.dts | 124 ++++++++
arch/arm/mach-socfpga/Kconfig | 5 +
images/Makefile.socfpga | 4 +
10 files changed, 696 insertions(+)
create mode 100644 arch/arm/boards/reflex-achilles/Makefile
create mode 100644 arch/arm/boards/reflex-achilles/hps.xml
create mode 100644 arch/arm/boards/reflex-achilles/lowlevel.c
create mode 100644 arch/arm/boards/reflex-achilles/pinmux-config-arria10.c
create mode 100644 arch/arm/boards/reflex-achilles/pll-config-arria10.c
create mode 100644 arch/arm/dts/socfpga_arria10_achilles.dts
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 250ccb88896f..bcd94a05694e 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -110,6 +110,7 @@ obj-$(CONFIG_MACH_SAMA5D4EK) += sama5d4ek/
obj-$(CONFIG_MACH_SCB9328) += scb9328/
obj-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += altera-socdk/
obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/
+obj-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += reflex-achilles/
obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += terasic-de0-nano-soc/
obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/
obj-$(CONFIG_MACH_SOLIDRUN_CUBOX) += solidrun-cubox/
diff --git a/arch/arm/boards/reflex-achilles/Makefile b/arch/arm/boards/reflex-achilles/Makefile
new file mode 100644
index 000000000000..6b4214115300
--- /dev/null
+++ b/arch/arm/boards/reflex-achilles/Makefile
@@ -0,0 +1,2 @@
+obj-y += lowlevel.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/reflex-achilles/hps.xml b/arch/arm/boards/reflex-achilles/hps.xml
new file mode 100644
index 000000000000..d719ca00587c
--- /dev/null
+++ b/arch/arm/boards/reflex-achilles/hps.xml
@@ -0,0 +1,351 @@
+<hps>
+ <system>
+ <config name='VERSION' value='16.1' />
+ <config name='DEVICE_FAMILY' value='Arria 10' />
+ <config name='TIME_AND_DATE' value='Tuesday December, 06, 2016 - 03:45:21 PM CET' />
+ <config name='DMA_Enable' value='No No No No No No No No' />
+ <config name='eosc1_clk_hz' value='25000000.0' />
+ <config name='emac0_clk_hz' value='250000000' />
+ <config name='emac1_clk_hz' value='250000000' />
+ <config name='emac2_clk_hz' value='250000000' />
+ <config name='sdmmc_clk_hz' value='200000000' />
+ <config name='l3_main_free_clk_hz' value='400000000' />
+ <config name='h2f_user0_clk_hz' value='100000000' />
+ <config name='h2f_user1_clk_hz' value='100000000' />
+ <config name='tpiu_clk_hz' value='100000000' />
+ <config name='f2h_free_clk_hz' value='200000000' />
+ <config name='cb_intosc_ls_clk_hz' value='60000000' />
+ </system>
+ <fpga_interfaces>
+ <config name='F2H_AXI_SLAVE' used='false' />
+ <config name='H2F_AXI_MASTER' used='false' />
+ <config name='LWH2F_AXI_MASTER' used='true' />
+ <config name='F2SDRAM0_AXI_SLAVE' used='false' />
+ <config name='F2SDRAM1_AXI_SLAVE' used='false' />
+ <config name='F2SDRAM2_AXI_SLAVE' used='false' />
+ </fpga_interfaces>
+ <peripherals>
+ <peripheral name='rgmii0' used='false' />
+ <peripheral name='rgmii1' used='true' />
+ <peripheral name='rgmii2' used='true' />
+ <peripheral name='nand' used='false' />
+ <peripheral name='qspi' used='false'>
+ <config name='CONFIG_HPS_QSPI_CS2' value='0' />
+ <config name='CONFIG_HPS_QSPI_CS3' value='0' />
+ <config name='CONFIG_HPS_QSPI_CS4' value='0' />
+ <config name='CONFIG_HPS_QSPI_CS0' value='0' />
+ <config name='CONFIG_HPS_QSPI_CS1' value='0' />
+ </peripheral>
+ <peripheral name='sdmmc' used='true'>
+ <config name='CONFIG_HPS_SDMMC_BUSWIDTH' value='8' />
+ </peripheral>
+ <peripheral name='usb0' used='false' />
+ <peripheral name='usb1' used='true' />
+ <peripheral name='spim0' used='true' />
+ <peripheral name='spim1' used='false' />
+ <peripheral name='spis0' used='false' />
+ <peripheral name='spis1' used='false' />
+ <peripheral name='uart0' used='true'>
+ <config name='CONFIG_HPS_UART0_TX' value='1' />
+ <config name='CONFIG_HPS_UART0_RTS' value='1' />
+ <config name='CONFIG_HPS_UART0_CTS' value='1' />
+ <config name='CONFIG_HPS_UART0_RX' value='1' />
+ </peripheral>
+ <peripheral name='uart1' used='false'>
+ <config name='CONFIG_HPS_UART1_TX' value='0' />
+ <config name='CONFIG_HPS_UART1_RTS' value='0' />
+ <config name='CONFIG_HPS_UART1_CTS' value='0' />
+ <config name='CONFIG_HPS_UART1_RX' value='0' />
+ </peripheral>
+ <peripheral name='i2c0' used='true' />
+ <peripheral name='i2c1' used='false' />
+ <peripheral name='i2cemac0' used='false' />
+ <peripheral name='i2cemac1' used='false' />
+ <peripheral name='i2cemac2' used='false' />
+ <peripheral name='trace' used='false' />
+ <peripheral name='pll_clock_out' used='false' />
+ </peripherals>
+ <csr>
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q4_12.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q4_11.sel' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_4.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q4_10.sel' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_5.sel' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_6.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q4_9.sel' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_7.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q4_8.sel' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_8.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q4_6.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q4_7.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q4_5.sel' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_9.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q4_4.sel' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_10.sel' value='10' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q4_3.sel' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_11.sel' value='10' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q4_2.sel' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_12.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q4_1.sel' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_13.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q3_12.sel' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_14.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q3_11.sel' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_15.sel' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_16.sel' value='15' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.pinmux_dedicated_io_17.sel' value='15' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q3_10.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q3_8.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q3_9.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q3_7.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q3_6.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q3_5.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q3_4.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q3_3.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q3_2.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q3_1.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q2_12.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q2_10.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q2_11.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q2_9.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q2_8.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q2_7.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q2_6.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q2_5.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q2_4.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q2_3.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q2_2.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q2_1.sel' value='8' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q1_12.sel' value='10' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q1_11.sel' value='10' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q1_10.sel' value='1' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q1_9.sel' value='1' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q1_8.sel' value='1' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q1_7.sel' value='1' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q1_6.sel' value='0' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q1_5.sel' value='0' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q1_4.sel' value='13' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q1_3.sel' value='13' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q1_2.sel' value='13' />
+ <config name='i_io48_pin_mux_shared_3v_io_grp.pinmux_shared_io_q1_1.sel' value='13' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_rgmii0_usefpga.sel' value='0' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_rgmii1_usefpga.sel' value='0' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_rgmii2_usefpga.sel' value='0' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_nand_usefpga.sel' value='0' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_qspi_usefpga.sel' value='0' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_sdmmc_usefpga.sel' value='0' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_usb0_usefpga.sel' value='0' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_usb1_usefpga.sel' value='0' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_spim0_usefpga.sel' value='1' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_spim1_usefpga.sel' value='0' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_spis0_usefpga.sel' value='0' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_spis1_usefpga.sel' value='0' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_uart0_usefpga.sel' value='0' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_uart1_usefpga.sel' value='0' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_i2c0_usefpga.sel' value='0' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_i2c1_usefpga.sel' value='0' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_i2cemac0_usefpga.sel' value='0' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_i2cemac1_usefpga.sel' value='0' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_i2cemac2_usefpga.sel' value='0' />
+ <config name='i_io48_pin_mux_fpga_interface_grp.pinmux_pll_clock_out_usefpga.sel' value='0' />
+ <config name='i_clk_mgr_alteragrp.nocclk.maincnt' value='3' />
+ <config name='i_clk_mgr_perpllgrp.vco1.denom' value='1' />
+ <config name='i_clk_mgr_mainpllgrp.cntr8clk.cnt' value='900' />
+ <config name='i_clk_mgr_perpllgrp.emacctl.emac2sel' value='0' />
+ <config name='i_clk_mgr_mainpllgrp.cntr9clk.cnt' value='900' />
+ <config name='i_clk_mgr_mainpllgrp.cntr6clk.cnt' value='7' />
+ <config name='i_clk_mgr_alteragrp.mpuclk.pericnt' value='900' />
+ <config name='i_clk_mgr_alteragrp.mpuclk.maincnt' value='1' />
+ <config name='i_clk_mgr_perpllgrp.cntr3clk.cnt' value='900' />
+ <config name='i_clk_mgr_perpllgrp.cntr6clk.src' value='0' />
+ <config name='i_clk_mgr_mainpllgrp.cntr2clk.cnt' value='900' />
+ <config name='i_clk_mgr_mainpllgrp.nocdiv.l4mpclk' value='2' />
+ <config name='i_clk_mgr_perpllgrp.cntr4clk.src' value='1' />
+ <config name='i_clk_mgr_perpllgrp.emacctl.emac0sel' value='0' />
+ <config name='i_clk_mgr_mainpllgrp.nocclk.cnt' value='0' />
+ <config name='i_clk_mgr_mainpllgrp.nocdiv.l4spclk' value='2' />
+ <config name='i_clk_mgr_perpllgrp.gpiodiv.gpiodbclk' value='32000' />
+ <config name='i_clk_mgr_perpllgrp.cntr3clk.src' value='1' />
+ <config name='i_clk_mgr_perpllgrp.cntr8clk.src' value='0' />
+ <config name='i_clk_mgr_mainpllgrp.vco1.numer' value='127' />
+ <config name='i_clk_mgr_perpllgrp.cntr8clk.cnt' value='900' />
+ <config name='i_clk_mgr_mainpllgrp.nocdiv.csatclk' value='2' />
+ <config name='i_clk_mgr_mainpllgrp.nocdiv.cspdbgclk' value='0' />
+ <config name='i_clk_mgr_mainpllgrp.mpuclk.cnt' value='0' />
+ <config name='i_clk_mgr_perpllgrp.cntr5clk.cnt' value='374' />
+ <config name='i_clk_mgr_perpllgrp.cntr6clk.cnt' value='900' />
+ <config name='i_clk_mgr_perpllgrp.cntr5clk.src' value='1' />
+ <config name='i_clk_mgr_perpllgrp.cntr2clk.src' value='1' />
+ <config name='i_clk_mgr_mainpllgrp.nocdiv.cstraceclk' value='0' />
+ <config name='i_clk_mgr_mainpllgrp.nocdiv.l4mainclk' value='2' />
+ <config name='i_clk_mgr_clkmgr.testioctrl.periclksel' value='8' />
+ <config name='i_clk_mgr_mainpllgrp.cntr7clk.src' value='0' />
+ <config name='i_clk_mgr_mainpllgrp.cntr7clk.cnt' value='900' />
+ <config name='i_clk_mgr_mainpllgrp.mpuclk.src' value='0' />
+ <config name='i_clk_mgr_mainpllgrp.cntr5clk.cnt' value='900' />
+ <config name='i_clk_mgr_mainpllgrp.vco1.denom' value='1' />
+ <config name='i_clk_mgr_mainpllgrp.cntr9clk.src' value='0' />
+ <config name='i_clk_mgr_clkmgr.testioctrl.debugclksel' value='16' />
+ <config name='i_clk_mgr_mainpllgrp.nocclk.src' value='0' />
+ <config name='i_clk_mgr_perpllgrp.cntr2clk.cnt' value='5' />
+ <config name='i_clk_mgr_perpllgrp.emacctl.emac1sel' value='0' />
+ <config name='i_clk_mgr_mainpllgrp.cntr3clk.cnt' value='900' />
+ <config name='i_clk_mgr_perpllgrp.vco0.psrc' value='0' />
+ <config name='i_clk_mgr_mainpllgrp.cntr4clk.cnt' value='900' />
+ <config name='i_clk_mgr_mainpllgrp.cntr15clk.cnt' value='900' />
+ <config name='i_clk_mgr_perpllgrp.vco1.numer' value='119' />
+ <config name='i_clk_mgr_clkmgr.testioctrl.mainclksel' value='8' />
+ <config name='i_clk_mgr_mainpllgrp.vco0.psrc' value='0' />
+ <config name='i_clk_mgr_alteragrp.nocclk.pericnt' value='900' />
+ <config name='i_clk_mgr_perpllgrp.cntr4clk.cnt' value='14' />
+ <config name='i_clk_mgr_perpllgrp.cntr7clk.cnt' value='900' />
+ <config name='i_clk_mgr_perpllgrp.cntr9clk.cnt' value='900' />
+ </csr>
+ <csr />
+ <!-- This section was added by Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition -->
+ <!-- Generated on Tue Dec 13 10:34:43 2016 -->
+ <csr>
+ <!-- OSC_CLK_1_HPS -->
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.rtrim' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.input_buf_en' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.wk_pu_en' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.pu_slw_rt' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.pd_slw_rt' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.pu_drv_strg' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_1.pd_drv_strg' value='10' />
+ <!-- nPOR_HPS -->
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.rtrim' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.input_buf_en' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.wk_pu_en' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.pu_slw_rt' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.pd_slw_rt' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.pu_drv_strg' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_2.pd_drv_strg' value='10' />
+ <!-- nRST_HPS -->
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.rtrim' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.input_buf_en' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.wk_pu_en' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.pu_slw_rt' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.pd_slw_rt' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.pu_drv_strg' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_3.pd_drv_strg' value='10' />
+ <!-- hps_io_phery_sdmmc_D0, HPS_DEDICATED_4, input, weak pull up disable, is output, Fast Slew, 1_8 -->
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_4.rtrim' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_4.input_buf_en' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_4.wk_pu_en' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_4.pu_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_4.pd_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_4.pu_drv_strg' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_4.pd_drv_strg' value='10' />
+ <!-- hps_io_phery_sdmmc_CMD, HPS_DEDICATED_5, input, weak pull up disable, is output, Fast Slew, 1_8 -->
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_5.rtrim' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_5.input_buf_en' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_5.wk_pu_en' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_5.pu_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_5.pd_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_5.pu_drv_strg' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_5.pd_drv_strg' value='10' />
+ <!-- hps_io_phery_sdmmc_CCLK, BOOTSEL2/HPS_DEDICATED_6, NOT input, weak pull up disable, is output, Fast Slew, 1_8 -->
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_6.rtrim' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_6.input_buf_en' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_6.wk_pu_en' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_6.pu_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_6.pd_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_6.pu_drv_strg' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_6.pd_drv_strg' value='10' />
+ <!-- hps_io_phery_sdmmc_D1, HPS_DEDICATED_7, input, weak pull up disable, is output, Fast Slew, 1_8 -->
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_7.rtrim' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_7.input_buf_en' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_7.wk_pu_en' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_7.pu_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_7.pd_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_7.pu_drv_strg' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_7.pd_drv_strg' value='10' />
+ <!-- hps_io_phery_sdmmc_D2, HPS_DEDICATED_8, input, weak pull up disable, is output, Fast Slew, 1_8 -->
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_8.rtrim' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_8.input_buf_en' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_8.wk_pu_en' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_8.pu_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_8.pd_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_8.pu_drv_strg' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_8.pd_drv_strg' value='10' />
+ <!-- hps_io_phery_sdmmc_D3, HPS_DEDICATED_9, input, weak pull up disable, is output, Fast Slew, 1_8 -->
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_9.rtrim' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_9.input_buf_en' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_9.wk_pu_en' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_9.pu_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_9.pd_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_9.pu_drv_strg' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_9.pd_drv_strg' value='10' />
+ <!-- Unused pin 10 -->
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_10.rtrim' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_10.input_buf_en' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_10.wk_pu_en' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_10.pu_slw_rt' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_10.pd_slw_rt' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_10.pu_drv_strg' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_10.pd_drv_strg' value='0' />
+ <!-- Unused pin 11 -->
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_11.rtrim' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_11.input_buf_en' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_11.wk_pu_en' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_11.pu_slw_rt' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_11.pd_slw_rt' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_11.pu_drv_strg' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_11.pd_drv_strg' value='0' />
+ <!-- hps_io_phery_sdmmc_D4, HPS_DEDICATED_12, input, weak pull up disable, is output, Fast Slew, 1_8 -->
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_12.rtrim' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_12.input_buf_en' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_12.wk_pu_en' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_12.pu_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_12.pd_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_12.pu_drv_strg' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_12.pd_drv_strg' value='10' />
+ <!-- hps_io_phery_sdmmc_D5, HPS_DEDICATED_13, input, weak pull up disable, is output, Fast Slew, 1_8 -->
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_13.rtrim' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_13.input_buf_en' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_13.wk_pu_en' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_13.pu_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_13.pd_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_13.pu_drv_strg' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_13.pd_drv_strg' value='10' />
+ <!-- hps_io_phery_sdmmc_D6, HPS_DEDICATED_14, input, weak pull up disable, is output, Fast Slew, 1_8 -->
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_14.rtrim' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_14.input_buf_en' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_14.wk_pu_en' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_14.pu_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_14.pd_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_14.pu_drv_strg' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_14.pd_drv_strg' value='10' />
+ <!-- hps_io_phery_sdmmc_D7, HPS_DEDICATED_15, input, weak pull up disable, is output, Fast Slew, 1_8 -->
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_15.rtrim' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_15.input_buf_en' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_15.wk_pu_en' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_15.pu_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_15.pd_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_15.pu_drv_strg' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_15.pd_drv_strg' value='10' />
+ <!-- hps_usr_led_g, HPS_DEDICATED_16, input, weak pull up disable, is output, Fast Slew, 1_8 -->
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_16.rtrim' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_16.input_buf_en' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_16.wk_pu_en' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_16.pu_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_16.pd_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_16.pu_drv_strg' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_16.pd_drv_strg' value='10' />
+ <!-- hps_usr_led_r, HPS_DEDICATED_17, input, weak pull up disable, is output, Fast Slew, 1_8 -->
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_17.rtrim' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_17.input_buf_en' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_17.wk_pu_en' value='0' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_17.pu_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_17.pd_slw_rt' value='1' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_17.pu_drv_strg' value='8' />
+ <config name='i_io48_pin_mux_dedicated_io_grp.configuration_dedicated_io_17.pd_drv_strg' value='10' />
+ <config name='i_io48_pin_mux.configuration_dedicated_io_bank.voltage_sel_clkrst_io' value='1' />
+ <config name='i_io48_pin_mux.configuration_dedicated_io_bank.voltage_sel_peri_io' value='1' />
+ </csr>
+ <option_flags>
+ <config name='chosen.early-release-fpga-config' value='0' />
+ </option_flags>
+ <!-- End of the section generated by Quartus Prime -->
+</hps>
diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c
new file mode 100644
index 000000000000..52ecb919e5a2
--- /dev/null
+++ b/arch/arm/boards/reflex-achilles/lowlevel.c
@@ -0,0 +1,48 @@
+#include <common.h>
+#include <linux/sizes.h>
+#include <io.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <asm/cache.h>
+#include <debug_ll.h>
+#include <mach/arria10-sdram.h>
+#include <mach/arria10-regs.h>
+#include <mach/arria10-reset-manager.h>
+#include <mach/arria10-clock-manager.h>
+#include <mach/arria10-pinmux.h>
+#include "pll-config-arria10.c"
+#include "pinmux-config-arria10.c"
+#include <mach/generic.h>
+
+extern char __dtb_socfpga_arria10_achilles_start[];
+
+static noinline void achilles_entry(void)
+{
+ void *fdt;
+
+ arm_early_mmu_cache_invalidate();
+
+ relocate_to_current_adr();
+ setup_c();
+
+ arria10_init(&mainpll_cfg, &perpll_cfg, &pinmux);
+
+ puts_ll("lowlevel init done\n");
+
+ arria10_ddr_calibration_sequence();
+
+ puts_ll("SDRAM setup done\n");
+
+ fdt = __dtb_socfpga_arria10_achilles_start - get_runtime_offset();
+
+ barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt);
+}
+
+ENTRY_FUNCTION(start_socfpga_achilles, r0, r1, r2)
+{
+ arm_cpu_lowlevel_init();
+
+ arm_setup_stack(0xffe00000 + SZ_256K - SZ_32K - SZ_4K - 16);
+
+ achilles_entry();
+}
diff --git a/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c b/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c
new file mode 100644
index 000000000000..58b1a1ebc1fd
--- /dev/null
+++ b/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c
@@ -0,0 +1,105 @@
+#include <mach/arria10-pinmux.h>
+
+static struct arria10_pinmux_cfg pinmux = {
+.shared_io_q4_12=8,
+.shared_io_q4_11=8,
+.shared_io_q4_10=8,
+.shared_io_q4_9=8,
+.shared_io_q4_8=8,
+.shared_io_q4_6=8,
+.shared_io_q4_7=8,
+.shared_io_q4_5=8,
+.shared_io_q4_4=8,
+.shared_io_q4_3=8,
+.shared_io_q4_2=8,
+.shared_io_q4_1=8,
+.shared_io_q3_12=8,
+.shared_io_q3_11=8,
+.shared_io_q3_10=8,
+.shared_io_q3_8=8,
+.shared_io_q3_9=8,
+.shared_io_q3_7=8,
+.shared_io_q3_6=8,
+.shared_io_q3_5=8,
+.shared_io_q3_4=8,
+.shared_io_q3_3=8,
+.shared_io_q3_2=8,
+.shared_io_q3_1=8,
+.shared_io_q2_12=8,
+.shared_io_q2_10=8,
+.shared_io_q2_11=8,
+.shared_io_q2_9=8,
+.shared_io_q2_8=8,
+.shared_io_q2_7=8,
+.shared_io_q2_6=8,
+.shared_io_q2_5=8,
+.shared_io_q2_4=8,
+.shared_io_q2_3=8,
+.shared_io_q2_2=8,
+.shared_io_q2_1=8,
+.shared_io_q1_12=10,
+.shared_io_q1_11=10,
+.shared_io_q1_10=1,
+.shared_io_q1_9=1,
+.shared_io_q1_8=1,
+.shared_io_q1_7=1,
+.shared_io_q1_6=0,
+.shared_io_q1_5=0,
+.shared_io_q1_4=13,
+.shared_io_q1_3=13,
+.shared_io_q1_2=13,
+.shared_io_q1_1=13,
+.dedicated_io_4=8,
+.dedicated_io_5=8,
+.dedicated_io_6=8,
+.dedicated_io_7=8,
+.dedicated_io_8=8,
+.dedicated_io_9=8,
+.dedicated_io_10=10,
+.dedicated_io_11=10,
+.dedicated_io_12=8,
+.dedicated_io_13=8,
+.dedicated_io_14=8,
+.dedicated_io_15=8,
+.dedicated_io_16=15,
+.dedicated_io_17=15,
+.cfg_dedicated_io_bank=0x00000101,
+.cfg_dedicated_io_1=0x000b080a,
+.cfg_dedicated_io_2=0x000b080a,
+.cfg_dedicated_io_3=0x000b080a,
+.cfg_dedicated_io_4=0x000a282a,
+.cfg_dedicated_io_5=0x000a282a,
+.cfg_dedicated_io_6=0x000a282a,
+.cfg_dedicated_io_7=0x000a282a,
+.cfg_dedicated_io_8=0x000a282a,
+.cfg_dedicated_io_9=0x000a282a,
+.cfg_dedicated_io_10=0x00090000,
+.cfg_dedicated_io_11=0x00090000,
+.cfg_dedicated_io_12=0x000a282a,
+.cfg_dedicated_io_13=0x000a282a,
+.cfg_dedicated_io_14=0x000a282a,
+.cfg_dedicated_io_15=0x000a282a,
+.cfg_dedicated_io_16=0x000a282a,
+.cfg_dedicated_io_17=0x000a282a,
+.rgmii0_usefpga=0,
+.rgmii1_usefpga=0,
+.rgmii2_usefpga=0,
+.nand_usefpga=0,
+.qspi_usefpga=0,
+.sdmmc_usefpga=0,
+.usb0_usefpga=0,
+.usb1_usefpga=0,
+.spim0_usefpga=1,
+.spim1_usefpga=0,
+.spis0_usefpga=0,
+.spis1_usefpga=0,
+.uart0_usefpga=0,
+.uart1_usefpga=0,
+.i2c0_usefpga=0,
+.i2c1_usefpga=0,
+.i2cemac0_usefpga=0,
+.i2cemac1_usefpga=0,
+.i2cemac2_usefpga=0,
+.pll_clock_out_usefpga=0,
+};
+
diff --git a/arch/arm/boards/reflex-achilles/pll-config-arria10.c b/arch/arm/boards/reflex-achilles/pll-config-arria10.c
new file mode 100644
index 000000000000..f4b10c956a22
--- /dev/null
+++ b/arch/arm/boards/reflex-achilles/pll-config-arria10.c
@@ -0,0 +1,55 @@
+#include <mach/arria10-clock-manager.h>
+
+static struct arria10_mainpll_cfg mainpll_cfg = {
+ .vco0_psrc = 0,
+ .vco1_numer = 127,
+ .vco1_denom = 1,
+ .mpuclk_cnt = 0,
+ .mpuclk_src = 0,
+ .nocclk_cnt = 0,
+ .nocclk_src = 0,
+ .cntr2clk_cnt = 900,
+ .cntr3clk_cnt = 900,
+ .cntr4clk_cnt = 900,
+ .cntr5clk_cnt = 900,
+ .cntr6clk_cnt = 7,
+ .cntr7clk_cnt = 900,
+ .cntr7clk_src = 0,
+ .cntr8clk_cnt = 900,
+ .cntr9clk_cnt = 900,
+ .cntr9clk_src = 0,
+ .cntr15clk_cnt = 900,
+ .nocdiv_l4mainclk = 2,
+ .nocdiv_l4mpclk = 2,
+ .nocdiv_l4spclk = 2,
+ .nocdiv_csatclk = 2,
+ .nocdiv_cstraceclk = 0,
+ .nocdiv_cspdbgclk = 0,
+ .mpuclk = 0x3840001,
+ .nocclk = 0x3840003,
+};
+
+static struct arria10_perpll_cfg perpll_cfg = {
+ .vco0_psrc = 0,
+ .vco1_denom = 1,
+ .vco1_numer = 119,
+ .cntr2clk_cnt = 5,
+ .cntr2clk_src = 1,
+ .cntr3clk_cnt = 900,
+ .cntr3clk_src = 1,
+ .cntr4clk_cnt = 14,
+ .cntr4clk_src = 1,
+ .cntr5clk_cnt = 374,
+ .cntr5clk_src = 1,
+ .cntr6clk_cnt = 900,
+ .cntr6clk_src = 0,
+ .cntr7clk_cnt = 900,
+ .cntr8clk_cnt = 900,
+ .cntr8clk_src = 0,
+ .cntr9clk_cnt = 900,
+ .cntr9clk_src = 0,
+ .emacctl_emac0sel = 0,
+ .emacctl_emac1sel = 0,
+ .emacctl_emac2sel = 0,
+ .gpiodiv_gpiodbclk = 32000,
+};
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 70359d8242a5..68fa18055a78 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -63,6 +63,7 @@ pbl-dtb-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o
pbl-dtb-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o
pbl-dtb-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += socfpga_cyclone5_socdk.dtb.o
pbl-dtb-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
+pbl-dtb-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += socfpga_arria10_achilles.dtb.o
pbl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += socfpga_cyclone5_de0_nano_soc.dtb.o
pbl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o
pbl-dtb-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o
diff --git a/arch/arm/dts/socfpga_arria10_achilles.dts b/arch/arm/dts/socfpga_arria10_achilles.dts
new file mode 100644
index 000000000000..dd991318e249
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_achilles.dts
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2015 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+/dts-v1/;
+#include <arm/socfpga_arria10.dtsi>
+
+/ {
+ model = "Reflex SOCFPGA Arria 10 Achilles";
+ compatible = "reflex,achilles", "altr,socfpga-arria10", "altr,socfpga";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ linux,stdout-path = &uart0;
+
+ environment@0 {
+ compatible = "barebox,environment";
+ device-path = &mmc, "partname:1";
+ file-path = "barebox.env";
+ };
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0xc0000000>;
+ };
+
+ soc {
+ clkmgr@ffd04000 {
+ clocks {
+ osc1 {
+ clock-frequency = <25000000>;
+ };
+
+ cb_intosc_hs_div2_clk {
+ clock-frequency = <0>;
+ };
+ cb_intosc_ls_clk {
+ clock-frequency = <60000000>;
+ };
+ f2s_free_clk {
+ clock-frequency = <200000000>;
+ };
+ };
+ };
+ };
+};
+
+&gmac1 {
+ phy-mode = "rgmii";
+ phy-addr = <0x00fffff0>; /* probe for phy addr */
+
+ /*
+ * These skews assume the user's FPGA design is adding 600ps of delay
+ * for TX_CLK on Arria 10.
+ *
+ * All skews are offset since hardware skew values for the ksz9031
+ * range from a negative skew to a positive skew.
+ * See the micrel-ksz90x1.txt Documentation file for details.
+ */
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <1860>; /* 960ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
+ max-frame-size = <3800>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ tempsensor: ti,tmp102@0x48 {
+ compatible = "ti,tmp102";
+ reg = <0x48>;
+ };
+
+ rtc: nxp,pcf8563@0x51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+
+ eeprom: at24@0x54 {
+ compatible = "at24";
+ reg = <0x54>;
+ bytelen = <256>;
+ pagesize = <16>;
+ };
+};
+
+&mmc {
+ supports-highspeed;
+ broken-cd;
+ bus-width = <1>;
+ status = "okay";
+};
+
+&uart0 {
+ reg-io-width = <4>;
+ status = "okay";
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 003574ba8d65..9bdcd7fec56f 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -32,6 +32,11 @@ config MACH_SOCFPGA_EBV_SOCRATES
select ARCH_SOCFPGA_CYCLONE5
bool "EBV Socrates"
+config MACH_SOCFPGA_REFLEX_ACHILLES
+ select HAVE_DEFAULT_ENVIRONMENT_NEW
+ select ARCH_SOCFPGA_ARRIA10
+ bool "Reflex Achilles"
+
config MACH_SOCFPGA_TERASIC_DE0_NANO_SOC
select HAVE_DEFAULT_ENVIRONMENT_NEW
select ARCH_SOCFPGA_CYCLONE5
diff --git a/images/Makefile.socfpga b/images/Makefile.socfpga
index d210a6cc2318..2d4b91dada3c 100644
--- a/images/Makefile.socfpga
+++ b/images/Makefile.socfpga
@@ -35,6 +35,10 @@ pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += start_socfpga_de0_nano_soc
FILE_barebox-socfpga-de0_nano_soc.img = start_socfpga_de0_nano_soc.pblx
socfpga-barebox-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += barebox-socfpga-de0_nano_soc.img
+pblx-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += start_socfpga_achilles
+FILE_barebox-socfpga-achilles.img = start_socfpga_achilles.pblx.socfpgaimg
+socfpga-barebox-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += barebox-socfpga-achilles.img
+
pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += start_socfpga_sockit_xload
FILE_barebox-socfpga-sockit-xload.img = start_socfpga_sockit_xload.pblx.socfpgaimg
socfpga-xload-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += barebox-socfpga-sockit-xload.img
--
2.11.0
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 7/7] ARM: socfpga: add arria10 defconfig
2017-04-03 10:55 [PATCH 0/7] SoCFPGA: add support for Arria10 Steffen Trumtrar
` (5 preceding siblings ...)
2017-04-03 10:55 ` [PATCH 6/7] ARM: socfpga: add support for reflex achilles board Steffen Trumtrar
@ 2017-04-03 10:55 ` Steffen Trumtrar
2017-04-04 17:52 ` [PATCH 0/7] SoCFPGA: add support for Arria10 Trent Piepho
7 siblings, 0 replies; 12+ messages in thread
From: Steffen Trumtrar @ 2017-04-03 10:55 UTC (permalink / raw)
To: barebox; +Cc: Steffen Trumtrar
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/configs/socfpga-arria10_defconfig | 89 ++++++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
create mode 100644 arch/arm/configs/socfpga-arria10_defconfig
diff --git a/arch/arm/configs/socfpga-arria10_defconfig b/arch/arm/configs/socfpga-arria10_defconfig
new file mode 100644
index 000000000000..e661895d6e6c
--- /dev/null
+++ b/arch/arm/configs/socfpga-arria10_defconfig
@@ -0,0 +1,89 @@
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES=y
+CONFIG_THUMB2_BAREBOX=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
+CONFIG_MMU=y
+CONFIG_MALLOC_SIZE=0x0
+CONFIG_MALLOC_TLSF=y
+CONFIG_KALLSYMS=y
+CONFIG_RELOCATABLE=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
+# CONFIG_TIMESTAMP is not set
+CONFIG_BOOTM_SHOW_TYPE=y
+CONFIG_BOOTM_VERBOSE=y
+CONFIG_BOOTM_INITRD=y
+CONFIG_BOOTM_OFTREE=y
+CONFIG_PBL_CONSOLE=y
+CONFIG_DEFAULT_COMPRESSION_LZO=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_POLLER=y
+CONFIG_STATE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_LONGHELP=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_ARM_MMUINFO=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_FILETYPE=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_SHA256SUM=y
+CONFIG_CMD_LET=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_MENU=y
+CONFIG_CMD_MENU_MANAGEMENT=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MM=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_BAREBOX_UPDATE=y
+CONFIG_CMD_FIRMWARELOAD=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_STATE=y
+CONFIG_NET=y
+CONFIG_NET_NETCONSOLE=y
+CONFIG_NET_RESOLV=y
+CONFIG_OF_BAREBOX_DRIVERS=y
+CONFIG_OF_BAREBOX_ENV_IN_FS=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_NET_DESIGNWARE=y
+CONFIG_MICREL_PHY=y
+# CONFIG_SPI is not set
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_MMC_BOOT_PARTITIONS=y
+CONFIG_MCI_DW=y
+# CONFIG_PINCTRL is not set
+CONFIG_FS_TFTP=y
+CONFIG_FS_NFS=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_ZLIB=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_DIGEST_SHA256_ARM=y
--
2.11.0
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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/7] SoCFPGA: add support for Arria10
2017-04-03 10:55 [PATCH 0/7] SoCFPGA: add support for Arria10 Steffen Trumtrar
` (6 preceding siblings ...)
2017-04-03 10:55 ` [PATCH 7/7] ARM: socfpga: add arria10 defconfig Steffen Trumtrar
@ 2017-04-04 17:52 ` Trent Piepho
2017-04-05 7:35 ` Steffen Trumtrar
7 siblings, 1 reply; 12+ messages in thread
From: Trent Piepho @ 2017-04-04 17:52 UTC (permalink / raw)
To: s.trumtrar; +Cc: barebox
On Mon, 2017-04-03 at 12:55 +0200, Steffen Trumtrar wrote:
> Although Cyclone5 and Arria10 share a lot of the peripherals,
> they a different in the critical parts (SDRAM controller, clock setup,...)
>
> The Arria10 has a larger OCRAM (64KB vs 256KB), that is why we can
> omit the xload support for now. The xload support can be added, once
> Arria10 boards that need to program the FPGA very early (might be needed for
> the SDRAM controller) are available.
>
That means this support doesn't include loading the FPGA from barebox?
The boot strategy is that the Barebox PBL image will fit in OCRAM and be
loaded by the ROM loader, and then the PBL will decompress barebox into
SDRAM? If so, it will be necessary to have the FPGA loaded from an
external device, such as an EPCQ flash chip, before barebox boots. As
SDRAM is not accessible until at least the peripheral FPGA image is
loaded.
U-Boot is able to load a FPGA image with a single bootloader. A U-Boot
image can be made that is small enough run in 256 kB yet has enough
drivers to load an FPGA image from eMMC or NOR flash into the FPGA and
then enable SDRAM.
It seems like this might be possible for barebox as well. If enough
drivers to load the FPGA were part of the PBL.
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/7] ARM: socfpga: add arria10 support
2017-04-03 10:55 ` [PATCH 4/7] ARM: socfpga: add arria10 support Steffen Trumtrar
@ 2017-04-04 18:58 ` Trent Piepho
0 siblings, 0 replies; 12+ messages in thread
From: Trent Piepho @ 2017-04-04 18:58 UTC (permalink / raw)
To: s.trumtrar; +Cc: barebox
On Mon, 2017-04-03 at 12:55 +0200, Steffen Trumtrar wrote:
> + vco = src_hz;
> + vco /= (1 + denom);
> + vco *= (1 + numer);
Don't you get rounding error by dividing first?
> + /* dedicated pins */
> + writel(pinmux->dedicated_io_4, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x0c);
> + writel(pinmux->dedicated_io_5, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x10);
> + writel(pinmux->dedicated_io_6, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x14);
> + writel(pinmux->dedicated_io_7, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x18);
> + writel(pinmux->dedicated_io_8, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x1c);
> + writel(pinmux->dedicated_io_9, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x20);
> + writel(pinmux->dedicated_io_10, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x24);
> + writel(pinmux->dedicated_io_11, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x28);
> + writel(pinmux->dedicated_io_12, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x2c);
> + writel(pinmux->dedicated_io_13, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x30);
> + writel(pinmux->dedicated_io_14, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x34);
> + writel(pinmux->dedicated_io_15, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x38);
> + writel(pinmux->dedicated_io_16, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x3c);
> + writel(pinmux->dedicated_io_17, ARRIA10_PINMUX_DEDICATED_IO_ADDR + 0x40);
> +
> + writel(pinmux->cfg_dedicated_io_bank, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x00);
> + writel(pinmux->cfg_dedicated_io_1, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x04);
> + writel(pinmux->cfg_dedicated_io_2, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x08);
> + writel(pinmux->cfg_dedicated_io_3, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x0c);
> + writel(pinmux->cfg_dedicated_io_4, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x10);
> + writel(pinmux->cfg_dedicated_io_5, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x14);
> + writel(pinmux->cfg_dedicated_io_6, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x18);
> + writel(pinmux->cfg_dedicated_io_7, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x1c);
> + writel(pinmux->cfg_dedicated_io_8, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x20);
> + writel(pinmux->cfg_dedicated_io_9, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x24);
> + writel(pinmux->cfg_dedicated_io_10, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x28);
> + writel(pinmux->cfg_dedicated_io_11, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x2c);
> + writel(pinmux->cfg_dedicated_io_12, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x30);
> + writel(pinmux->cfg_dedicated_io_13, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x3c);
> + writel(pinmux->cfg_dedicated_io_14, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x38);
> + writel(pinmux->cfg_dedicated_io_15, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x3c);
> + writel(pinmux->cfg_dedicated_io_16, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x40);
> + writel(pinmux->cfg_dedicated_io_17, ARRIA10_PINMUX_DEDICATED_IO_CFG_ADDR + 0x44);
Sure are a lot of copied lines there. Wouldn't an array and loop be
more elegant?
> +void arria10_reset_deassert_dedicated_peripherals(void)
> +{
> + uint32_t mask0 = 0;
> + uint32_t mask1 = 0;
> + uint32_t mask = 0;
> +
> + mask |= ARRIA10_RSTMGR_PER0MODRST_SDMMCECC;
> + mask |= ARRIA10_RSTMGR_PER0MODRST_QSPIECC;
> + mask |= ARRIA10_RSTMGR_PER0MODRST_NANDECC;
> + mask |= ARRIA10_RSTMGR_PER0MODRST_DMAECC;
> +
> + /* enable ECC OCP first */
> + clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask);
> +
> + mask = 0;
> + mask |= ARRIA10_RSTMGR_PER0MODRST_SDMMC;
> + mask |= ARRIA10_RSTMGR_PER0MODRST_QSPI;
> + mask |= ARRIA10_RSTMGR_PER0MODRST_NAND;
> + mask |= ARRIA10_RSTMGR_PER0MODRST_DMA;
It looks like the peripherals to bring out of reset are hard coded here?
Should unused peripherals be brought out of reset?
> +
> + clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask);
> +
> + mask = ARRIA10_RSTMGR_PER1MODRST_L4SYSTMR0;
How come this time mask isn't set to 0 first like the two blocks above?
I.e., why not write it in a consistent style?
> +
> + mask |= ARRIA10_RSTMGR_PER1MODRST_UART1;
> + mask |= ARRIA10_RSTMGR_PER1MODRST_UART0;
> +
> + clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST, mask);
Is there a reason to bring system timer0, and uart 0 & 1 out of reset
here, and then a bunch of other peripherals in the same register out of
reset below? Why not do them all at once?
> +
> + mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C3;
> + mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C4;
> + mask1 |= ARRIA10_RSTMGR_PER1MODRST_I2C2;
> + mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMACECC1 |
> + ARRIA10_RSTMGR_PER0MODRST_EMAC1;
> + mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMACECC2 |
> + ARRIA10_RSTMGR_PER0MODRST_EMAC2;
> + mask0 |= ARRIA10_RSTMGR_PER0MODRST_EMACECC0 |
> + ARRIA10_RSTMGR_PER0MODRST_EMAC0;
> + mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIS0;
> + mask0 |= ARRIA10_RSTMGR_PER0MODRST_SPIM0;
> + mask1 |= ARRIA10_RSTMGR_PER1MODRST_UART1;
uart1 was already brought out of reset in the previous block, why again?
> + mask1 |= ARRIA10_RSTMGR_PER1MODRST_GPIO2;
Why now mask1 and mask0? Why not continue the pattern from the previous
three blocks and use mask.
> +
> + clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST,
> + mask & ECC_MASK);
This looks like a bug. mask was last set to the bits for PER*1*MODRST
peripherals but here it is programming PER*0*MODRST register.
> + clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST, mask1);
> + clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask0);
> +}
> +
> +static const uint32_t per0fpgamasks[] = {
> + ARRIA10_RSTMGR_PER0MODRST_EMACECC0 |
> + ARRIA10_RSTMGR_PER0MODRST_EMAC0,
> + ARRIA10_RSTMGR_PER0MODRST_EMACECC1 |
> + ARRIA10_RSTMGR_PER0MODRST_EMAC1,
> + ARRIA10_RSTMGR_PER0MODRST_EMACECC2 |
> + ARRIA10_RSTMGR_PER0MODRST_EMAC2,
> + 0, /* i2c0 per1mod */
Comments for unset lines look incorrect. These should be per0modrst
bits, not per1modrst bits.
> + 0, /* i2c1 per1mod */
> + 0, /* i2c0_emac */
> + 0, /* i2c1_emac */
> + 0, /* i2c2_emac */
> + ARRIA10_RSTMGR_PER0MODRST_NANDECC |
> + ARRIA10_RSTMGR_PER0MODRST_NAND,
> + ARRIA10_RSTMGR_PER0MODRST_QSPIECC |
> + ARRIA10_RSTMGR_PER0MODRST_QSPI,
> + ARRIA10_RSTMGR_PER0MODRST_SDMMCECC |
> + ARRIA10_RSTMGR_PER0MODRST_SDMMC,
> + ARRIA10_RSTMGR_PER0MODRST_SPIM0,
> + ARRIA10_RSTMGR_PER0MODRST_SPIM1,
> + ARRIA10_RSTMGR_PER0MODRST_SPIS0,
> + ARRIA10_RSTMGR_PER0MODRST_SPIS1,
> + 0, /* uart0 per1mod */
> + 0, /* uart1 per1mod */
> +};
This hard codes what peripherals are connected to the FPGA, right?
Shouldn't this come from the device tree?
> +
> +static const uint32_t per1fpgamasks[] = {
> + 0, /* emac0 per0mod */
Ditto, comments don't match the array values, per0 vs per1.
> + 0, /* emac1 per0mod */
> + 0, /* emac2 per0mod */
> + ARRIA10_RSTMGR_PER1MODRST_I2C0,
> + ARRIA10_RSTMGR_PER1MODRST_I2C1,
> + ARRIA10_RSTMGR_PER1MODRST_I2C2, /* i2c0_emac */
> + ARRIA10_RSTMGR_PER1MODRST_I2C3, /* i2c1_emac */
> + ARRIA10_RSTMGR_PER1MODRST_I2C4, /* i2c2_emac */
> + 0, /* nand per0mod */
> + 0, /* qspi per0mod */
> + 0, /* sdmmc per0mod */
> + 0, /* spim0 per0mod */
> + 0, /* spim1 per0mod */
> + 0, /* spis0 per0mod */
> + 0, /* spis1 per0mod */
> + ARRIA10_RSTMGR_PER1MODRST_UART0,
> + ARRIA10_RSTMGR_PER1MODRST_UART1,
> +};
> +
> +#define DDR_CONFIG_ELEMENTS (sizeof(ddr_config)/sizeof(uint32_t))
ARRAY_SIZE(ddr_config)
> +void udelay(unsigned long time)
> +{
> + unsigned long i = 1000 * time;
> +
> + while (i--)
> + ;
> +}
Is there something wrong with the barebox udelay? How does this delay
for microseconds?
> +
> +static void ddr_set_bit(uint32_t ereg, uint32_t bit)
> +{
> + unsigned int tmp = readl(ereg);
> +
> + tmp |= (1 << bit);
> + writel(tmp, ereg);
> +}
Why not use setbits_le32() like the rest of the barebox code?
> +
> +static void ddr_clr_bit(uint32_t ereg, uint32_t bit)
> +{
> + unsigned int tmp = readl(ereg);
> +
> + tmp &= ~(1 << bit);
> + writel(tmp, ereg);
> +}
Ditto, clrbits_le32
> +
> +static void ddr_delay(uint32_t delay)
> +{
> + int tmr;
> +
> + for (tmr = 0; tmr < delay; tmr++)
> + udelay(1000);
> +}
Why not the mdelay() that already exists?
> +/* Function to startup the SDRAM*/
> +static int arria10_sdram_startup(void)
> +{
> + uint32_t val;
> + /* Release NOC ddr scheduler from reset */
> + val = readl(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_BRGMODRST);
> + val &= ~ARRIA10_RSTMGR_BRGMODRST_DDRSCH;
> + writel(val, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_BRGMODRST);
clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_BRGMODRST,
ARRIA10_RSTMGR_BRGMODRST_DDRSCH)
> diff --git a/images/Makefile.socfpga b/images/Makefile.socfpga
> index 21804d93df72..d210a6cc2318 100644
> --- a/images/Makefile.socfpga
> +++ b/images/Makefile.socfpga
> @@ -4,11 +4,19 @@
>
> # %.socfpgaimg - convert into socfpga image
> # ----------------------------------------------------------------
> +ifdef CONFIG_ARCH_SOCFPGA_ARRIA10
> +quiet_cmd_socfpga_image = SOCFPGA-IMG $@
> + cmd_socfpga_image = scripts/socfpga_mkimage -o $@ -b -v1 $<
Why prepend the extra barebox header?
> +
> +$(obj)/%.socfpgaimg: $(obj)/% FORCE
> + $(call if_changed,socfpga_image)
> +else
> quiet_cmd_socfpga_image = SOCFPGA-IMG $@
> cmd_socfpga_image = scripts/socfpga_mkimage -o $@ $<
>
> $(obj)/%.socfpgaimg: $(obj)/% FORCE
> $(call if_changed,socfpga_image)
Why these two lines above duplicated in the ifdef? They are the same.
Maybe don't use ifdef and duplicated code and instead have options that
are set based on image type. Like this:
SOCFPGA_IMAGE_ARGS-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += -v1
SOCFPGA_IMAGE_ARGS-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += -v0
cmd_socfpga_image = scripts/socfpga_mkimage -o $@ $(SOCFPGA_IMAGE_ARGS-y) $<
> +endif
>
> # ----------------------- Cyclone5 based boards ---------------------------
> pblx-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += start_socfpga_socdk_xload
> diff --git a/scripts/socfpga_mkimage.c b/scripts/socfpga_mkimage.c
> index d7fe1b1b69f7..3763044aacab 100644
> --- a/scripts/socfpga_mkimage.c
> +++ b/scripts/socfpga_mkimage.c
> @@ -62,6 +62,7 @@ static uint32_t bb_header[] = {
> 0x00000000, /* socfpga header */
> 0x00000000, /* socfpga header */
> 0x00000000, /* socfpga header */
> + 0x00000000, /* socfpga header */
> 0xea00006b, /* entry. b 0x200 (offset may be adjusted) */
> };
I think this change will break extra barebox header with v0 images.
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/7] SoCFPGA: add support for Arria10
2017-04-04 17:52 ` [PATCH 0/7] SoCFPGA: add support for Arria10 Trent Piepho
@ 2017-04-05 7:35 ` Steffen Trumtrar
2017-04-05 18:55 ` Trent Piepho
0 siblings, 1 reply; 12+ messages in thread
From: Steffen Trumtrar @ 2017-04-05 7:35 UTC (permalink / raw)
To: Trent Piepho; +Cc: barebox
Trent Piepho <tpiepho@kymetacorp.com> writes:
> On Mon, 2017-04-03 at 12:55 +0200, Steffen Trumtrar wrote:
>> Although Cyclone5 and Arria10 share a lot of the peripherals,
>> they a different in the critical parts (SDRAM controller, clock setup,...)
>>
>> The Arria10 has a larger OCRAM (64KB vs 256KB), that is why we can
>> omit the xload support for now. The xload support can be added, once
>> Arria10 boards that need to program the FPGA very early (might be needed for
>> the SDRAM controller) are available.
>>
>
> That means this support doesn't include loading the FPGA from barebox?
That is correct.
>
> The boot strategy is that the Barebox PBL image will fit in OCRAM and be
> loaded by the ROM loader, and then the PBL will decompress barebox into
> SDRAM? If so, it will be necessary to have the FPGA loaded from an
> external device, such as an EPCQ flash chip, before barebox boots. As
> SDRAM is not accessible until at least the peripheral FPGA image is
> loaded.
>
> U-Boot is able to load a FPGA image with a single bootloader. A U-Boot
> image can be made that is small enough run in 256 kB yet has enough
> drivers to load an FPGA image from eMMC or NOR flash into the FPGA and
> then enable SDRAM.
>
> It seems like this might be possible for barebox as well. If enough
> drivers to load the FPGA were part of the PBL.
Of course this is also possible with barebox. The reason that the
support is not added yet, is that I do not have any Arria10 board that
needs or uses this; even with the provided vendor U-Boot.
This series is just groundwork for future development.
Regards,
Steffen
--
Pengutronix e.K. | Steffen Trumtrar |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/7] SoCFPGA: add support for Arria10
2017-04-05 7:35 ` Steffen Trumtrar
@ 2017-04-05 18:55 ` Trent Piepho
0 siblings, 0 replies; 12+ messages in thread
From: Trent Piepho @ 2017-04-05 18:55 UTC (permalink / raw)
To: s.trumtrar; +Cc: barebox
On Wed, 2017-04-05 at 09:35 +0200, Steffen Trumtrar wrote:
> Trent Piepho <tpiepho@kymetacorp.com> writes:
> >
> > U-Boot is able to load a FPGA image with a single bootloader. A U-Boot
> > image can be made that is small enough run in 256 kB yet has enough
> > drivers to load an FPGA image from eMMC or NOR flash into the FPGA and
> > then enable SDRAM.
> >
> > It seems like this might be possible for barebox as well. If enough
> > drivers to load the FPGA were part of the PBL.
>
> Of course this is also possible with barebox. The reason that the
> support is not added yet, is that I do not have any Arria10 board that
> needs or uses this; even with the provided vendor U-Boot.
> This series is just groundwork for future development.
Any A10 board should be able to use CvP, as Altera calls it, to load the
FPGA image from a processor accessible memory like QSPI or mmc or even
perhaps NFS. While most of the dev kits seem to have an EPCQ flash so
this isn't necessary, after you have used JTAG to reprogram that EPCQ
flash at 20 minutes each time, the drawbacks become more apparent!
Being able to use barebox to NFS load the image or copy an image into
eMMC at far faster rate than EPCQ NOR flash over JTAG would be really
nice.
U-Boot doesn't have a PBL. It does this by building a somewhat stripped
u-boot that fits, uncompressed, into 256 kB. It uses the qspi or mmc
drivers (pretty sure only one will fit!) to stream the image into the
FPGA before enabling SDRAM.
Barebox is larger than u-boot so this might not work. Try making a <
224 kB _uncompressed_ barebox. It has to be pretty stripped. It's
already a pain that u-boot can't have mmc, qspi, and network support at
the same time. A barebox that runs inside 256 kB would be even more
limited.
But, barebox has the ability to use a compressed image plus a PBL.
Maybe this can let barebox do better than u-boot on arria10?
One could try to place the drivers needed to load the FPGA into the PBL,
have the PBL code load the FPGA and enable SDRAM, then uncompress the
not-stripped main barebox.
The difficulty would be getting the drivers needed to load the FPGA to
run from PBL context. Then fitting those uncompressed drivers and PBL
code plus the compressed main barebox into a 224kB image.
One could also try a two barebox solution like Cyclone5, where one
builds barebox twice in an xloader and main configuration. In that
case, it might make sense for the xloader to NOT use a PBL. The reason
PBL works on C5, is because the code to enable SDRAM isn't that large
and fits in the PBL. On A10, enabling SDRAM means finding and streaming
a file in a filesystem on MMC into the FPGA. Much more complex if you
want to leverage the existing drivers. The PBL will be so large that
the extra code to uncompress and relocate barebox is larger than any
savings of having what's not in the PBL be compressed.
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^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2017-04-05 18:55 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-04-03 10:55 [PATCH 0/7] SoCFPGA: add support for Arria10 Steffen Trumtrar
2017-04-03 10:55 ` [PATCH 1/7] ARM: socfpga: rename socfpga->cyclone5 Steffen Trumtrar
2017-04-03 10:55 ` [PATCH 2/7] clk: socfpga: move driver to subdirectory Steffen Trumtrar
2017-04-03 10:55 ` [PATCH 3/7] net: designware: add dwmac-3.72a compatible Steffen Trumtrar
2017-04-03 10:55 ` [PATCH 4/7] ARM: socfpga: add arria10 support Steffen Trumtrar
2017-04-04 18:58 ` Trent Piepho
2017-04-03 10:55 ` [PATCH 5/7] clk: socfpga: add arria10 clk drivers Steffen Trumtrar
2017-04-03 10:55 ` [PATCH 6/7] ARM: socfpga: add support for reflex achilles board Steffen Trumtrar
2017-04-03 10:55 ` [PATCH 7/7] ARM: socfpga: add arria10 defconfig Steffen Trumtrar
2017-04-04 17:52 ` [PATCH 0/7] SoCFPGA: add support for Arria10 Trent Piepho
2017-04-05 7:35 ` Steffen Trumtrar
2017-04-05 18:55 ` Trent Piepho
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