Re: [PATCH v2 00/11] AT91, at91sam9x5ek updates (part II/III)

From: Sascha Hauer <s.hauer@pengutronix.de>
To: Sam Ravnborg <sam@ravnborg.org>
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>, barebox@lists.infradead.org
Subject: Re: [PATCH v2 00/11] AT91, at91sam9x5ek updates (part II/III)
Date: Wed, 19 Apr 2017 11:42:29 +0200	[thread overview]
Message-ID: <20170419094229.hqdwrshmyph6clc2@pengutronix.de> (raw)
In-Reply-To: <20170415215042.GA3267@ravnborg.org>

Hi Sam,

On Sat, Apr 15, 2017 at 11:50:42PM +0200, Sam Ravnborg wrote:
> Hi Andrey.
> 
> While trying to port my proprietary at91sam9263 based board
> I have stumbled over how the early init works.
> And so far I have used at91sam9x5ek as reference.
> 
> If I follow the code paths for sam9x5 it looks like this:
> 
> 	barebox_arm_head  (arch/arm/include/asm/barebox-arm-head.h)
> 	    _barebox_arm_head
> 	    b barebox_arm_reset_vector -->
> 
> 	barebox_arm_reset_vector (arch/arm/mach-at91/at91sam9x5_lowlevel_init.c)
> 	    arm_cpu_lowlevel_init
> 	    arm_setup_stack(AT91SAM9X5_SRAM_BASE + AT91SAM9X5_SRAM_SIZE - 16);
> 	    barebox_arm_entry -->

barebox_arm_reset_vector is unused for multi image support.

> 
> 	barebox_arm_entry (arch/arm/cpu/entry.c)
> 	    arm_setup_stack(arm_mem_stack_top(membase, membase + memsize) - 16);
> 	    arm_early_mmu_cache_invalidate
> 	    barebox_{multi,single,non}_pbl_start
> 
> 	And then we have:
> 	ENTRY_FUNCTION(start_at91sam9x5ek, r0, r1, r2)  (arch/arm/boards/at91sam9x5ek/lowlevel.c)
> 	    arm_cpu_lowlevel_init
> 	    arm_setup_stack(AT91SAM9X5_SRAM_BASE + AT91SAM9X5_SRAM_SIZE - 16);
> 	    barebox_arm_entry
> 
> 
> And something in this confuses me...
> I know at91sam9x5 is built for multi image support.
> Which is why start_at91sam9x5ek() is referenced in images/Makefile.at91
> 
> But why do we need to call arm_setup_stack() in three different places.
> And with different parameters.
> And arm_cpu_lowlevel_init is called from two places.
> 
> Can someone shed some light on this.

Ultimately we want to have the stack somehwere at the end of the SDRAM.
However, during early init there might be no SDRAM available, so the
stack is configured into internal SRAM.

Sascha

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