[PATCH] PPC: request a consistent memory layout (part II)

[PATCH] PPC: request a consistent memory layout (part II)

[Juergen Borleis]

Using the memory test command will crash barebox, because it may tests the
area where the vector table is located for the PPC architecture.

On the e300 PPC core the vectors are programmable in their location.
This change checks the used location at run-time and requests the area
to prevent the memory test from overwriting it.

Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
---
 arch/ppc/include/asm/common.h |  1 +
 arch/ppc/mach-mpc5xxx/cpu.c   | 17 +++++++++++++++++
 arch/ppc/mach-mpc5xxx/start.S |  5 +++++
 3 files changed, 23 insertions(+)

diff --git a/arch/ppc/include/asm/common.h b/arch/ppc/include/asm/common.h
index 045817bed..7ea5dacdb 100644
--- a/arch/ppc/include/asm/common.h
+++ b/arch/ppc/include/asm/common.h
@@ -11,6 +11,7 @@ int	cpu_init      (void);
 
 uint	get_pvr	      (void);
 uint	get_svr	      (void);
+uint	get_msr	      (void);
 
 void	trap_init     (ulong);
 
diff --git a/arch/ppc/mach-mpc5xxx/cpu.c b/arch/ppc/mach-mpc5xxx/cpu.c
index ab58967aa..75bb7b9e8 100644
--- a/arch/ppc/mach-mpc5xxx/cpu.c
+++ b/arch/ppc/mach-mpc5xxx/cpu.c
@@ -61,10 +61,27 @@ int checkcpu (void)
 }
 
 /* ------------------------------------------------------------------------- */
+static unsigned mpc5125_get_CPU_exception_vector_begin(void)
+{
+	unsigned msr = get_msr();
+
+	if (msr & MSR_IP)
+		return 0xfff00000;
+	return 0x00000000;
+}
 
 static int mpc5xxx_reserve_region(void)
 {
 	struct resource *r;
+	unsigned exception_vector;
+
+	exception_vector = mpc5125_get_CPU_exception_vector_begin();
+	r = request_sdram_region("vector_table", exception_vector, exception_vector + 0x2fff);
+	if (r == NULL) {
+		pr_err("Failed to request vector_table region at: 0x%08x/0x%08x\n",
+			exception_vector, exception_vector + 0x2fff);
+		return -EBUSY;
+	}
 
 	/* keep this in sync with the assembler routines setting up the stack */
 	r = request_sdram_region("stack", _text_base - STACK_SIZE, STACK_SIZE);
diff --git a/arch/ppc/mach-mpc5xxx/start.S b/arch/ppc/mach-mpc5xxx/start.S
index 291f6250a..67207ae81 100644
--- a/arch/ppc/mach-mpc5xxx/start.S
+++ b/arch/ppc/mach-mpc5xxx/start.S
@@ -737,3 +737,8 @@ _bss_start:
 .globl _bss_end
 _bss_end:
 	.long _end
+
+.globl get_msr
+get_msr:
+	mfmsr	r3
+	blr
-- 
2.11.0


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Re: [PATCH] PPC: request a consistent memory layout (part II)

[Sascha Hauer]

On Mon, May 22, 2017 at 10:49:30AM +0200, Juergen Borleis wrote:
> Using the memory test command will crash barebox, because it may tests the
> area where the vector table is located for the PPC architecture.
> 
> On the e300 PPC core the vectors are programmable in their location.
> This change checks the used location at run-time and requests the area
> to prevent the memory test from overwriting it.
> 
> Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
> ---
>  arch/ppc/include/asm/common.h |  1 +
>  arch/ppc/mach-mpc5xxx/cpu.c   | 17 +++++++++++++++++
>  arch/ppc/mach-mpc5xxx/start.S |  5 +++++
>  3 files changed, 23 insertions(+)
> 
> diff --git a/arch/ppc/include/asm/common.h b/arch/ppc/include/asm/common.h
> index 045817bed..7ea5dacdb 100644
> --- a/arch/ppc/include/asm/common.h
> +++ b/arch/ppc/include/asm/common.h
> @@ -11,6 +11,7 @@ int	cpu_init      (void);
>  
>  uint	get_pvr	      (void);
>  uint	get_svr	      (void);
> +uint	get_msr	      (void);
>  
>  void	trap_init     (ulong);
>  
> diff --git a/arch/ppc/mach-mpc5xxx/cpu.c b/arch/ppc/mach-mpc5xxx/cpu.c
> index ab58967aa..75bb7b9e8 100644
> --- a/arch/ppc/mach-mpc5xxx/cpu.c
> +++ b/arch/ppc/mach-mpc5xxx/cpu.c
> @@ -61,10 +61,27 @@ int checkcpu (void)
>  }
>  
>  /* ------------------------------------------------------------------------- */
> +static unsigned mpc5125_get_CPU_exception_vector_begin(void)
> +{
> +	unsigned msr = get_msr();
> +
> +	if (msr & MSR_IP)
> +		return 0xfff00000;
> +	return 0x00000000;
> +}
>  
>  static int mpc5xxx_reserve_region(void)
>  {
>  	struct resource *r;
> +	unsigned exception_vector;
> +
> +	exception_vector = mpc5125_get_CPU_exception_vector_begin();
> +	r = request_sdram_region("vector_table", exception_vector, exception_vector + 0x2fff);
> +	if (r == NULL) {
> +		pr_err("Failed to request vector_table region at: 0x%08x/0x%08x\n",
> +			exception_vector, exception_vector + 0x2fff);
> +		return -EBUSY;
> +	}

I have the feeling that we should actively put the vector table to one
of the two locations, so we should implicitly know where it is and not
have to test the MSR_IP bit.

Also there is no SDRAM at 0xfff00000, right? Requesting SDRAM there
will fail every time for a good reason.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH] PPC: request a consistent memory layout (part II)

[Juergen Borleis]

Hi Sascha,

On Monday 22 May 2017 12:26:43 Sascha Hauer wrote:
> [...]
> I have the feeling that we should actively put the vector table to one
> of the two locations, so we should implicitly know where it is and not
> have to test the MSR_IP bit.

Sometimes it depends on the boot mode. You can locate the NOR flash memory 
at 0x00000 or 0xfff00000 (via bootstrap pins) and in the latter case the 
vector table is at 0xfff00000 (at least the reset vector)!

> Also there is no SDRAM at 0xfff00000, right?

Yes, but (maybe) flash.

> Requesting SDRAM there will fail every time for a good reason.

Good catch.

jb
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Pengutronix e.K.                             | Juergen Borleis             |
Industrial Linux Solutions                   | http://www.pengutronix.de/  |

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Re: [PATCH] PPC: request a consistent memory layout (part II)

[Sascha Hauer]

On Mon, May 22, 2017 at 12:34:38PM +0200, Juergen Borleis wrote:
> Hi Sascha,
> 
> On Monday 22 May 2017 12:26:43 Sascha Hauer wrote:
> > [...]
> > I have the feeling that we should actively put the vector table to one
> > of the two locations, so we should implicitly know where it is and not
> > have to test the MSR_IP bit.
> 
> Sometimes it depends on the boot mode. You can locate the NOR flash memory 
> at 0x00000 or 0xfff00000 (via bootstrap pins) and in the latter case the 
> vector table is at 0xfff00000 (at least the reset vector)!

Regardless of the bootmode in the end the vector table should be in
SDRAM, no? With a vector table in flash no vector except the reset
vector will point to a valid address and thus we won't be able to catch
any exceptions. Looing at the powerpc code we really do have exception
handling code, but I don't know how broken it actually is.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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