From: Sascha Hauer <s.hauer@pengutronix.de>
To: Juergen Borleis <jbe@pengutronix.de>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH] PPC: request a consistent memory layout (part II)
Date: Mon, 22 May 2017 12:43:01 +0200 [thread overview]
Message-ID: <20170522104301.tq27k4v3ftavwpbp@pengutronix.de> (raw)
In-Reply-To: <201705221234.39274.jbe@pengutronix.de>
On Mon, May 22, 2017 at 12:34:38PM +0200, Juergen Borleis wrote:
> Hi Sascha,
>
> On Monday 22 May 2017 12:26:43 Sascha Hauer wrote:
> > [...]
> > I have the feeling that we should actively put the vector table to one
> > of the two locations, so we should implicitly know where it is and not
> > have to test the MSR_IP bit.
>
> Sometimes it depends on the boot mode. You can locate the NOR flash memory
> at 0x00000 or 0xfff00000 (via bootstrap pins) and in the latter case the
> vector table is at 0xfff00000 (at least the reset vector)!
Regardless of the bootmode in the end the vector table should be in
SDRAM, no? With a vector table in flash no vector except the reset
vector will point to a valid address and thus we won't be able to catch
any exceptions. Looing at the powerpc code we really do have exception
handling code, but I don't know how broken it actually is.
Sascha
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prev parent reply other threads:[~2017-05-22 10:43 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-22 8:49 Juergen Borleis
2017-05-22 10:26 ` Sascha Hauer
2017-05-22 10:34 ` Juergen Borleis
2017-05-22 10:43 ` Sascha Hauer [this message]
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