From: Sascha Hauer <s.hauer@pengutronix.de>
To: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH] ARM: mvebu: fix size mask for RAM window
Date: Tue, 13 Jun 2017 09:23:03 +0200 [thread overview]
Message-ID: <20170613072303.2pkx6wwqp3sysara@pengutronix.de> (raw)
In-Reply-To: <20170612223749.13780-1-u.kleine-koenig@pengutronix.de>
On Tue, Jun 13, 2017 at 12:37:49AM +0200, Uwe Kleine-König wrote:
> The size field in the window control register occupies bits 31:16. So
> adapt ARMADA_370_XP_DDR_SIZE_MASK accordingly. This fixes detection of
> RAM chips smaller than 32 MiB and so probably doesn't affect any
> supported machine.
>
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> ---
> arch/arm/mach-mvebu/common.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied, thanks
Sascha
>
> diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c
> index 06bfb7261544..fa971da11e75 100644
> --- a/arch/arm/mach-mvebu/common.c
> +++ b/arch/arm/mach-mvebu/common.c
> @@ -47,7 +47,7 @@
> #define ARMADA_370_XP_SDRAM_BASE (IOMEM(MVEBU_REMAP_INT_REG_BASE) + 0x20000)
> #define ARMADA_370_XP_DDR_SIZE_CSn(n) (0x184 + ((n) * 0x8))
> #define ARMADA_370_XP_DDR_SIZE_ENABLED BIT(0)
> -#define ARMADA_370_XP_DDR_SIZE_MASK 0xff000000
> +#define ARMADA_370_XP_DDR_SIZE_MASK 0xffff0000
>
> /*
> * Marvell MVEBU SoC id and revision can be read from any PCIe
> --
> 2.11.0
>
>
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prev parent reply other threads:[~2017-06-13 7:23 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-12 22:37 Uwe Kleine-König
2017-06-13 7:23 ` Sascha Hauer [this message]
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