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From: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
To: barebox@lists.infradead.org
Cc: andrey.gusakov@cogentembedded.com
Subject: [PATCH v1 08/10] video: tc358767: optimize DPCD register write
Date: Wed,  5 Jul 2017 20:18:11 +0300	[thread overview]
Message-ID: <20170705171813.17527-9-andrey.gusakov@cogentembedded.com> (raw)
In-Reply-To: <20170705171813.17527-1-andrey.gusakov@cogentembedded.com>

Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
---
 drivers/video/tc358767.c | 24 +++++++++++++-----------
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/video/tc358767.c b/drivers/video/tc358767.c
index cd56bb4f4..246b49e07 100644
--- a/drivers/video/tc358767.c
+++ b/drivers/video/tc358767.c
@@ -35,6 +35,7 @@
 #include <asm-generic/div64.h>
 
 #define DP_LINK_BW_SET			0x100
+#define DP_ENHANCED_FRAME_EN		(1 << 7)
 #define DP_TRAINING_PATTERN_SET		0x102
 #define TRAINING_LANE0_SET		0x103
 
@@ -892,7 +893,7 @@ static int tc_main_link_setup(struct tc_data *tc)
 	bool ready;
 	u32 value;
 	int ret;
-	u8 tmp[8];
+	u8 tmp[16];
 
 	/* display mode should be set at this point */
 	if (!tc->mode)
@@ -993,21 +994,22 @@ static int tc_main_link_setup(struct tc_data *tc)
 	/* LANE_COUNT_SET */
 	tmp[1] = tc->link.lanes;
 	if (tc->link.enhanced)
-		tmp[1] |= (1 << 7);
-	ret = tc_aux_write(tc, DP_LINK_BW_SET, tmp, 2);
-	if (ret)
-		goto err_dpcd_write;
+		tmp[1] |= DP_ENHANCED_FRAME_EN;
 
-	/* TRAINING_LANE0_SET .. TRAINING_LANE3_SET */
-	tmp[0] = 0x00;
-	tmp[1] = 0x00;
+	/* TRAINING_PATTERN_SET */
 	tmp[2] = 0x00;
+	/* TRAINING_LANE0_SET .. TRAINING_LANE3_SET */
 	tmp[3] = 0x00;
+	tmp[4] = 0x00;
+	tmp[5] = 0x00;
+	tmp[6] = 0x00;
 	/* DOWNSPREAD_CTRL */
-	tmp[4] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
+	tmp[7] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
 	/* MAIN_LINK_CHANNEL_CODING_SET */
-	tmp[5] = tc->link.coding8b10b ? DP_SET_ANSI_8B10B : 0x00;
-	ret = tc_aux_write(tc, TRAINING_LANE0_SET, tmp, 6);
+	tmp[8] = tc->link.coding8b10b ? DP_SET_ANSI_8B10B : 0x00;
+
+	/* DP_LINK_BW_SET .. MAIN_LINK_CHANNEL_CODING_SET */
+	ret = tc_aux_write(tc, DP_LINK_BW_SET, tmp, 9);
 	if (ret)
 		goto err_dpcd_write;
 
-- 
2.13.0


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  parent reply	other threads:[~2017-07-05 17:17 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-05 17:18 [PATCH v1 00/10] video: tc358767: fixes and improvements Andrey Gusakov
2017-07-05 17:18 ` [PATCH v1 01/10] video: tc358767: fix EDID read for DP displays Andrey Gusakov
2017-07-05 17:18 ` [PATCH v1 02/10] video: tc358767: fix DP0_MISC register set Andrey Gusakov
2017-07-05 17:18 ` [PATCH v1 03/10] video: tc358767: fix timing calculation Andrey Gusakov
2017-07-05 17:18 ` [PATCH v1 04/10] video: tc358767: fix AUXDATAn registers access during write Andrey Gusakov
2017-07-05 17:18 ` [PATCH v1 05/10] video: tc358767: do not fail if sink supports more than 2 lanes Andrey Gusakov
2017-07-05 17:18 ` [PATCH v1 06/10] video: tc358767: support newer DPCD revisions and higher data rates Andrey Gusakov
2017-07-05 17:18 ` [PATCH v1 07/10] video: tc358767: optimize aux i2c bus checks Andrey Gusakov
2017-07-05 17:18 ` Andrey Gusakov [this message]
2017-07-05 17:18 ` [PATCH v1 09/10] video: tc358767: filter out modes with too high pixelclock Andrey Gusakov
2017-07-05 17:18 ` [PATCH v1 10/10] video: tc358767: accept any hsync and vsync polatiry Andrey Gusakov
2017-07-06 12:34 ` [PATCH v1 00/10] video: tc358767: fixes and improvements Lucas Stach

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