* [PATCH v2 01/13] MIPS: ath79: provide CONFIG_SOC_QCA_AR9331 option
@ 2017-08-07 14:39 Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 02/13] MIPS: ath79: add initial QCA AR9344 SoC support Oleksij Rempel
` (12 more replies)
0 siblings, 13 replies; 17+ messages in thread
From: Oleksij Rempel @ 2017-08-07 14:39 UTC (permalink / raw)
To: barebox; +Cc: Oleksij Rempel
QCA AR9331 and QCA AR9344 have some similar part but different uart engines.
We need this flag to provide common debug_ll support.
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
---
arch/mips/mach-ath79/Kconfig | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index 9b8e3946e..f2eae2532 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -4,17 +4,22 @@ config ARCH_TEXT_BASE
hex
default 0xa0800000
+config SOC_QCA_AR9331
+ bool
+
choice
prompt "Board type"
config BOARD_TPLINK_MR3020
bool "TP-LINK MR3020"
+ select SOC_QCA_AR9331
select HAVE_PBL_IMAGE
select HAVE_IMAGE_COMPRESSION
select HAS_NMON
config BOARD_BLACK_SWIFT
bool "Black Swift"
+ select SOC_QCA_AR9331
select HAVE_PBL_IMAGE
select HAVE_IMAGE_COMPRESSION
select HAS_NMON
--
2.11.0
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 02/13] MIPS: ath79: add initial QCA AR9344 SoC support
2017-08-07 14:39 [PATCH v2 01/13] MIPS: ath79: provide CONFIG_SOC_QCA_AR9331 option Oleksij Rempel
@ 2017-08-07 14:39 ` Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 03/13] MIPS: ath79: add TP-Link WDR4300 board support Oleksij Rempel
` (11 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Oleksij Rempel @ 2017-08-07 14:39 UTC (permalink / raw)
To: barebox; +Cc: Oleksij Rempel
According to the documentation:
"The AR9344 is a highly integrated and feature-rich IEEE 802.11n 2x2 2.4/5 GHz
System-on-a-Chip (SoC) for advanced WLAN platforms.
It includes a MIPS 74Kc processor, PCI Express 1.1 Root Complex and Endpoint
interfaces, five port IEEE 802.3 Fast Ethernet Switch with MAC/PHY,
one MII/RMII/RGMII interface, one USB 2.0 MAC/PHY, and external memory
interface for serial Flash, SDRAM, DDR1 or DDR2, I2S/SPDIF-Out audio interface,
SLIC VOIP/PCM interface, two UARTs, and GPIOs that can be used for LED
controls or other general purpose interface configurations.
The AR9344 supports 802.11n operations up to 144 Mbps for 20 MHz and 300 Mbps
for 40 MHz respectively, and 802.11a/b/g data rates.
Additional features include Maximal Likelihood (ML) decoding, Low-Density
Parity Check (LDPC), Maximal Ratio Combining (MRC), Tx Beamforming (TxBF), and
On-Chip One-Time Programmable (OTP) memory."
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
---
arch/mips/dts/ar9344.dtsi | 53 ++
arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 9 +
arch/mips/mach-ath79/include/mach/debug_ll.h | 167 +------
.../mips/mach-ath79/include/mach/debug_ll_ar9331.h | 176 +++++++
.../mips/mach-ath79/include/mach/debug_ll_ar9344.h | 191 ++++++++
.../include/mach/pbl_ll_init_ar9344_1.1.h | 540 +++++++++++++++++++++
6 files changed, 978 insertions(+), 158 deletions(-)
create mode 100644 arch/mips/dts/ar9344.dtsi
create mode 100644 arch/mips/mach-ath79/include/mach/debug_ll_ar9331.h
create mode 100644 arch/mips/mach-ath79/include/mach/debug_ll_ar9344.h
create mode 100644 arch/mips/mach-ath79/include/mach/pbl_ll_init_ar9344_1.1.h
diff --git a/arch/mips/dts/ar9344.dtsi b/arch/mips/dts/ar9344.dtsi
new file mode 100644
index 000000000..0838e8d7f
--- /dev/null
+++ b/arch/mips/dts/ar9344.dtsi
@@ -0,0 +1,53 @@
+#include <dt-bindings/clock/ath79-clk.h>
+
+/ {
+ compatible = "qca,ar9344";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "mips,mips74Kc";
+ reg = <0>;
+ };
+ };
+
+ ref: ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ ranges;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart@18020000 {
+ compatible = "ns16550a", "qca,ar9344-uart0";
+ reg = <0x18020000 0x20>;
+
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ big-endian;
+
+ status = "disabled";
+ };
+
+ spi: spi@1f000000 {
+ compatible = "qca,ar7100-spi", "qca,ar9344-spi";
+ reg = <0x1f000000 0x1c>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index de96c565a..f56c3f724 100644
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -37,6 +37,15 @@
#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
#define AR933X_UART_SIZE 0x14
+#define AR934X_UART0_BASE (AR71XX_APB_BASE + 0x00020000)
+#define AR934X_UART0_SIZE 0x18
+#define AR934X_UART0_SHIFT 2
+
+/* WASP BootStrap Register */
+#define WASP_BOOTSTRAP_REG (AR71XX_RESET_BASE + 0xb0)
+#define WASP_REF_CLK_25 (1 << 4) /* 0 - 25MHz 1 - 40 MHz */
+#define WASP_RAM_TYPE(a) ((a) & 0x3)
+
/*
* RTC block
*/
diff --git a/arch/mips/mach-ath79/include/mach/debug_ll.h b/arch/mips/mach-ath79/include/mach/debug_ll.h
index 04bd3ea72..73d064a3a 100644
--- a/arch/mips/mach-ath79/include/mach/debug_ll.h
+++ b/arch/mips/mach-ath79/include/mach/debug_ll.h
@@ -1,5 +1,5 @@
/*
- * based on linux.git/drivers/tty/serial/ar933x_uart.c
+ * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
*
* This file is part of barebox.
* See file CREDITS for list of people who contributed to this project.
@@ -15,162 +15,13 @@
*
*/
-#ifndef __AR933X_DEBUG_LL__
-#define __AR933X_DEBUG_LL__
+#ifndef __MACH_ATH79_DEBUG_LL__
+#define __MACH_ATH79_DEBUG_LL__
-#include <asm/addrspace.h>
-#include <mach/ar71xx_regs.h>
+#if defined(CONFIG_SOC_QCA_AR9331)
+#include <mach/debug_ll_ar9331.h>
+#elif defined(CONFIG_SOC_QCA_AR9344)
+#include <mach/debug_ll_ar9344.h>
+#endif
-#define DEBUG_LL_UART_ADDR KSEG1ADDR(AR933X_UART_BASE)
-
-#define AR933X_UART_DATA_REG 0x00
-#define AR933X_UART_DATA_TX_RX_MASK 0xff
-#define AR933X_UART_DATA_TX_CSR 0x200
-#define AR933X_UART_DATA_RX_CSR 0x100
-
-#ifndef __ASSEMBLY__
-
-#include <io.h>
-
-/*
- * C macros
- */
-
-static inline void ar933x_debug_ll_writel(u32 b, int offset)
-{
- __raw_writel(b, (u8 *)DEBUG_LL_UART_ADDR + offset);
-}
-
-static inline u32 ar933x_debug_ll_readl(int offset)
-{
- return __raw_readl((u8 *)DEBUG_LL_UART_ADDR + offset);
-}
-
-static inline void PUTC_LL(int ch)
-{
- u32 data;
-
- /* wait transmitter ready */
- data = ar933x_debug_ll_readl(AR933X_UART_DATA_REG);
- while (!(data & AR933X_UART_DATA_TX_CSR))
- data = ar933x_debug_ll_readl(AR933X_UART_DATA_REG);
-
- data = (ch & AR933X_UART_DATA_TX_RX_MASK) | AR933X_UART_DATA_TX_CSR;
- ar933x_debug_ll_writel(data, AR933X_UART_DATA_REG);
-}
-#else /* __ASSEMBLY__ */
-/*
- * Macros for use in assembly language code
- */
-
-#define AR933X_UART_CS_REG 0x04
-#define UART_CS_REG ((KSEG1 | AR933X_UART_BASE) | AR933X_UART_CS_REG)
-#define AR933X_UART_CS_IF_MODE_S 2
-#define AR933X_UART_CS_IF_MODE_DCE 2
-#define AR933X_UART_CS_TX_READY_ORIDE BIT(7)
-#define AR933X_UART_CS_RX_READY_ORIDE BIT(8)
-
-/*
- * simple uart clock setup
- * from u-boot_mod/u-boot/cpu/mips/ar7240/hornet_serial.c
- */
-#define BAUD_CLOCK 25000000
-#define CLOCK_SCALE ((BAUD_CLOCK / (16 * CONFIG_BAUDRATE)) - 1)
-#define CLOCK_STEP 0x2000
-
-#define AR933X_UART_CLOCK_REG 0x08
-#define CLOCK_REG ((KSEG1 | AR933X_UART_BASE) | AR933X_UART_CLOCK_REG)
-
-.macro debug_ll_ar9331_init
-#ifdef CONFIG_DEBUG_LL
-
- pbl_reg_writel ((AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) \
- | AR933X_UART_CS_TX_READY_ORIDE \
- | AR933X_UART_CS_RX_READY_ORIDE), UART_CS_REG
- pbl_reg_writel ((CLOCK_SCALE << 16) | CLOCK_STEP), CLOCK_REG
-
-#endif /* CONFIG_DEBUG_LL */
-.endm
-
-/*
- * output a character in a0
- */
-.macro debug_ll_outc_a0
-#ifdef CONFIG_DEBUG_LL
- .set push
- .set reorder
-
- la t0, DEBUG_LL_UART_ADDR
-201:
- lw t1, AR933X_UART_DATA_REG(t0) /* get line status */
- andi t1, t1, AR933X_UART_DATA_TX_CSR /* check for transmitter empty */
- beqz t1, 201b /* try again */
- andi a0, a0, AR933X_UART_DATA_TX_RX_MASK
- ori a0, a0, AR933X_UART_DATA_TX_CSR
- sw a0, 0(t0) /* write the character */
- .set pop
-#endif /* CONFIG_DEBUG_LL */
-.endm
-
-/*
- * output a character
- */
-.macro debug_ll_outc chr
-#ifdef CONFIG_DEBUG_LL
- li a0, \chr
- debug_ll_outc_a0
-#endif /* CONFIG_DEBUG_LL */
-.endm
-
-/*
- * check character in input buffer
- * return value:
- * v0 = 0 no character in input buffer
- * v0 != 0 character in input buffer
- */
-/* FIXME: use tstc */
-.macro debug_ll_tstc
-#ifdef CONFIG_DEBUG_LL
- .set push
- .set reorder
-
- la t0, DEBUG_LL_UART_ADDR
-
- /* get line status and check for data present */
- lw v0, AR933X_UART_DATA_REG(t0)
- andi v0, v0, AR933X_UART_DATA_RX_CSR
-
- .set pop
-#endif /* CONFIG_DEBUG_LL */
-.endm
-
-/*
- * get character to v0
- */
-.macro debug_ll_getc
-#ifdef CONFIG_DEBUG_LL
- .set push
- .set reorder
-
- la t0, DEBUG_LL_UART_ADDR
-204:
- lw v0, AR933X_UART_DATA_REG(t0)
- andi v0, v0, AR933X_UART_DATA_RX_CSR
-
- /* try again */
- beqz v0, 204b
-
- /* read a character */
- lw v0, AR933X_UART_DATA_REG(t0)
- andi v0, v0, AR933X_UART_DATA_TX_RX_MASK
-
- /* remove the character from the FIFO */
- li t1, AR933X_UART_DATA_RX_CSR
- sw t1, AR933X_UART_DATA_REG(t0)
-
- .set pop
-#endif /* CONFIG_DEBUG_LL */
-.endm
-#endif /* __ASSEMBLY__ */
-
-#endif /* __AR933X_DEBUG_LL__ */
+#endif /* __MACH_AR9344_DEBUG_LL_H__ */
diff --git a/arch/mips/mach-ath79/include/mach/debug_ll_ar9331.h b/arch/mips/mach-ath79/include/mach/debug_ll_ar9331.h
new file mode 100644
index 000000000..04bd3ea72
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/debug_ll_ar9331.h
@@ -0,0 +1,176 @@
+/*
+ * based on linux.git/drivers/tty/serial/ar933x_uart.c
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __AR933X_DEBUG_LL__
+#define __AR933X_DEBUG_LL__
+
+#include <asm/addrspace.h>
+#include <mach/ar71xx_regs.h>
+
+#define DEBUG_LL_UART_ADDR KSEG1ADDR(AR933X_UART_BASE)
+
+#define AR933X_UART_DATA_REG 0x00
+#define AR933X_UART_DATA_TX_RX_MASK 0xff
+#define AR933X_UART_DATA_TX_CSR 0x200
+#define AR933X_UART_DATA_RX_CSR 0x100
+
+#ifndef __ASSEMBLY__
+
+#include <io.h>
+
+/*
+ * C macros
+ */
+
+static inline void ar933x_debug_ll_writel(u32 b, int offset)
+{
+ __raw_writel(b, (u8 *)DEBUG_LL_UART_ADDR + offset);
+}
+
+static inline u32 ar933x_debug_ll_readl(int offset)
+{
+ return __raw_readl((u8 *)DEBUG_LL_UART_ADDR + offset);
+}
+
+static inline void PUTC_LL(int ch)
+{
+ u32 data;
+
+ /* wait transmitter ready */
+ data = ar933x_debug_ll_readl(AR933X_UART_DATA_REG);
+ while (!(data & AR933X_UART_DATA_TX_CSR))
+ data = ar933x_debug_ll_readl(AR933X_UART_DATA_REG);
+
+ data = (ch & AR933X_UART_DATA_TX_RX_MASK) | AR933X_UART_DATA_TX_CSR;
+ ar933x_debug_ll_writel(data, AR933X_UART_DATA_REG);
+}
+#else /* __ASSEMBLY__ */
+/*
+ * Macros for use in assembly language code
+ */
+
+#define AR933X_UART_CS_REG 0x04
+#define UART_CS_REG ((KSEG1 | AR933X_UART_BASE) | AR933X_UART_CS_REG)
+#define AR933X_UART_CS_IF_MODE_S 2
+#define AR933X_UART_CS_IF_MODE_DCE 2
+#define AR933X_UART_CS_TX_READY_ORIDE BIT(7)
+#define AR933X_UART_CS_RX_READY_ORIDE BIT(8)
+
+/*
+ * simple uart clock setup
+ * from u-boot_mod/u-boot/cpu/mips/ar7240/hornet_serial.c
+ */
+#define BAUD_CLOCK 25000000
+#define CLOCK_SCALE ((BAUD_CLOCK / (16 * CONFIG_BAUDRATE)) - 1)
+#define CLOCK_STEP 0x2000
+
+#define AR933X_UART_CLOCK_REG 0x08
+#define CLOCK_REG ((KSEG1 | AR933X_UART_BASE) | AR933X_UART_CLOCK_REG)
+
+.macro debug_ll_ar9331_init
+#ifdef CONFIG_DEBUG_LL
+
+ pbl_reg_writel ((AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) \
+ | AR933X_UART_CS_TX_READY_ORIDE \
+ | AR933X_UART_CS_RX_READY_ORIDE), UART_CS_REG
+ pbl_reg_writel ((CLOCK_SCALE << 16) | CLOCK_STEP), CLOCK_REG
+
+#endif /* CONFIG_DEBUG_LL */
+.endm
+
+/*
+ * output a character in a0
+ */
+.macro debug_ll_outc_a0
+#ifdef CONFIG_DEBUG_LL
+ .set push
+ .set reorder
+
+ la t0, DEBUG_LL_UART_ADDR
+201:
+ lw t1, AR933X_UART_DATA_REG(t0) /* get line status */
+ andi t1, t1, AR933X_UART_DATA_TX_CSR /* check for transmitter empty */
+ beqz t1, 201b /* try again */
+ andi a0, a0, AR933X_UART_DATA_TX_RX_MASK
+ ori a0, a0, AR933X_UART_DATA_TX_CSR
+ sw a0, 0(t0) /* write the character */
+ .set pop
+#endif /* CONFIG_DEBUG_LL */
+.endm
+
+/*
+ * output a character
+ */
+.macro debug_ll_outc chr
+#ifdef CONFIG_DEBUG_LL
+ li a0, \chr
+ debug_ll_outc_a0
+#endif /* CONFIG_DEBUG_LL */
+.endm
+
+/*
+ * check character in input buffer
+ * return value:
+ * v0 = 0 no character in input buffer
+ * v0 != 0 character in input buffer
+ */
+/* FIXME: use tstc */
+.macro debug_ll_tstc
+#ifdef CONFIG_DEBUG_LL
+ .set push
+ .set reorder
+
+ la t0, DEBUG_LL_UART_ADDR
+
+ /* get line status and check for data present */
+ lw v0, AR933X_UART_DATA_REG(t0)
+ andi v0, v0, AR933X_UART_DATA_RX_CSR
+
+ .set pop
+#endif /* CONFIG_DEBUG_LL */
+.endm
+
+/*
+ * get character to v0
+ */
+.macro debug_ll_getc
+#ifdef CONFIG_DEBUG_LL
+ .set push
+ .set reorder
+
+ la t0, DEBUG_LL_UART_ADDR
+204:
+ lw v0, AR933X_UART_DATA_REG(t0)
+ andi v0, v0, AR933X_UART_DATA_RX_CSR
+
+ /* try again */
+ beqz v0, 204b
+
+ /* read a character */
+ lw v0, AR933X_UART_DATA_REG(t0)
+ andi v0, v0, AR933X_UART_DATA_TX_RX_MASK
+
+ /* remove the character from the FIFO */
+ li t1, AR933X_UART_DATA_RX_CSR
+ sw t1, AR933X_UART_DATA_REG(t0)
+
+ .set pop
+#endif /* CONFIG_DEBUG_LL */
+.endm
+#endif /* __ASSEMBLY__ */
+
+#endif /* __AR933X_DEBUG_LL__ */
diff --git a/arch/mips/mach-ath79/include/mach/debug_ll_ar9344.h b/arch/mips/mach-ath79/include/mach/debug_ll_ar9344.h
new file mode 100644
index 000000000..d156ce9f3
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/debug_ll_ar9344.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright (C) 2017 Oleksij Rempel <o.rempel@pengutronix.de>
+ * Copyright (C) 2012, 2013 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __AR9344_DEBUG_LL__
+#define __AR9344_DEBUG_LL__
+
+#include <asm/addrspace.h>
+#include <mach/ar71xx_regs.h>
+
+#define DEBUG_LL_UART_ADDR KSEG1ADDR(AR934X_UART0_BASE)
+#define DEBUG_LL_UART_SHIFT AR934X_UART0_SHIFT
+
+#define DEBUG_LL_UART_DIVISOR_40 (40000000 / (16 * CONFIG_BAUDRATE))
+#define DEBUG_LL_UART_DIVISOR_25 (25000000 / (16 * CONFIG_BAUDRATE))
+
+#define UART_THR (0x0 << DEBUG_LL_UART_SHIFT)
+#define UART_RBR (0x0 << DEBUG_LL_UART_SHIFT)
+#define UART_DLL (0x0 << DEBUG_LL_UART_SHIFT)
+#define UART_IER (0x1 << DEBUG_LL_UART_SHIFT)
+#define UART_DLM (0x1 << DEBUG_LL_UART_SHIFT)
+#define UART_FCR (0x2 << DEBUG_LL_UART_SHIFT)
+#define UART_LCR (0x3 << DEBUG_LL_UART_SHIFT)
+#define UART_LSR (0x5 << DEBUG_LL_UART_SHIFT)
+
+#define UART_LCR_W 0x07 /* Set UART to 8,N,2 & DLAB = 0 */
+#define UART_LCR_DLAB 0x87 /* Set UART to 8,N,2 & DLAB = 1 */
+
+#define UART_LSR_DR 0x01 /* UART received data present */
+#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
+
+#define UART_FCR_RST 0x07 /* FIFO_EN | RCVR_FIFO_RST | XMIT_FIFO_RST */
+
+#ifndef __ASSEMBLY__
+
+/*
+ * C macros
+ */
+
+#include <asm/io.h>
+
+static inline void PUTC_LL(char ch)
+{
+#ifdef CONFIG_DEBUG_LL
+ while (!(__raw_readl((u8 *)DEBUG_LL_UART_ADDR + UART_LSR) & UART_LSR_THRE))
+ ;
+ __raw_writel(ch, (u8 *)DEBUG_LL_UART_ADDR + UART_THR);
+#endif /* CONFIG_DEBUG_LL */
+}
+#else /* __ASSEMBLY__ */
+/*
+ * Macros for use in assembly language code
+ */
+
+.macro debug_ll_ar9344_init
+#ifdef CONFIG_DEBUG_LL
+
+ /* find out the ref clock */
+ li t5, KSEG1ADDR(WASP_BOOTSTRAP_REG);
+ li t6, WASP_REF_CLK_25
+ lw t7, 0(t5);
+ and t6, t7, t6
+ beq zero, t6, uart_setup_ref25_val
+ nop
+uart_setup_ref40_val:
+ li t5, DEBUG_LL_UART_DIVISOR_40
+ b 1f
+ nop
+
+uart_setup_ref25_val:
+ li t5, DEBUG_LL_UART_DIVISOR_25
+1:
+
+ la t0, DEBUG_LL_UART_ADDR
+
+ li t1, UART_LCR_DLAB /* DLAB on */
+ sw t1, UART_LCR(t0) /* Write it out */
+
+ sw t5, UART_DLL(t0) /* write low order byte */
+ li t1, 0
+ sw t1, UART_DLM(t0) /* write high order byte */
+
+ li t1, UART_LCR_W /* DLAB off */
+ sw t1, UART_LCR(t0) /* Write it out */
+
+ li t1, UART_FCR_RST /* reset FIFOs */
+ sw t1, UART_FCR(t0) /* Write it out */
+
+ li t1, 0 /* disable interrupts */
+ sw t1, UART_IER(t0) /* Write it out */
+#endif /* CONFIG_DEBUG_LL */
+.endm
+
+/*
+ * output a character in a0
+ */
+.macro debug_ll_outc_a0
+#ifdef CONFIG_DEBUG_LL
+ .set push
+ .set reorder
+
+ la t0, DEBUG_LL_UART_ADDR
+
+201: lw t1, UART_LSR(t0) /* get line status */
+ andi t1, t1, UART_LSR_THRE /* check for transmitter empty */
+ beqz t1, 201b /* try again */
+
+ sw a0, UART_THR(t0) /* write the character */
+
+ .set pop
+#endif /* CONFIG_DEBUG_LL */
+.endm
+
+/*
+ * output a character
+ */
+.macro debug_ll_outc chr
+#ifdef CONFIG_DEBUG_LL
+ li a0, \chr
+ debug_ll_outc_a0
+#endif /* CONFIG_DEBUG_LL */
+.endm
+
+/*
+ * output CR + NL
+ */
+.macro debug_ll_outnl
+#ifdef CONFIG_DEBUG_LL
+ debug_ll_outc '\r'
+ debug_ll_outc '\n'
+#endif /* CONFIG_DEBUG_LL */
+.endm
+
+/*
+ * check character in input buffer
+ * return value:
+ * v0 = 0 no character in input buffer
+ * v0 != 0 character in input buffer
+ */
+.macro debug_ll_tstc
+#ifdef CONFIG_DEBUG_LL
+ .set push
+ .set reorder
+
+ la t0, DEBUG_LL_UART_ADDR
+
+ /* get line status and check for data present */
+ lw t1, UART_LSR(t0)
+ andi v0, t1, UART_LSR_DR
+
+ .set pop
+#endif /* CONFIG_DEBUG_LL */
+.endm
+
+/*
+ * get character to v0
+ */
+.macro debug_ll_getc
+#ifdef CONFIG_DEBUG_LL
+ .set push
+ .set reorder
+
+204:
+ debug_ll_tstc
+
+ /* try again */
+ beqz v0, 204b
+
+ /* read a character */
+ lw v0, UART_RBR(t0)
+
+ .set pop
+#endif /* CONFIG_DEBUG_LL */
+.endm
+#endif /* __ASSEMBLY__ */
+
+#endif /* __INCLUDE_MIPS_ASM_DEBUG_LL_NS16550_H__ */
diff --git a/arch/mips/mach-ath79/include/mach/pbl_ll_init_ar9344_1.1.h b/arch/mips/mach-ath79/include/mach/pbl_ll_init_ar9344_1.1.h
new file mode 100644
index 000000000..594ec1155
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/pbl_ll_init_ar9344_1.1.h
@@ -0,0 +1,540 @@
+#ifndef __ASM_MACH_ATH79_PBL_LL_INIT_AR9344_1_1_H
+#define __ASM_MACH_ATH79_PBL_LL_INIT_AR9344_1_1_H
+
+#include <asm/addrspace.h>
+#include <asm/regdef.h>
+
+#define AR7240_APB_BASE (KSEG1 | 0x18000000) /* 384M */
+#define AR7240_DDR_CTL_BASE AR7240_APB_BASE+0x00000000
+#define AR7240_PLL_BASE AR7240_APB_BASE+0x00050000
+
+#define ATH_DDR_COUNT_LOC (KSEG1 | 0x1d000000)
+#define ATH_CPU_COUNT_LOC (KSEG1 | 0x1d000004)
+
+/*
+ * DDR block
+ */
+#define AR7240_DDR_CONFIG AR7240_DDR_CTL_BASE+0
+#define AR7240_DDR_CONFIG2 AR7240_DDR_CTL_BASE+4
+#define AR7240_DDR_MODE AR7240_DDR_CTL_BASE+0x08
+#define AR7240_DDR_EXT_MODE AR7240_DDR_CTL_BASE+0x0c
+#define AR7240_DDR_CONTROL AR7240_DDR_CTL_BASE+0x10
+#define AR7240_DDR_REFRESH AR7240_DDR_CTL_BASE+0x14
+#define AR7240_DDR_RD_DATA_THIS_CYCLE AR7240_DDR_CTL_BASE+0x18
+#define AR7240_DDR_TAP_CONTROL0 AR7240_DDR_CTL_BASE+0x1c
+#define AR7240_DDR_TAP_CONTROL1 AR7240_DDR_CTL_BASE+0x20
+#define AR7240_DDR_TAP_CONTROL2 AR7240_DDR_CTL_BASE+0x24
+#define AR7240_DDR_TAP_CONTROL3 AR7240_DDR_CTL_BASE+0x28
+#define AR7240_DDR_DDR2_CONFIG AR7240_DDR_CTL_BASE+0x8c
+#define AR7240_DDR_BURST AR7240_DDR_CTL_BASE+0xc4
+#define AR7240_DDR_BURST2 AR7240_DDR_CTL_BASE+0xc8
+#define AR7240_AHB_MASTER_TIMEOUT AR7240_DDR_CTL_BASE+0xcc
+#define AR7240_DDR_CTL_CONFIG AR7240_DDR_CTL_BASE+0x108
+#define AR7240_DDR_DEBUG_RD_CNTL AR7240_DDR_CTL_BASE+0x118
+
+#define AR934X_CPU_PLL_DITHER AR7240_PLL_BASE+0x0048
+
+#define AR934X_CPU_PLL_CONFIG AR7240_PLL_BASE+0x0000
+#define AR934X_DDR_PLL_CONFIG AR7240_PLL_BASE+0x0004
+#define AR934X_CPU_DDR_CLOCK_CONTROL AR7240_PLL_BASE+0x0008
+#define AR934X_DDR_PLL_DITHER AR7240_PLL_BASE+0x0044
+
+#define CPU_DPLL3_ADDRESS (KSEG1 | 0x181161c8)
+#define CPU_DPLL4_ADDRESS (KSEG1 | 0x181161cc)
+#define DDR_DPLL3_ADDRESS (KSEG1 | 0x18116248)
+#define DDR_DPLL4_ADDRESS (KSEG1 | 0x1811624c)
+
+#define DPLL2_ADDRESS_c4 (KSEG1 | 0x181161c4)
+#define DPLL2_ADDRESS_44 (KSEG1 | 0x18116244)
+#define DPLL3_ADDRESS_88 (KSEG1 | 0x18116188)
+
+#define CPU_PLL_CONFIG_NINT_VAL_40 0x380
+#define DDR_PLL_CONFIG_NINT_VAL_40 0x3000
+#define CPU_PLL_NFRAC_40 0
+#define DDR_PLL_NFRAC_40 0
+
+#define CPU_PLL_CONFIG_NINT_VAL_25 0x580
+#define DDR_PLL_CONFIG_NINT_VAL_25 0x4c00
+#define CPU_PLL_NFRAC_25 0x659
+#define DDR_PLL_NFRAC_25 0x330cc
+
+#define CPU_PLL_DITHER_DITHER_EN_LSB 31
+#define CPU_PLL_DITHER_DITHER_EN_MASK 0x80000000
+#define CPU_PLL_DITHER_DITHER_EN_SET(x) \
+ (((x) << CPU_PLL_DITHER_DITHER_EN_LSB) \
+ & CPU_PLL_DITHER_DITHER_EN_MASK)
+
+#define CPU_PLL_DITHER_NFRAC_STEP_LSB 12
+#define CPU_PLL_DITHER_NFRAC_STEP_MASK 0x0003f000
+#define CPU_PLL_DITHER_NFRAC_STEP_SET(x) \
+ (((x) << CPU_PLL_DITHER_NFRAC_STEP_LSB) \
+ & CPU_PLL_DITHER_NFRAC_STEP_MASK)
+
+#define CPU_PLL_DITHER_UPDATE_COUNT_LSB 18
+#define CPU_PLL_DITHER_UPDATE_COUNT_MASK 0x00fc0000
+#define CPU_PLL_DITHER_UPDATE_COUNT_SET(x) \
+ (((x) << CPU_PLL_DITHER_UPDATE_COUNT_LSB) \
+ & CPU_PLL_DITHER_UPDATE_COUNT_MASK)
+
+#define DDR_PLL_DITHER_DITHER_EN_LSB 31
+#define DDR_PLL_DITHER_DITHER_EN_MASK 0x80000000
+#define DDR_PLL_DITHER_DITHER_EN_SET(x) \
+ (((x) << DDR_PLL_DITHER_DITHER_EN_LSB) \
+ & DDR_PLL_DITHER_DITHER_EN_MASK)
+
+#define DDR_PLL_DITHER_NFRAC_STEP_LSB 20
+#define DDR_PLL_DITHER_NFRAC_STEP_MASK 0x07f00000
+#define DDR_PLL_DITHER_NFRAC_STEP_SET(x) \
+ (((x) << DDR_PLL_DITHER_NFRAC_STEP_LSB) \
+ & DDR_PLL_DITHER_NFRAC_STEP_MASK)
+
+#define DDR_PLL_DITHER_UPDATE_COUNT_LSB 27
+#define DDR_PLL_DITHER_UPDATE_COUNT_MASK 0x78000000
+#define DDR_PLL_DITHER_UPDATE_COUNT_SET(x) \
+ (((x) << DDR_PLL_DITHER_UPDATE_COUNT_LSB) \
+ & DDR_PLL_DITHER_UPDATE_COUNT_MASK)
+
+#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB 2
+#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK 0x00000004
+#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(x) \
+ (((x) << CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB) \
+ & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK)
+
+#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB 3
+#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK 0x00000008
+#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(x) \
+ (((x) << CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) \
+ & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK)
+
+#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB 4
+#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK 0x00000010
+#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(x) \
+ (((x) << CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB) \
+ & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK)
+
+#define CPU_DPLL3_DO_MEAS_LSB 30
+#define CPU_DPLL3_DO_MEAS_MASK 0x40000000
+#define CPU_DPLL3_DO_MEAS_SET(x) \
+ (((x) << CPU_DPLL3_DO_MEAS_LSB) & CPU_DPLL3_DO_MEAS_MASK)
+
+#define CPU_DPLL3_SQSUM_DVC_LSB 3
+#define CPU_DPLL3_SQSUM_DVC_MASK 0x007ffff8
+#define CPU_DPLL3_SQSUM_DVC_SET(x) \
+ (((x) << CPU_DPLL3_SQSUM_DVC_LSB) & CPU_DPLL3_SQSUM_DVC_MASK)
+
+#define CPU_DPLL4_MEAS_DONE_LSB 3
+#define CPU_DPLL4_MEAS_DONE_MASK 0x00000008
+#define CPU_DPLL4_MEAS_DONE_SET(x) \
+ (((x) << CPU_DPLL4_MEAS_DONE_LSB) & CPU_DPLL4_MEAS_DONE_MASK)
+
+#define CPU_PLL_CONFIG_PLLPWD_LSB 30
+#define CPU_PLL_CONFIG_PLLPWD_MASK 0x40000000
+#define CPU_PLL_CONFIG_PLLPWD_SET(x) \
+ (((x) << CPU_PLL_CONFIG_PLLPWD_LSB) & CPU_PLL_CONFIG_PLLPWD_MASK)
+
+#define DDR_DPLL3_DO_MEAS_LSB 30
+#define DDR_DPLL3_DO_MEAS_MASK 0x40000000
+#define DDR_DPLL3_DO_MEAS_SET(x) \
+ (((x) << DDR_DPLL3_DO_MEAS_LSB) & DDR_DPLL3_DO_MEAS_MASK)
+
+#define DDR_DPLL3_SQSUM_DVC_LSB 3
+#define DDR_DPLL3_SQSUM_DVC_MASK 0x007ffff8
+#define DDR_DPLL3_SQSUM_DVC_SET(x) \
+ (((x) << DDR_DPLL3_SQSUM_DVC_LSB) & DDR_DPLL3_SQSUM_DVC_MASK)
+
+#define DDR_DPLL4_MEAS_DONE_LSB 3
+#define DDR_DPLL4_MEAS_DONE_MASK 0x00000008
+#define DDR_DPLL4_MEAS_DONE_SET(x) \
+ (((x) << DDR_DPLL4_MEAS_DONE_LSB) & DDR_DPLL4_MEAS_DONE_MASK)
+
+#define DDR_PLL_CONFIG_PLLPWD_LSB 30
+#define DDR_PLL_CONFIG_PLLPWD_MASK 0x40000000
+#define DDR_PLL_CONFIG_PLLPWD_SET(x) \
+ (((x) << DDR_PLL_CONFIG_PLLPWD_LSB) & DDR_PLL_CONFIG_PLLPWD_MASK)
+
+/*
+ * Helper macros.
+ * These Clobber t7, t8 and t9
+ */
+#define set_val(_reg, _mask, _val) \
+ li t7, KSEG1ADDR(_reg); \
+ lw t8, 0(t7); \
+ li t9, ~_mask; \
+ and t8, t8, t9; \
+ li t9, _val; \
+ or t8, t8, t9; \
+ sw t8, 0(t7)
+
+#define cpu_ddr_control_set(_mask, _val) \
+ set_val(AR934X_CPU_DDR_CLOCK_CONTROL, _mask, _val)
+
+#define set_srif_pll_reg(reg, _r) \
+ li t7, KSEG1ADDR(reg); \
+ sw _r, 0(t7);
+
+#define inc_loop_count(loc) \
+ li t9, loc; \
+ lw t7, 0(t9); \
+ addi t7, t7, 1; \
+ sw t7, 0(t9);
+
+#define clear_loop_count(loc) \
+ li t9, loc; \
+ sw zero, 0(t9);
+
+/******************************************************************************
+ * first level initialization:
+ *
+ * 0) If clock cntrl reset switch is already set, we're recovering from
+ * "divider reset"; goto 3.
+ * 1) Setup divide ratios.
+ * 2) Reset.
+ * 3) Setup pll's, wait for lock.
+ *
+ *****************************************************************************/
+
+.macro pbl_ar9344_v11_pll_config
+ .set push
+ .set noreorder
+
+ pbl_reg_writel 0x13210f00, DPLL2_ADDRESS_c4
+ pbl_reg_writel 0x03000000, CPU_DPLL3_ADDRESS
+ pbl_reg_writel 0x13210f00, DPLL2_ADDRESS_44
+ pbl_reg_writel 0x03000000, DDR_DPLL3_ADDRESS
+ pbl_reg_writel 0x03000000, DPLL3_ADDRESS_88
+
+ li t5, KSEG1ADDR(WASP_BOOTSTRAP_REG);
+ li t6, WASP_REF_CLK_25
+ lw t7, 0(t5);
+ and t6, t7, t6
+ beq zero, t6, setup_ref25_val
+ nop
+
+setup_ref40_val:
+ li t5, CPU_PLL_CONFIG_NINT_VAL_40
+ li t6, DDR_PLL_CONFIG_NINT_VAL_40
+ li t7, CPU_PLL_NFRAC_40
+ li t9, DDR_PLL_NFRAC_40
+ b 1f
+ nop
+
+setup_ref25_val:
+ li t5, CPU_PLL_CONFIG_NINT_VAL_25
+ li t6, DDR_PLL_CONFIG_NINT_VAL_25
+ li t7, CPU_PLL_NFRAC_25
+ li t9, DDR_PLL_NFRAC_25
+
+1:
+ li t4, (CPU_PLL_DITHER_DITHER_EN_SET(0) | \
+ CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \
+ CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf));
+ or t4, t4, t7
+
+ li t8, 0x21000;
+ or t5, t5, t8
+
+ li t8, 0x210000;
+ or t6, t6, t8
+
+ li t3, (DDR_PLL_DITHER_DITHER_EN_SET(0) | \
+ DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \
+ DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf));
+
+ or t3, t3, t9
+
+pll_bypass_set:
+ /* reg, mask, val */
+ /* 0xb8050008, 0xfffffffb, 0x4 */
+ cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK, \
+ CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1));
+ /* 0xb8050008, 0xfffffff7, 0x8 */
+ cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK, \
+ CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1));
+ /* 0xb8050008, 0xffffffef, 0x10 */
+ cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK, \
+ CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1));
+
+init_cpu_pll:
+ li t7, AR934X_CPU_PLL_CONFIG
+ li t8, CPU_PLL_CONFIG_PLLPWD_SET(1)
+ or t8, t8, t5
+ sw t8, 0(t7);
+
+init_ddr_pll:
+ li t7, AR934X_DDR_PLL_CONFIG
+ li t8, DDR_PLL_CONFIG_PLLPWD_SET(1)
+ or t8, t8, t6
+ sw t8, 0(t7);
+
+init_ahb_pll:
+ pbl_reg_writel 0x0130801C, AR934X_CPU_DDR_CLOCK_CONTROL
+
+srif_set:
+ /* Use built in values, based on ref clock */
+ li t5, KSEG1ADDR(WASP_BOOTSTRAP_REG);
+ li t6, WASP_REF_CLK_25
+ lw t7, 0(t5);
+ and t6, t7, t6
+ /* jump to 25ref clk */
+ beq zero, t6, 1f
+ nop
+
+ /* refdiv nint nfrac */
+ /* cpu freq = (40 MHz refclk/refdiv 8) * Nint */
+ li t4, ((0x8 << 27) | (112 << 18) | 0);
+ /* ddr freq = (40 MHz refclk/refdiv 8) * Nint */
+ li t5, ((0x8 << 27) | (90 << 18) | 0);
+ b 2f
+ nop
+1:
+
+ /* cpu freq = (25 MHz refclk/refdiv 5) * Nint */
+ li t4, ((0x5 << 27) | (112 << 18) | 0);
+ /* ddr freq = (25 MHz refclk/refdiv 5) * Nint */
+ li t5, ((0x5 << 27) | (90 << 18) | 0);
+
+2:
+
+ /* 0 to 0xbd000004 */
+ clear_loop_count(ATH_CPU_COUNT_LOC);
+
+cpu_pll_is_not_locked:
+ inc_loop_count(ATH_CPU_COUNT_LOC);
+
+ pbl_reg_writel 0x10810F00, DPLL2_ADDRESS_c4
+
+ set_srif_pll_reg(0xb81161c0, t4);
+
+ pbl_reg_writel 0xd0810f00, DPLL2_ADDRESS_c4
+ pbl_reg_writel 0x03000000, CPU_DPLL3_ADDRESS
+ pbl_reg_writel 0xd0800f00, DPLL2_ADDRESS_c4
+
+cpu_clear_do_meas1:
+ li t7, KSEG1ADDR(CPU_DPLL3_ADDRESS)
+ lw t8, 0(t7)
+ li t9, ~CPU_DPLL3_DO_MEAS_SET(1)
+ and t8, t8, t9
+ sw t8, 0(t7)
+
+cpu_set_do_meas:
+ li t7, KSEG1ADDR(CPU_DPLL3_ADDRESS)
+ lw t8, 0(t7)
+ li t9, CPU_DPLL3_DO_MEAS_SET(1)
+ or t8, t8, t9
+ sw t8, 0(t7)
+
+ li t7, KSEG1ADDR(CPU_DPLL4_ADDRESS)
+cpu_wait_for_meas_done:
+ lw t8, 0(t7)
+ andi t8, t8, CPU_DPLL4_MEAS_DONE_SET(1)
+ beqz t8, cpu_wait_for_meas_done
+ nop
+
+cpu_clear_do_meas2:
+ li t7, KSEG1ADDR(CPU_DPLL3_ADDRESS)
+ lw t8, 0(t7)
+ li t9, ~CPU_DPLL3_DO_MEAS_SET(1)
+ and t8, t8, t9
+ sw t8, 0(t7)
+
+cpu_read_sqsum_dvc:
+ li t7, KSEG1ADDR(CPU_DPLL3_ADDRESS)
+ lw t8, 0(t7)
+ li t9, CPU_DPLL3_SQSUM_DVC_MASK
+ and t8, t8, t9
+ sra t8, t8, CPU_DPLL3_SQSUM_DVC_LSB
+ li t9, 0x40000
+ subu t8, t8, t9
+ bgez t8, cpu_pll_is_not_locked
+ nop
+
+ /* DDR */
+ clear_loop_count(ATH_DDR_COUNT_LOC)
+
+ddr_pll_is_not_locked:
+
+ inc_loop_count(ATH_DDR_COUNT_LOC)
+
+ pbl_reg_writel 0x10810F00, DPLL2_ADDRESS_44
+
+ set_srif_pll_reg(0xb8116240, t5);
+
+ pbl_reg_writel 0xD0810F00, DPLL2_ADDRESS_44
+ pbl_reg_writel 0x03000000, DDR_DPLL3_ADDRESS
+ pbl_reg_writel 0xD0800F00, DPLL2_ADDRESS_44
+
+ddr_clear_do_meas1:
+ li t7, DDR_DPLL3_ADDRESS
+ lw t8, 0(t7)
+ li t9, ~DDR_DPLL3_DO_MEAS_SET(1)
+ and t8, t8, t9
+ sw t8, 0(t7)
+
+
+ddr_set_do_meas:
+ li t7, DDR_DPLL3_ADDRESS
+ lw t8, 0(t7)
+ li t9, DDR_DPLL3_DO_MEAS_SET(1)
+ or t8, t8, t9
+ sw t8, 0(t7)
+
+ li t7, KSEG1ADDR(DDR_DPLL4_ADDRESS)
+ddr_wait_for_meas_done:
+ lw t8, 0(t7)
+ andi t8, t8, DDR_DPLL4_MEAS_DONE_SET(1)
+ beqz t8, ddr_wait_for_meas_done
+ nop
+
+ddr_clear_do_meas2:
+ li t7, DDR_DPLL3_ADDRESS
+ lw t8, 0(t7)
+ li t9, ~DDR_DPLL3_DO_MEAS_SET(1)
+ and t8, t8, t9
+ sw t8, 0(t7)
+
+ddr_read_sqsum_dvc:
+ li t7, DDR_DPLL3_ADDRESS
+ lw t8, 0(t7)
+ li t9, DDR_DPLL3_SQSUM_DVC_MASK
+ and t8, t8, t9
+ sra t8, t8, DDR_DPLL3_SQSUM_DVC_LSB
+ li t9, 0x40000
+ subu t8, t8, t9
+ bgez t8, ddr_pll_is_not_locked
+ nop
+
+pll_bypass_unset:
+ cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK, \
+ CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(0));
+ cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK, \
+ CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(0));
+ cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK, \
+ CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(0));
+
+ddr_pll_dither_unset:
+ pbl_reg_writel 0x78180200, AR934X_DDR_PLL_DITHER
+
+cpu_pll_dither_unset:
+ li t7, AR934X_CPU_PLL_DITHER
+ sw t4, 0(t7)
+
+ .set pop
+.endm
+
+#define AR9344_DDR_DDR2_CONFIG AR7240_DDR_CTL_BASE+0xb8
+#define CFG_934X_DDR2_EN_TWL_VAL 0x0e59
+#define USEC_MULT 1
+#define CFG_934X_DDR2_CONFIG_VAL 0xc7d48cd0
+#define CFG_934X_DDR2_CONFIG2_VAL 0x9dd0e6a8
+#define CFG_934X_DDR2_MODE_VAL_INIT 0x133
+#define CFG_934X_DDR2_EXT_MODE_VAL_INIT 0x382
+#define CFG_934X_DDR2_EXT_MODE_VAL 0x402
+#define CFG_934X_DDR2_MODE_VAL 0x33
+#define CFG_DDR_REFRESH_VAL 0x4270
+#define CFG_934X_DDR2_TAP_VAL 0x10012
+#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32 0xff
+#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16 0xffff
+
+.macro pbl_ar9344_v11_ddr2_config
+ .set push
+ .set noreorder
+
+ pbl_reg_writel CFG_934X_DDR2_EN_TWL_VAL, AR9344_DDR_DDR2_CONFIG
+ pbl_sleep t2, 100 * USEC_MULT
+
+ pbl_reg_writel 0x10, AR7240_DDR_CONTROL
+ pbl_sleep t2, 10 * USEC_MULT
+
+ pbl_reg_writel 0x20, AR7240_DDR_CONTROL
+ pbl_sleep t2, 10 * USEC_MULT
+
+ li t5, KSEG1ADDR(WASP_BOOTSTRAP_REG);
+ li t6, BIT(3)
+ lw t7, 0(t5);
+ and t6, t7, t6
+ beq zero, t6, setup_16bit_1
+ nop
+setup_32bit_1:
+ pbl_reg_writel BIT(6), AR7240_DDR_CTL_CONFIG
+ b 1f
+ nop
+setup_16bit_1:
+ pbl_reg_clr BIT(6), AR7240_DDR_CTL_CONFIG
+1:
+
+ pbl_sleep t2, 10 * USEC_MULT
+
+ pbl_reg_writel CFG_934X_DDR2_CONFIG_VAL, AR7240_DDR_CONFIG
+ pbl_sleep t2, 100 * USEC_MULT
+
+ pbl_reg_writel CFG_934X_DDR2_CONFIG2_VAL, AR7240_DDR_CONFIG2
+ pbl_sleep t2, 100 * USEC_MULT
+
+ pbl_reg_writel 0x8, AR7240_DDR_CONTROL
+ pbl_sleep t2, 10 * USEC_MULT
+
+ pbl_reg_writel CFG_934X_DDR2_MODE_VAL_INIT, AR7240_DDR_MODE
+ pbl_sleep t2, 1000 * USEC_MULT
+
+ pbl_reg_writel 0x1, AR7240_DDR_CONTROL
+ pbl_sleep t2, 10 * USEC_MULT
+
+ pbl_reg_writel CFG_934X_DDR2_EXT_MODE_VAL_INIT, AR7240_DDR_EXT_MODE
+ pbl_sleep t2, 100 * USEC_MULT
+
+ pbl_reg_writel 0x2, AR7240_DDR_CONTROL
+ pbl_sleep t2, 10 * USEC_MULT
+
+ pbl_reg_writel CFG_934X_DDR2_EXT_MODE_VAL, AR7240_DDR_EXT_MODE
+ pbl_sleep t2, 100 * USEC_MULT
+
+ pbl_reg_writel 0x2, AR7240_DDR_CONTROL
+ pbl_sleep t2, 10 * USEC_MULT
+
+ pbl_reg_writel 0x8, AR7240_DDR_CONTROL
+ pbl_sleep t2, 10 * USEC_MULT
+
+ pbl_reg_writel CFG_934X_DDR2_MODE_VAL, AR7240_DDR_MODE
+ pbl_sleep t2, 100 * USEC_MULT
+
+ pbl_reg_writel 0x1, AR7240_DDR_CONTROL
+ pbl_sleep t2, 10 * USEC_MULT
+
+ pbl_reg_writel CFG_DDR_REFRESH_VAL, AR7240_DDR_REFRESH
+ pbl_sleep t2, 100 * USEC_MULT
+
+ pbl_reg_writel CFG_934X_DDR2_TAP_VAL, AR7240_DDR_TAP_CONTROL0
+ pbl_reg_writel CFG_934X_DDR2_TAP_VAL, AR7240_DDR_TAP_CONTROL1
+
+
+ li t5, KSEG1ADDR(WASP_BOOTSTRAP_REG);
+ li t6, BIT(3)
+ lw t7, 0(t5);
+ and t6, t7, t6
+ beq zero, t6, setup_16bit_2
+ nop
+setup_32bit_2:
+ pbl_reg_writel CFG_934X_DDR2_TAP_VAL, AR7240_DDR_TAP_CONTROL2
+ pbl_reg_writel CFG_934X_DDR2_TAP_VAL, AR7240_DDR_TAP_CONTROL3
+ pbl_reg_writel CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32, AR7240_DDR_RD_DATA_THIS_CYCLE
+ b 1f
+ nop
+setup_16bit_2:
+ pbl_reg_writel CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16, AR7240_DDR_RD_DATA_THIS_CYCLE
+
+1:
+ pbl_sleep t2, 100 * USEC_MULT
+
+ pbl_reg_writel 0x74444444, AR7240_DDR_BURST
+ pbl_sleep t2, 100 * USEC_MULT
+
+ pbl_reg_writel 0x222, AR7240_DDR_BURST2
+ pbl_sleep t2, 100 * USEC_MULT
+
+ pbl_reg_writel 0xfffff, AR7240_AHB_MASTER_TIMEOUT
+ pbl_sleep t2, 100 * USEC_MULT
+
+ .set pop
+.endm
+
+#endif /* __ASM_MACH_ATH79_PBL_LL_INIT_AR9344_1_1_H */
--
2.11.0
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 03/13] MIPS: ath79: add TP-Link WDR4300 board support
2017-08-07 14:39 [PATCH v2 01/13] MIPS: ath79: provide CONFIG_SOC_QCA_AR9331 option Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 02/13] MIPS: ath79: add initial QCA AR9344 SoC support Oleksij Rempel
@ 2017-08-07 14:39 ` Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 04/13] MIPS: add virt_to_phys() and phys_to_virt() Oleksij Rempel
` (10 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Oleksij Rempel @ 2017-08-07 14:39 UTC (permalink / raw)
To: barebox; +Cc: Oleksij Rempel
This provides low level initialization of pll and ddr2. Resulting binary
should work from SRAM, DDR2 and SPI flash. If started from DDR2 RAM
level initialization will skipped.
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
---
arch/mips/Makefile | 1 +
arch/mips/boards/tplink-wdr4300/Makefile | 1 +
arch/mips/boards/tplink-wdr4300/board.c | 28 ++++++++
.../tplink-wdr4300/include/board/board_pbl_start.h | 62 +++++++++++++++++
arch/mips/configs/tplink-wdr4300_defconfig | 78 ++++++++++++++++++++++
arch/mips/dts/ar9344_tl_wdr4300.dts | 63 +++++++++++++++++
arch/mips/mach-ath79/Kconfig | 10 +++
7 files changed, 243 insertions(+)
create mode 100644 arch/mips/boards/tplink-wdr4300/Makefile
create mode 100644 arch/mips/boards/tplink-wdr4300/board.c
create mode 100644 arch/mips/boards/tplink-wdr4300/include/board/board_pbl_start.h
create mode 100644 arch/mips/configs/tplink-wdr4300_defconfig
create mode 100644 arch/mips/dts/ar9344_tl_wdr4300.dts
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 75761b5e7..dd5ceea20 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -80,6 +80,7 @@ board-$(CONFIG_BOARD_NETGEAR_WG102) := netgear-wg102
machine-$(CONFIG_MACH_MIPS_ATH79) := ath79
board-$(CONFIG_BOARD_TPLINK_MR3020) := tplink-mr3020
+board-$(CONFIG_BOARD_TPLINK_WDR4300) := tplink-wdr4300
board-$(CONFIG_BOARD_BLACK_SWIFT) := black-swift
machine-$(CONFIG_MACH_MIPS_BCM47XX) := bcm47xx
diff --git a/arch/mips/boards/tplink-wdr4300/Makefile b/arch/mips/boards/tplink-wdr4300/Makefile
new file mode 100644
index 000000000..dcfc2937d
--- /dev/null
+++ b/arch/mips/boards/tplink-wdr4300/Makefile
@@ -0,0 +1 @@
+obj-y += board.o
diff --git a/arch/mips/boards/tplink-wdr4300/board.c b/arch/mips/boards/tplink-wdr4300/board.c
new file mode 100644
index 000000000..d6126fcb6
--- /dev/null
+++ b/arch/mips/boards/tplink-wdr4300/board.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2017 Oleksij Rempel <o.rempel@pengutronix.de>
+ * Copyright (C) 2014 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+
+static int model_hostname_init(void)
+{
+ barebox_set_hostname("wdr4300");
+
+ return 0;
+}
+postcore_initcall(model_hostname_init);
diff --git a/arch/mips/boards/tplink-wdr4300/include/board/board_pbl_start.h b/arch/mips/boards/tplink-wdr4300/include/board/board_pbl_start.h
new file mode 100644
index 000000000..7d4ee4bab
--- /dev/null
+++ b/arch/mips/boards/tplink-wdr4300/include/board/board_pbl_start.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2017 Oleksij Rempel <o.rempel@pengutronix.de>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <mach/debug_ll_ar9344.h>
+#include <asm/pbl_macros.h>
+#include <mach/pbl_macros.h>
+#include <mach/pbl_ll_init_ar9344_1.1.h>
+#include <asm/pbl_nmon.h>
+
+ .macro board_pbl_start
+ .set push
+ .set noreorder
+
+ mips_barebox_10h
+
+ debug_ll_ar9344_init
+
+ debug_ll_outc '1'
+
+ hornet_mips24k_cp0_setup
+ debug_ll_outc '2'
+
+ /* test if we are in the SRAM */
+ pbl_blt 0xbd000000 1f t8
+ debug_ll_outc '3'
+ b skip_flash_test
+ nop
+1:
+ /* test if we are in the flash */
+ pbl_blt 0xbf000000 skip_pll_ram_config t8
+ debug_ll_outc '4'
+skip_flash_test:
+
+ pbl_ar9344_v11_pll_config
+ debug_ll_outc '5'
+
+ pbl_ar9344_v11_ddr2_config
+
+skip_pll_ram_config:
+ debug_ll_outc '6'
+ debug_ll_outnl
+
+ mips_nmon
+
+ copy_to_link_location pbl_start
+
+ .set pop
+ .endm
diff --git a/arch/mips/configs/tplink-wdr4300_defconfig b/arch/mips/configs/tplink-wdr4300_defconfig
new file mode 100644
index 000000000..a277e35b1
--- /dev/null
+++ b/arch/mips/configs/tplink-wdr4300_defconfig
@@ -0,0 +1,78 @@
+CONFIG_BUILTIN_DTB=y
+CONFIG_BUILTIN_DTB_NAME="ar9344_tl_wdr3400"
+CONFIG_MACH_MIPS_ATH79=y
+CONFIG_BOARD_TPLINK_WDR4300=y
+CONFIG_PBL_IMAGE=y
+CONFIG_IMAGE_COMPRESSION_XZKERN=y
+CONFIG_MMU=y
+CONFIG_TEXT_BASE=0x81000000
+CONFIG_MALLOC_TLSF=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_CMD_DMESG=y
+CONFIG_LONGHELP=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_IMD=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_DEFAULTENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_LET=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_READF=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MM=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_LED_TRIGGER=y
+CONFIG_CMD_BAREBOX_UPDATE=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIME=y
+CONFIG_NET=y
+CONFIG_NET_NFS=y
+CONFIG_NET_NETCONSOLE=y
+CONFIG_NET_RESOLV=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_SNTP=y
+CONFIG_OFDEVICE=y
+CONFIG_OF_BAREBOX_DRIVERS=y
+CONFIG_OF_BAREBOX_ENV_IN_FS=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_NET_AG71XX=y
+CONFIG_AT803X_PHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_GPIO=y
+CONFIG_DRIVER_SPI_ATH79=y
+CONFIG_MTD=y
+# CONFIG_MTD_OOB_DEVICE is not set
+CONFIG_MTD_M25P80=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_GPIO_OF=y
+CONFIG_LED_TRIGGERS=y
+CONFIG_DIGEST_SHA224_GENERIC=y
+CONFIG_DIGEST_SHA256_GENERIC=y
diff --git a/arch/mips/dts/ar9344_tl_wdr4300.dts b/arch/mips/dts/ar9344_tl_wdr4300.dts
new file mode 100644
index 000000000..b02c1d730
--- /dev/null
+++ b/arch/mips/dts/ar9344_tl_wdr4300.dts
@@ -0,0 +1,63 @@
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9344.dtsi"
+
+/ {
+ model = "TP-Link WDR4300";
+ compatible = "tplink,tl-wdr4300";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ chosen {
+ stdout-path = &uart0;
+
+ environment@0 {
+ compatible = "barebox,environment";
+ device-path = &spiflash, "partname:barebox-environment";
+ };
+ };
+};
+
+&ref {
+ clock-frequency = <40000000>;
+};
+
+&uart0 {
+ status = "okay";
+ clock-frequency = <40000000>;
+};
+
+&spi {
+ num-chipselects = <1>;
+ status = "okay";
+
+ /* Winbond W25Q64CV SPI flash */
+ spiflash: w25q64cv@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor", "winbond,w25q64cv";
+ spi-max-frequency = <104000000>;
+ reg = <0>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "barebox-environment";
+ reg = <0x80000 0x10000>;
+ };
+ };
+};
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index f2eae2532..9fec00c98 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -7,6 +7,9 @@ config ARCH_TEXT_BASE
config SOC_QCA_AR9331
bool
+config SOC_QCA_AR9344
+ bool
+
choice
prompt "Board type"
@@ -17,6 +20,13 @@ config BOARD_TPLINK_MR3020
select HAVE_IMAGE_COMPRESSION
select HAS_NMON
+config BOARD_TPLINK_WDR4300
+ bool "TP-LINK WDR4300"
+ select SOC_QCA_AR9344
+ select HAVE_PBL_IMAGE
+ select HAVE_IMAGE_COMPRESSION
+ select HAS_NMON
+
config BOARD_BLACK_SWIFT
bool "Black Swift"
select SOC_QCA_AR9331
--
2.11.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 04/13] MIPS: add virt_to_phys() and phys_to_virt()
2017-08-07 14:39 [PATCH v2 01/13] MIPS: ath79: provide CONFIG_SOC_QCA_AR9331 option Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 02/13] MIPS: ath79: add initial QCA AR9344 SoC support Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 03/13] MIPS: ath79: add TP-Link WDR4300 board support Oleksij Rempel
@ 2017-08-07 14:39 ` Oleksij Rempel
2017-08-07 19:56 ` Peter Mamonov
2017-08-07 14:39 ` [PATCH v2 05/13] net: ath79: add ag71xx Ethernet driver Oleksij Rempel
` (9 subsequent siblings)
12 siblings, 1 reply; 17+ messages in thread
From: Oleksij Rempel @ 2017-08-07 14:39 UTC (permalink / raw)
To: barebox; +Cc: Peter Mamonov
From: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
arch/mips/include/asm/io.h | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 4bee5913a..993b30e2a 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -12,11 +12,46 @@
#include <linux/compiler.h>
#include <asm/types.h>
+#include <asm/addrspace.h>
#include <asm/byteorder.h>
void dma_flush_range(unsigned long, unsigned long);
void dma_inv_range(unsigned long, unsigned long);
+/*
+ * virt_to_phys - map virtual addresses to physical
+ * @address: address to remap
+ *
+ * The returned physical address is the physical (CPU) mapping for
+ * the memory address given. It is only valid to use this function on
+ * addresses directly mapped or allocated via kmalloc.
+ *
+ * This function does not give bus mappings for DMA transfers. In
+ * almost all conceivable cases a device driver should not be using
+ * this function
+ */
+static inline unsigned long virt_to_phys(const void *address)
+{
+ return (unsigned long)address & 0x1fffffff;
+}
+
+/*
+ * phys_to_virt - map physical address to virtual
+ * @address: address to remap
+ *
+ * The returned virtual address is a current CPU mapping for
+ * the memory address given. It is only valid to use this function on
+ * addresses that have a kernel mapping
+ *
+ * This function does not handle bus mappings for DMA transfers. In
+ * almost all conceivable cases a device driver should not be using
+ * this function
+ */
+static inline void *phys_to_virt(unsigned long address)
+{
+ return (void *)(KSEG0 | (address & 0x1fffffff));
+}
+
#define IO_SPACE_LIMIT 0
/*****************************************************************************/
--
2.11.0
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 05/13] net: ath79: add ag71xx Ethernet driver
2017-08-07 14:39 [PATCH v2 01/13] MIPS: ath79: provide CONFIG_SOC_QCA_AR9331 option Oleksij Rempel
` (2 preceding siblings ...)
2017-08-07 14:39 ` [PATCH v2 04/13] MIPS: add virt_to_phys() and phys_to_virt() Oleksij Rempel
@ 2017-08-07 14:39 ` Oleksij Rempel
2017-08-07 20:45 ` Peter Mamonov
2017-08-07 14:39 ` [PATCH v2 06/13] net: ag71xx: bit 19 should be set to 1 for GE0 Oleksij Rempel
` (8 subsequent siblings)
12 siblings, 1 reply; 17+ messages in thread
From: Oleksij Rempel @ 2017-08-07 14:39 UTC (permalink / raw)
To: barebox
From: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
Documentation/boards/mips/tplink-mr3020.rst | 7 +
arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 12 +
drivers/net/Kconfig | 7 +
drivers/net/Makefile | 1 +
drivers/net/ag71xx.c | 530 ++++++++++++++++++++++++
5 files changed, 557 insertions(+)
create mode 100644 drivers/net/ag71xx.c
diff --git a/Documentation/boards/mips/tplink-mr3020.rst b/Documentation/boards/mips/tplink-mr3020.rst
index 99101c337..4119c1e7e 100644
--- a/Documentation/boards/mips/tplink-mr3020.rst
+++ b/Documentation/boards/mips/tplink-mr3020.rst
@@ -60,6 +60,13 @@ Next, setup network on MR3020 and run ``6F01A8C0.img``, e.g.:
hornet> tftpboot 0x81000000 6F01A8C0.img
hornet> bootm 0x81000000
+WIP: Short form:
+ hornet> set ipaddr 192.168.0.2; set serverip 192.168.0.1
+ hornet> tftpboot 0x81000000 6F01A8C0.img; bootm 0x81000000
+
+u-boot_mod:
+ uboot> setenv ipaddr 192.168.1.12; setenv serverip 192.168.1.2
+ uboot> tftpboot 0x81000000 6F01A8C0.img; bootm 0x81000000
Links
-----
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index f56c3f724..31d33b3c4 100644
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -102,6 +102,8 @@
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
#define AR933X_PLL_DITHER_FRAC_REG 0x10
#define AR933X_PLL_DITHER_REG 0x14
+#define AR933X_ETHSW_CLOCK_CONTROL_REG 0x24
+#define AR933X_ETH_XMII_CONTROL_REG 0x2c
#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
@@ -125,6 +127,16 @@
#define AR933X_RESET_REG_RESET_MODULE 0x1c
#define AR933X_RESET_REG_BOOTSTRAP 0xac
+#define AR933X_RESET_GE1_MDIO BIT(23)
+#define AR933X_RESET_GE0_MDIO BIT(22)
+#define AR933X_RESET_GE1_MAC BIT(13)
+#define AR933X_RESET_WMAC BIT(11)
+#define AR933X_RESET_GE0_MAC BIT(9)
+#define AR933X_RESET_SWITCH BIT(8)
+#define AR933X_RESET_USB_HOST BIT(5)
+#define AR933X_RESET_USB_PHY BIT(4)
+#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
+
#define AR71XX_RESET_FULL_CHIP BIT(24)
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index c3980e78f..9d69b6aeb 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -204,6 +204,13 @@ config DRIVER_NET_EFI_SNP
bool "EFI SNP ethernet driver"
depends on EFI_BOOTUP
+config DRIVER_NET_AG71XX
+ bool "Atheros AG71xx ethernet driver"
+ depends on MACH_MIPS_ATH79
+ select PHYLIB
+ help
+ This option enables support for Atheros AG71XX ethernet chip.
+
config DRIVER_NET_TSE
depends on NIOS2
bool "Altera TSE ethernet driver"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 42ea208e3..86c8ac32f 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -30,3 +30,4 @@ obj-$(CONFIG_DRIVER_NET_SMC91111) += smc91111.o
obj-$(CONFIG_DRIVER_NET_TAP) += tap.o
obj-$(CONFIG_DRIVER_NET_TSE) += altera_tse.o
obj-$(CONFIG_DRIVER_NET_EFI_SNP) += efi-snp.o
+obj-$(CONFIG_DRIVER_NET_AG71XX) += ag71xx.o
diff --git a/drivers/net/ag71xx.c b/drivers/net/ag71xx.c
new file mode 100644
index 000000000..b2e066be3
--- /dev/null
+++ b/drivers/net/ag71xx.c
@@ -0,0 +1,530 @@
+/*
+ * Atheros AR71xx built-in ethernet mac driver
+ *
+ * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * Based on Atheros' AG7100 driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <net.h>
+#include <dma.h>
+#include <init.h>
+#include <io.h>
+#include <linux/err.h>
+#include <linux/phy.h>
+#include <of_net.h>
+#include <of_address.h>
+
+#include <mach/ath79.h>
+
+/* Register offsets */
+#define AG71XX_REG_MAC_CFG1 0x0000
+#define AG71XX_REG_MAC_CFG2 0x0004
+#define AG71XX_REG_MAC_IPG 0x0008
+#define AG71XX_REG_MAC_HDX 0x000c
+#define AG71XX_REG_MAC_MFL 0x0010
+#define AG71XX_REG_MII_CFG 0x0020
+#define AG71XX_REG_MII_CMD 0x0024
+#define AG71XX_REG_MII_ADDR 0x0028
+#define AG71XX_REG_MII_CTRL 0x002c
+#define AG71XX_REG_MII_STATUS 0x0030
+#define AG71XX_REG_MII_IND 0x0034
+#define AG71XX_REG_MAC_IFCTL 0x0038
+#define AG71XX_REG_MAC_ADDR1 0x0040
+#define AG71XX_REG_MAC_ADDR2 0x0044
+#define AG71XX_REG_FIFO_CFG0 0x0048
+#define AG71XX_REG_FIFO_CFG1 0x004c
+#define AG71XX_REG_FIFO_CFG2 0x0050
+#define AG71XX_REG_FIFO_CFG3 0x0054
+#define AG71XX_REG_FIFO_CFG4 0x0058
+#define AG71XX_REG_FIFO_CFG5 0x005c
+#define AG71XX_REG_FIFO_RAM0 0x0060
+#define AG71XX_REG_FIFO_RAM1 0x0064
+#define AG71XX_REG_FIFO_RAM2 0x0068
+#define AG71XX_REG_FIFO_RAM3 0x006c
+#define AG71XX_REG_FIFO_RAM4 0x0070
+#define AG71XX_REG_FIFO_RAM5 0x0074
+#define AG71XX_REG_FIFO_RAM6 0x0078
+#define AG71XX_REG_FIFO_RAM7 0x007c
+
+#define AG71XX_REG_TX_CTRL 0x0180
+#define AG71XX_REG_TX_DESC 0x0184
+#define AG71XX_REG_TX_STATUS 0x0188
+#define AG71XX_REG_RX_CTRL 0x018c
+#define AG71XX_REG_RX_DESC 0x0190
+#define AG71XX_REG_RX_STATUS 0x0194
+#define AG71XX_REG_INT_ENABLE 0x0198
+#define AG71XX_REG_INT_STATUS 0x019c
+
+#define AG71XX_REG_FIFO_DEPTH 0x01a8
+#define AG71XX_REG_RX_SM 0x01b0
+#define AG71XX_REG_TX_SM 0x01b4
+
+#define MAC_CFG1_TXE BIT(0) /* Tx Enable */
+#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
+#define MAC_CFG1_RXE BIT(2) /* Rx Enable */
+#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
+#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
+#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
+#define MAC_CFG1_LB BIT(8) /* Loopback mode */
+#define MAC_CFG1_TX_RST BIT(18) /* Tx Reset */
+#define MAC_CFG1_RX_RST BIT(19) /* Rx Reset */
+#define MAC_CFG1_SR BIT(31) /* Soft Reset */
+
+#define MAC_CFG2_FDX BIT(0)
+#define MAC_CFG2_CRC_EN BIT(1)
+#define MAC_CFG2_PAD_CRC_EN BIT(2)
+#define MAC_CFG2_LEN_CHECK BIT(4)
+#define MAC_CFG2_HUGE_FRAME_EN BIT(5)
+#define MAC_CFG2_IF_1000 BIT(9)
+#define MAC_CFG2_IF_10_100 BIT(8)
+
+#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
+#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
+#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
+#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
+#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
+#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
+ | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
+
+#define FIFO_CFG0_ENABLE_SHIFT 8
+
+#define FIFO_CFG4_DE BIT(0) /* Drop Event */
+#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
+#define FIFO_CFG4_FC BIT(2) /* False Carrier */
+#define FIFO_CFG4_CE BIT(3) /* Code Error */
+#define FIFO_CFG4_CR BIT(4) /* CRC error */
+#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
+#define FIFO_CFG4_LO BIT(6) /* Length out of range */
+#define FIFO_CFG4_OK BIT(7) /* Packet is OK */
+#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
+#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
+#define FIFO_CFG4_DR BIT(10) /* Dribble */
+#define FIFO_CFG4_LE BIT(11) /* Long Event */
+#define FIFO_CFG4_CF BIT(12) /* Control Frame */
+#define FIFO_CFG4_PF BIT(13) /* Pause Frame */
+#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
+#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
+#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
+#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
+
+#define FIFO_CFG5_DE BIT(0) /* Drop Event */
+#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
+#define FIFO_CFG5_FC BIT(2) /* False Carrier */
+#define FIFO_CFG5_CE BIT(3) /* Code Error */
+#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
+#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
+#define FIFO_CFG5_OK BIT(6) /* Packet is OK */
+#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
+#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
+#define FIFO_CFG5_DR BIT(9) /* Dribble */
+#define FIFO_CFG5_CF BIT(10) /* Control Frame */
+#define FIFO_CFG5_PF BIT(11) /* Pause Frame */
+#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
+#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
+#define FIFO_CFG5_LE BIT(14) /* Long Event */
+#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
+#define FIFO_CFG5_16 BIT(16) /* unknown */
+#define FIFO_CFG5_17 BIT(17) /* unknown */
+#define FIFO_CFG5_SF BIT(18) /* Short Frame */
+#define FIFO_CFG5_BM BIT(19) /* Byte Mode */
+
+#define AG71XX_INT_TX_PS BIT(0)
+#define AG71XX_INT_TX_UR BIT(1)
+#define AG71XX_INT_TX_BE BIT(3)
+#define AG71XX_INT_RX_PR BIT(4)
+#define AG71XX_INT_RX_OF BIT(6)
+#define AG71XX_INT_RX_BE BIT(7)
+
+#define MAC_IFCTL_SPEED BIT(16)
+
+#define MII_CFG_CLK_DIV_4 0
+#define MII_CFG_CLK_DIV_6 2
+#define MII_CFG_CLK_DIV_8 3
+#define MII_CFG_CLK_DIV_10 4
+#define MII_CFG_CLK_DIV_14 5
+#define MII_CFG_CLK_DIV_20 6
+#define MII_CFG_CLK_DIV_28 7
+#define MII_CFG_CLK_DIV_34 8
+#define MII_CFG_CLK_DIV_42 9
+#define MII_CFG_CLK_DIV_50 10
+#define MII_CFG_CLK_DIV_58 11
+#define MII_CFG_CLK_DIV_66 12
+#define MII_CFG_CLK_DIV_74 13
+#define MII_CFG_CLK_DIV_82 14
+#define MII_CFG_CLK_DIV_98 15
+#define MII_CFG_RESET BIT(31)
+
+#define MII_CMD_WRITE 0x0
+#define MII_CMD_READ 0x1
+#define MII_ADDR_SHIFT 8
+#define MII_IND_BUSY BIT(0)
+#define MII_IND_INVALID BIT(2)
+
+#define TX_CTRL_TXE BIT(0) /* Tx Enable */
+
+#define TX_STATUS_PS BIT(0) /* Packet Sent */
+#define TX_STATUS_UR BIT(1) /* Tx Underrun */
+#define TX_STATUS_BE BIT(3) /* Bus Error */
+
+#define RX_CTRL_RXE BIT(0) /* Rx Enable */
+
+#define RX_STATUS_PR BIT(0) /* Packet Received */
+#define RX_STATUS_OF BIT(2) /* Rx Overflow */
+#define RX_STATUS_BE BIT(3) /* Bus Error */
+
+/*
+ * GMAC register macros
+ */
+#define AG71XX_ETH_CFG_RGMII_GE0 (1<<0)
+#define AG71XX_ETH_CFG_MII_GE0_SLAVE (1<<4)
+
+/*
+ * h/w descriptor
+ */
+typedef struct {
+ uint32_t pkt_start_addr;
+
+ uint32_t is_empty : 1;
+ uint32_t res1 : 10;
+ uint32_t ftpp_override : 5;
+ uint32_t res2 : 4;
+ uint32_t pkt_size : 12;
+
+ uint32_t next_desc ;
+} ag7240_desc_t;
+
+#define NO_OF_TX_FIFOS 8
+#define NO_OF_RX_FIFOS 8
+#define TX_RING_SZ (NO_OF_TX_FIFOS * sizeof(ag7240_desc_t))
+#define MAX_RBUFF_SZ 0x600 /* 1518 rounded up */
+
+#define MAX_WAIT 1000
+
+struct ag71xx {
+ struct device_d *dev;
+ struct eth_device netdev;
+ void __iomem *regs;
+ void __iomem *regs_gmac;
+ struct mii_bus miibus;
+
+ void *rx_buffer;
+
+ unsigned char *rx_pkt[NO_OF_RX_FIFOS];
+ ag7240_desc_t *fifo_tx;
+ ag7240_desc_t *fifo_rx;
+
+ int next_tx;
+ int next_rx;
+};
+
+static inline void ag71xx_check_reg_offset(struct ag71xx *priv, int reg)
+{
+ switch (reg) {
+ case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
+ case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM:
+ case AG71XX_REG_MII_CFG:
+ break;
+
+ default:
+ BUG();
+ }
+}
+
+static inline u32 ag71xx_gmac_rr(struct ag71xx *dev, int reg)
+{
+ return __raw_readl(dev->regs_gmac + reg);
+}
+
+static inline void ag71xx_gmac_wr(struct ag71xx *dev, int reg, u32 val)
+{
+ __raw_writel(val, dev->regs_gmac + reg);
+}
+
+static inline u32 ag71xx_rr(struct ag71xx *priv, int reg)
+{
+ ag71xx_check_reg_offset(priv, reg);
+
+ return __raw_readl(priv->regs + reg);
+}
+
+static inline void ag71xx_wr(struct ag71xx *priv, int reg, u32 val)
+{
+ ag71xx_check_reg_offset(priv, reg);
+
+ __raw_writel(val, priv->regs + reg);
+ /* flush write */
+ (void)__raw_readl(priv->regs + reg);
+}
+
+static int ag71xx_ether_mii_read(struct mii_bus *miidev, int addr, int reg)
+{
+ return 0xffff;
+}
+
+static int ag71xx_ether_mii_write(struct mii_bus *miidev, int addr, int reg, u16 val)
+{
+ return 0;
+}
+
+static int ag71xx_ether_set_ethaddr(struct eth_device *edev, const unsigned char *adr)
+{
+ return 0;
+}
+
+static int ag71xx_ether_get_ethaddr(struct eth_device *edev, unsigned char *adr)
+{
+ /* We have no eeprom */
+ return -1;
+}
+
+static void ag71xx_ether_halt(struct eth_device *edev)
+{
+ struct ag71xx *priv = edev->priv;
+
+ ag71xx_wr(priv, AG71XX_REG_RX_CTRL, 0);
+ while (ag71xx_rr(priv, AG71XX_REG_RX_CTRL))
+ ;
+}
+
+static int ag71xx_ether_rx(struct eth_device *edev)
+{
+ struct ag71xx *priv = edev->priv;
+ ag7240_desc_t *f;
+ unsigned int work_done;
+
+ for (work_done = 0; work_done < NO_OF_RX_FIFOS; work_done++) {
+ unsigned int pktlen;
+ unsigned char *rx_pkt;
+
+ f = &priv->fifo_rx[priv->next_rx];
+
+ if (f->is_empty)
+ break;
+
+ pktlen = f->pkt_size;
+ rx_pkt = priv->rx_pkt[priv->next_rx];
+
+ /* invalidate */
+ dma_sync_single_for_cpu((unsigned long)rx_pkt, pktlen,
+ DMA_FROM_DEVICE);
+
+ net_receive(edev, rx_pkt, pktlen - 4);
+
+ f->is_empty = 1;
+
+ priv->next_rx = (priv->next_rx + 1) % NO_OF_RX_FIFOS;
+ }
+
+ if (!(ag71xx_rr(priv, AG71XX_REG_RX_CTRL) & RX_CTRL_RXE)) {
+ f = &priv->fifo_rx[priv->next_rx];
+ ag71xx_wr(priv, AG71XX_REG_RX_DESC, virt_to_phys(f));
+ ag71xx_wr(priv, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
+ }
+
+ return work_done;
+}
+
+static int ag71xx_ether_send(struct eth_device *edev, void *packet, int length)
+{
+ struct ag71xx *priv = edev->priv;
+ struct device_d *dev = priv->dev;
+ ag7240_desc_t *f = &priv->fifo_tx[priv->next_tx];
+ int i;
+
+ /* flush */
+ dma_sync_single_for_device((unsigned long)packet, length, DMA_TO_DEVICE);
+
+ f->pkt_start_addr = virt_to_phys(packet);
+ f->res1 = 0;
+ f->pkt_size = length;
+ f->is_empty = 0;
+ ag71xx_wr(priv, AG71XX_REG_TX_DESC, virt_to_phys(f));
+ ag71xx_wr(priv, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
+
+ /* flush again?! */
+ dma_sync_single_for_cpu((unsigned long)packet, length, DMA_TO_DEVICE);
+
+ for (i = 0; i < MAX_WAIT; i++) {
+ udelay(100);
+ if (f->is_empty) {
+ break;
+ }
+ }
+
+ if (i == MAX_WAIT) {
+ dev_err(dev, "Tx Timed out\n");
+ }
+
+ f->pkt_start_addr = 0;
+ f->pkt_size = 0;
+
+ priv->next_tx = (priv->next_tx + 1) % NO_OF_TX_FIFOS;
+
+ return 0;
+}
+
+static int ag71xx_ether_open(struct eth_device *edev)
+{
+ return 0;
+}
+
+static int ag71xx_ether_init(struct eth_device *edev)
+{
+ struct ag71xx *priv = edev->priv;
+ int i;
+ void *rxbuf = priv->rx_buffer;
+
+ priv->next_rx = 0;
+
+ for (i = 0; i < NO_OF_RX_FIFOS; i++) {
+ ag7240_desc_t *fr = &priv->fifo_rx[i];
+
+ priv->rx_pkt[i] = rxbuf;
+ fr->pkt_start_addr = virt_to_phys(rxbuf);
+ fr->pkt_size = MAX_RBUFF_SZ;
+ fr->is_empty = 1;
+ fr->next_desc = virt_to_phys(&priv->fifo_rx[(i + 1) % NO_OF_RX_FIFOS]);
+
+ /* invalidate */
+ dma_sync_single_for_device((unsigned long)rxbuf, MAX_RBUFF_SZ,
+ DMA_FROM_DEVICE);
+
+ rxbuf += MAX_RBUFF_SZ;
+ }
+
+ /* Clean Tx BD's */
+ memset(priv->fifo_tx, 0, TX_RING_SZ);
+
+ ag71xx_wr(priv, AG71XX_REG_RX_DESC, virt_to_phys(priv->fifo_rx));
+ ag71xx_wr(priv, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
+
+ return 1;
+}
+
+static int ag71xx_mii_setup(struct ag71xx *priv)
+{
+ u32 rd;
+
+ rd = ag71xx_gmac_rr(priv, 0);
+ rd |= AG71XX_ETH_CFG_MII_GE0_SLAVE;
+ ag71xx_gmac_wr(priv, 0, rd);
+
+ return 0;
+}
+
+static int ag71xx_probe(struct device_d *dev)
+{
+ void __iomem *regs, *regs_gmac;
+ struct mii_bus *miibus;
+ struct eth_device *edev;
+ struct ag71xx *priv;
+ u32 mac_h, mac_l;
+ u32 rd;
+
+ regs_gmac = dev_request_mem_region_by_name(dev, "gmac");
+ if (IS_ERR(regs_gmac))
+ return PTR_ERR(regs_gmac);
+
+ regs = dev_request_mem_region_by_name(dev, "ge0");
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
+
+ priv = xzalloc(sizeof(struct ag71xx));
+ edev = &priv->netdev;
+ miibus = &priv->miibus;
+ edev->priv = priv;
+
+ edev->init = ag71xx_ether_init;
+ edev->open = ag71xx_ether_open;
+ edev->send = ag71xx_ether_send;
+ edev->recv = ag71xx_ether_rx;
+ edev->halt = ag71xx_ether_halt;
+ edev->get_ethaddr = ag71xx_ether_get_ethaddr;
+ edev->set_ethaddr = ag71xx_ether_set_ethaddr;
+
+ priv->dev = dev;
+ priv->regs = regs;
+ priv->regs_gmac = regs_gmac;
+
+ miibus->read = ag71xx_ether_mii_read;
+ miibus->write = ag71xx_ether_mii_write;
+ miibus->priv = priv;
+
+ /* enable switch core */
+ rd = __raw_readl((char *)KSEG1ADDR(AR71XX_PLL_BASE + AR933X_ETHSW_CLOCK_CONTROL_REG)) & ~(0x1f);
+ rd |= 0x10;
+ __raw_writel(rd, (char *)KSEG1ADDR(AR71XX_PLL_BASE + AR933X_ETHSW_CLOCK_CONTROL_REG));
+
+ if (ath79_reset_rr(AR933X_RESET_REG_RESET_MODULE) != 0)
+ ath79_reset_wr(AR933X_RESET_REG_RESET_MODULE, 0);
+
+ /* reset GE0 MAC and MDIO */
+ rd = ath79_reset_rr(AR933X_RESET_REG_RESET_MODULE);
+ rd |= AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO | AR933X_RESET_SWITCH;
+ ath79_reset_wr(AR933X_RESET_REG_RESET_MODULE, rd);
+ mdelay(100);
+
+ rd = ath79_reset_rr(AR933X_RESET_REG_RESET_MODULE);
+ rd &= ~(AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO | AR933X_RESET_SWITCH);
+ ath79_reset_wr(AR933X_RESET_REG_RESET_MODULE, rd);
+ mdelay(100);
+
+ ag71xx_wr(priv, AG71XX_REG_MAC_CFG1, (MAC_CFG1_SR | MAC_CFG1_TX_RST | MAC_CFG1_RX_RST));
+ ag71xx_wr(priv, AG71XX_REG_MAC_CFG1, (MAC_CFG1_RXE | MAC_CFG1_TXE));
+
+ rd = ag71xx_rr(priv, AG71XX_REG_MAC_CFG2);
+ rd |= (MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK | MAC_CFG2_IF_10_100);
+ ag71xx_wr(priv, AG71XX_REG_MAC_CFG2, rd);
+
+ /* config FIFOs */
+ ag71xx_wr(priv, AG71XX_REG_FIFO_CFG0, 0x1f00);
+
+ ag71xx_mii_setup(priv);
+
+ ag71xx_wr(priv, AG71XX_REG_FIFO_CFG1, 0x10ffff);
+ ag71xx_wr(priv, AG71XX_REG_FIFO_CFG2, 0xAAA0555);
+
+ ag71xx_wr(priv, AG71XX_REG_FIFO_CFG4, 0x3ffff);
+ ag71xx_wr(priv, AG71XX_REG_FIFO_CFG5, 0x66b82);
+ ag71xx_wr(priv, AG71XX_REG_FIFO_CFG3, 0x1f00140);
+
+ priv->rx_buffer = xmemalign(PAGE_SIZE, NO_OF_RX_FIFOS * MAX_RBUFF_SZ);
+ priv->fifo_tx = dma_alloc_coherent(NO_OF_TX_FIFOS * sizeof(ag7240_desc_t), DMA_ADDRESS_BROKEN);
+ priv->fifo_rx = dma_alloc_coherent(NO_OF_RX_FIFOS * sizeof(ag7240_desc_t), DMA_ADDRESS_BROKEN);
+ priv->next_tx = 0;
+
+ mac_l = 0x3344;
+ mac_h = 0x0004d980;
+
+ ag71xx_wr(priv, AG71XX_REG_MAC_ADDR1, mac_l);
+ ag71xx_wr(priv, AG71XX_REG_MAC_ADDR2, mac_h);
+
+ mdiobus_register(miibus);
+ eth_register(edev);
+
+ dev_info(dev, "network device registered\n");
+
+ return 0;
+}
+
+static __maybe_unused struct of_device_id ag71xx_dt_ids[] = {
+ {
+ .compatible = "qca,ar7100-gmac",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver_d ag71xx_driver = {
+ .name = "ag71xx-gmac",
+ .probe = ag71xx_probe,
+ .of_compatible = DRV_OF_COMPAT(ag71xx_dt_ids),
+};
+device_platform_driver(ag71xx_driver);
--
2.11.0
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 06/13] net: ag71xx: bit 19 should be set to 1 for GE0
2017-08-07 14:39 [PATCH v2 01/13] MIPS: ath79: provide CONFIG_SOC_QCA_AR9331 option Oleksij Rempel
` (3 preceding siblings ...)
2017-08-07 14:39 ` [PATCH v2 05/13] net: ath79: add ag71xx Ethernet driver Oleksij Rempel
@ 2017-08-07 14:39 ` Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 07/13] MIPS: tplink-mr3020: pbl: move WMAC init after flash addr test Oleksij Rempel
` (7 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Oleksij Rempel @ 2017-08-07 14:39 UTC (permalink / raw)
To: barebox
From: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
drivers/net/ag71xx.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ag71xx.c b/drivers/net/ag71xx.c
index b2e066be3..d13bf9171 100644
--- a/drivers/net/ag71xx.c
+++ b/drivers/net/ag71xx.c
@@ -492,7 +492,8 @@ static int ag71xx_probe(struct device_d *dev)
ag71xx_wr(priv, AG71XX_REG_FIFO_CFG2, 0xAAA0555);
ag71xx_wr(priv, AG71XX_REG_FIFO_CFG4, 0x3ffff);
- ag71xx_wr(priv, AG71XX_REG_FIFO_CFG5, 0x66b82);
+ /* bit 19 should be set to 1 for GE0 */
+ ag71xx_wr(priv, AG71XX_REG_FIFO_CFG5, (0x66b82) | (1 << 19));
ag71xx_wr(priv, AG71XX_REG_FIFO_CFG3, 0x1f00140);
priv->rx_buffer = xmemalign(PAGE_SIZE, NO_OF_RX_FIFOS * MAX_RBUFF_SZ);
--
2.11.0
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 07/13] MIPS: tplink-mr3020: pbl: move WMAC init after flash addr test
2017-08-07 14:39 [PATCH v2 01/13] MIPS: ath79: provide CONFIG_SOC_QCA_AR9331 option Oleksij Rempel
` (4 preceding siblings ...)
2017-08-07 14:39 ` [PATCH v2 06/13] net: ag71xx: bit 19 should be set to 1 for GE0 Oleksij Rempel
@ 2017-08-07 14:39 ` Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 08/13] MIPS: tplink-mr3020: pbl: move hornet_mips24k_cp0_setup " Oleksij Rempel
` (6 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Oleksij Rempel @ 2017-08-07 14:39 UTC (permalink / raw)
To: barebox; +Cc: Oleksij Rempel
if this function is called in the RAM, we won't be able to
continue start sequence.
It brakes boot over JTAG use case.
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Cc: Yegor Yefremov <yegorslists@googlemail.com>
---
arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h b/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h
index 3a7b560a0..1774556a8 100644
--- a/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h
+++ b/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h
@@ -26,12 +26,12 @@
mips_barebox_10h
- pbl_ar9331_wmac_enable
-
hornet_mips24k_cp0_setup
pbl_blt 0xbf000000 skip_pll_ram_config t8
+ pbl_ar9331_wmac_enable
+
hornet_1_1_war
pbl_ar9331_pll
--
2.11.0
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 08/13] MIPS: tplink-mr3020: pbl: move hornet_mips24k_cp0_setup after flash addr test
2017-08-07 14:39 [PATCH v2 01/13] MIPS: ath79: provide CONFIG_SOC_QCA_AR9331 option Oleksij Rempel
` (5 preceding siblings ...)
2017-08-07 14:39 ` [PATCH v2 07/13] MIPS: tplink-mr3020: pbl: move WMAC init after flash addr test Oleksij Rempel
@ 2017-08-07 14:39 ` Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 09/13] MIPS: tplink-mr3020_defconfig: enable more options Oleksij Rempel
` (5 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Oleksij Rempel @ 2017-08-07 14:39 UTC (permalink / raw)
To: barebox; +Cc: Oleksij Rempel
this is needed to start zbarebox.bin from running barebox.
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
---
arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h b/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h
index 1774556a8..e70f55e87 100644
--- a/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h
+++ b/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h
@@ -26,10 +26,10 @@
mips_barebox_10h
- hornet_mips24k_cp0_setup
-
pbl_blt 0xbf000000 skip_pll_ram_config t8
+ hornet_mips24k_cp0_setup
+
pbl_ar9331_wmac_enable
hornet_1_1_war
--
2.11.0
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 09/13] MIPS: tplink-mr3020_defconfig: enable more options
2017-08-07 14:39 [PATCH v2 01/13] MIPS: ath79: provide CONFIG_SOC_QCA_AR9331 option Oleksij Rempel
` (6 preceding siblings ...)
2017-08-07 14:39 ` [PATCH v2 08/13] MIPS: tplink-mr3020: pbl: move hornet_mips24k_cp0_setup " Oleksij Rempel
@ 2017-08-07 14:39 ` Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 10/13] MIPS: tplink-mr3020.dts: add partition table Oleksij Rempel
` (4 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Oleksij Rempel @ 2017-08-07 14:39 UTC (permalink / raw)
To: barebox; +Cc: Oleksij Rempel
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
---
arch/mips/configs/tplink-mr3020_defconfig | 40 +++++++++++++++++++++++++++++--
1 file changed, 38 insertions(+), 2 deletions(-)
diff --git a/arch/mips/configs/tplink-mr3020_defconfig b/arch/mips/configs/tplink-mr3020_defconfig
index 93fb10ddd..4193bd628 100644
--- a/arch/mips/configs/tplink-mr3020_defconfig
+++ b/arch/mips/configs/tplink-mr3020_defconfig
@@ -6,33 +6,67 @@ CONFIG_IMAGE_COMPRESSION_XZKERN=y
CONFIG_MMU=y
CONFIG_TEXT_BASE=0x81000000
CONFIG_MALLOC_TLSF=y
+CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_CMD_DMESG=y
CONFIG_LONGHELP=y
CONFIG_CMD_IOMEM=y
+CONFIG_CMD_IMD=y
CONFIG_CMD_MEMINFO=y
-# CONFIG_CMD_BOOTM is not set
CONFIG_CMD_GO=y
CONFIG_CMD_LOADB=y
CONFIG_CMD_LOADY=y
CONFIG_CMD_RESET=y
-CONFIG_CMD_GLOBAL=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_DEFAULTENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_SAVEENV=y
CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_LET=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_READF=y
CONFIG_CMD_SLEEP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_HOST=y
+CONFIG_CMD_MIITOOL=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_ECHO_E=y
CONFIG_CMD_EDIT=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MM=y
CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_LED=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_LED_TRIGGER=y
+CONFIG_CMD_BAREBOX_UPDATE=y
CONFIG_CMD_OF_NODE=y
CONFIG_CMD_OF_PROPERTY=y
CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIME=y
+CONFIG_NET=y
+CONFIG_NET_NFS=y
+CONFIG_NET_NETCONSOLE=y
+CONFIG_NET_SNTP=y
CONFIG_OFDEVICE=y
+CONFIG_OF_BAREBOX_DRIVERS=y
+CONFIG_OF_BAREBOX_ENV_IN_FS=y
CONFIG_DRIVER_SERIAL_AR933X=y
+CONFIG_DRIVER_NET_AG71XX=y
+CONFIG_AT803X_PHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_GPIO=y
CONFIG_DRIVER_SPI_ATH79=y
CONFIG_MTD=y
# CONFIG_MTD_OOB_DEVICE is not set
@@ -41,5 +75,7 @@ CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_LED_GPIO_OF=y
CONFIG_LED_TRIGGERS=y
+CONFIG_FS_TFTP=y
+CONFIG_FS_NFS=y
CONFIG_DIGEST_SHA224_GENERIC=y
CONFIG_DIGEST_SHA256_GENERIC=y
--
2.11.0
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 10/13] MIPS: tplink-mr3020.dts: add partition table
2017-08-07 14:39 [PATCH v2 01/13] MIPS: ath79: provide CONFIG_SOC_QCA_AR9331 option Oleksij Rempel
` (7 preceding siblings ...)
2017-08-07 14:39 ` [PATCH v2 09/13] MIPS: tplink-mr3020_defconfig: enable more options Oleksij Rempel
@ 2017-08-07 14:39 ` Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 11/13] MIPS: ar9344.dtsi: add ag71xx Ethernet driver Oleksij Rempel
` (3 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Oleksij Rempel @ 2017-08-07 14:39 UTC (permalink / raw)
To: barebox; +Cc: Oleksij Rempel
We need partition table for barebox update handler
and for barebox environment
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
---
arch/mips/dts/tplink-mr3020.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/mips/dts/tplink-mr3020.dts b/arch/mips/dts/tplink-mr3020.dts
index 1e843ee00..eaae11edd 100644
--- a/arch/mips/dts/tplink-mr3020.dts
+++ b/arch/mips/dts/tplink-mr3020.dts
@@ -4,4 +4,23 @@
aliases {
spiflash = &spiflash;
};
+
+ chosen {
+ environment@0 {
+ compatible = "barebox,environment";
+ device-path = &spiflash, "partname:barebox-environment";
+ };
+ };
+};
+
+&spiflash {
+ partition@0 {
+ label = "barebox";
+ reg = <0 0x80000>;
+ };
+
+ partition@80000 {
+ label = "barebox-environment";
+ reg = <0x80000 0x10000>;
+ };
};
--
2.11.0
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 11/13] MIPS: ar9344.dtsi: add ag71xx Ethernet driver
2017-08-07 14:39 [PATCH v2 01/13] MIPS: ath79: provide CONFIG_SOC_QCA_AR9331 option Oleksij Rempel
` (8 preceding siblings ...)
2017-08-07 14:39 ` [PATCH v2 10/13] MIPS: tplink-mr3020.dts: add partition table Oleksij Rempel
@ 2017-08-07 14:39 ` Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 12/13] MIPS: ath79: add barebox update handler Oleksij Rempel
` (2 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Oleksij Rempel @ 2017-08-07 14:39 UTC (permalink / raw)
To: barebox; +Cc: Oleksij Rempel
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
---
arch/mips/dts/ar9344.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/mips/dts/ar9344.dtsi b/arch/mips/dts/ar9344.dtsi
index 0838e8d7f..431273c36 100644
--- a/arch/mips/dts/ar9344.dtsi
+++ b/arch/mips/dts/ar9344.dtsi
@@ -49,5 +49,14 @@
status = "disabled";
};
+
+ mac0: mac@19000000 {
+ compatible = "qca,ar7100-gmac", "qca,ar9344-gmac";
+ reg = <0x18070000 0x00000100>,
+ <0x19000000 0x01000000>;
+ reg-names = "gmac", "ge0";
+ phy-mode = "mii";
+ status = "disabled";
+ };
};
};
--
2.11.0
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 12/13] MIPS: ath79: add barebox update handler
2017-08-07 14:39 [PATCH v2 01/13] MIPS: ath79: provide CONFIG_SOC_QCA_AR9331 option Oleksij Rempel
` (9 preceding siblings ...)
2017-08-07 14:39 ` [PATCH v2 11/13] MIPS: ar9344.dtsi: add ag71xx Ethernet driver Oleksij Rempel
@ 2017-08-07 14:39 ` Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 13/13] filetype: fix file type detection for Barebox MIPS Oleksij Rempel
2017-08-09 15:23 ` [PATCH v2 01/13] MIPS: ath79: provide CONFIG_SOC_QCA_AR9331 option Oleksij Rempel
12 siblings, 0 replies; 17+ messages in thread
From: Oleksij Rempel @ 2017-08-07 14:39 UTC (permalink / raw)
To: barebox; +Cc: Oleksij Rempel
Most of ar93xx SoCs seem to work only with spi.
spifash handler should be enough for now.
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
---
arch/mips/mach-ath79/Makefile | 1 +
arch/mips/mach-ath79/bbu.c | 28 ++++++++++++++++++++++++++++
2 files changed, 29 insertions(+)
create mode 100644 arch/mips/mach-ath79/bbu.c
diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile
index f3cc6684b..3772daeba 100644
--- a/arch/mips/mach-ath79/Makefile
+++ b/arch/mips/mach-ath79/Makefile
@@ -1 +1,2 @@
obj-y += reset.o
+obj-y += bbu.o
diff --git a/arch/mips/mach-ath79/bbu.c b/arch/mips/mach-ath79/bbu.c
new file mode 100644
index 000000000..701b5752e
--- /dev/null
+++ b/arch/mips/mach-ath79/bbu.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2017 Oleksij Rempel <linux@rempel-privat.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <bbu.h>
+#include <init.h>
+
+static int ath79_init_bbu(void)
+{
+ bbu_register_std_file_update("barebox", BBU_HANDLER_FLAG_DEFAULT,
+ "/dev/spiflash.barebox",
+ filetype_mips_barebox);
+
+ return 0;
+}
+postcore_initcall(ath79_init_bbu);
+
+
--
2.11.0
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 13/13] filetype: fix file type detection for Barebox MIPS
2017-08-07 14:39 [PATCH v2 01/13] MIPS: ath79: provide CONFIG_SOC_QCA_AR9331 option Oleksij Rempel
` (10 preceding siblings ...)
2017-08-07 14:39 ` [PATCH v2 12/13] MIPS: ath79: add barebox update handler Oleksij Rempel
@ 2017-08-07 14:39 ` Oleksij Rempel
2017-08-09 15:23 ` [PATCH v2 01/13] MIPS: ath79: provide CONFIG_SOC_QCA_AR9331 option Oleksij Rempel
12 siblings, 0 replies; 17+ messages in thread
From: Oleksij Rempel @ 2017-08-07 14:39 UTC (permalink / raw)
To: barebox; +Cc: Oleksij Rempel
Since there is no NULL after "barebox" in the file header,
comparison won't stop on the right place.
Fix regression introduced by patch:
|commit 03939c0dfbf27d99e81d85e1bc0340fbee083d74
|Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|Date: Tue Jan 22 15:40:36 2013 +0100
|
| filetype: add is_barebox_mips_head support
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
---
include/filetype.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/filetype.h b/include/filetype.h
index 709c1869f..c84905d78 100644
--- a/include/filetype.h
+++ b/include/filetype.h
@@ -77,7 +77,7 @@ static inline int is_barebox_arm_head(const char *head)
#ifdef CONFIG_MIPS
static inline int is_barebox_mips_head(const char *head)
{
- return !strcmp(head + MIPS_HEAD_MAGICWORD_OFFSET, "barebox");
+ return !strncmp(head + MIPS_HEAD_MAGICWORD_OFFSET, "barebox", 7);
}
#else
static inline int is_barebox_mips_head(const char *head)
--
2.11.0
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 04/13] MIPS: add virt_to_phys() and phys_to_virt()
2017-08-07 14:39 ` [PATCH v2 04/13] MIPS: add virt_to_phys() and phys_to_virt() Oleksij Rempel
@ 2017-08-07 19:56 ` Peter Mamonov
0 siblings, 0 replies; 17+ messages in thread
From: Peter Mamonov @ 2017-08-07 19:56 UTC (permalink / raw)
To: Oleksij Rempel; +Cc: barebox
Hi Oleksij,
On Mon, Aug 07, 2017 at 04:39:18PM +0200, Oleksij Rempel wrote:
> From: Antony Pavlov <antonynpavlov@gmail.com>
>
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
> ---
> arch/mips/include/asm/io.h | 35 +++++++++++++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
> index 4bee5913a..993b30e2a 100644
> --- a/arch/mips/include/asm/io.h
> +++ b/arch/mips/include/asm/io.h
> @@ -12,11 +12,46 @@
>
> #include <linux/compiler.h>
> #include <asm/types.h>
> +#include <asm/addrspace.h>
> #include <asm/byteorder.h>
>
> void dma_flush_range(unsigned long, unsigned long);
> void dma_inv_range(unsigned long, unsigned long);
>
> +/*
> + * virt_to_phys - map virtual addresses to physical
> + * @address: address to remap
> + *
> + * The returned physical address is the physical (CPU) mapping for
> + * the memory address given. It is only valid to use this function on
> + * addresses directly mapped or allocated via kmalloc.
> + *
> + * This function does not give bus mappings for DMA transfers. In
> + * almost all conceivable cases a device driver should not be using
> + * this function
> + */
> +static inline unsigned long virt_to_phys(const void *address)
> +{
> + return (unsigned long)address & 0x1fffffff;
Guess we can use CPHYSADDR() macros here, which is available in barebox.
> +}
> +
> +/*
> + * phys_to_virt - map physical address to virtual
> + * @address: address to remap
> + *
> + * The returned virtual address is a current CPU mapping for
> + * the memory address given. It is only valid to use this function on
> + * addresses that have a kernel mapping
> + *
> + * This function does not handle bus mappings for DMA transfers. In
> + * almost all conceivable cases a device driver should not be using
> + * this function
> + */
> +static inline void *phys_to_virt(unsigned long address)
> +{
> + return (void *)(KSEG0 | (address & 0x1fffffff));
Same here: there is a CKSEG0ADDR() macros available in barebox.
> +}
> +
> #define IO_SPACE_LIMIT 0
>
> /*****************************************************************************/
> --
> 2.11.0
>
Regards,
Peter
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 05/13] net: ath79: add ag71xx Ethernet driver
2017-08-07 14:39 ` [PATCH v2 05/13] net: ath79: add ag71xx Ethernet driver Oleksij Rempel
@ 2017-08-07 20:45 ` Peter Mamonov
2017-08-08 7:50 ` Lucas Stach
0 siblings, 1 reply; 17+ messages in thread
From: Peter Mamonov @ 2017-08-07 20:45 UTC (permalink / raw)
To: Oleksij Rempel; +Cc: barebox
On Mon, Aug 07, 2017 at 04:39:19PM +0200, Oleksij Rempel wrote:
> From: Yegor Yefremov <yegorslists@googlemail.com>
>
> Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> ---
> Documentation/boards/mips/tplink-mr3020.rst | 7 +
> arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 12 +
> drivers/net/Kconfig | 7 +
> drivers/net/Makefile | 1 +
> drivers/net/ag71xx.c | 530 ++++++++++++++++++++++++
> 5 files changed, 557 insertions(+)
> create mode 100644 drivers/net/ag71xx.c
>
> diff --git a/Documentation/boards/mips/tplink-mr3020.rst b/Documentation/boards/mips/tplink-mr3020.rst
> index 99101c337..4119c1e7e 100644
> --- a/Documentation/boards/mips/tplink-mr3020.rst
> +++ b/Documentation/boards/mips/tplink-mr3020.rst
> @@ -60,6 +60,13 @@ Next, setup network on MR3020 and run ``6F01A8C0.img``, e.g.:
> hornet> tftpboot 0x81000000 6F01A8C0.img
> hornet> bootm 0x81000000
>
> +WIP: Short form:
> + hornet> set ipaddr 192.168.0.2; set serverip 192.168.0.1
> + hornet> tftpboot 0x81000000 6F01A8C0.img; bootm 0x81000000
> +
> +u-boot_mod:
> + uboot> setenv ipaddr 192.168.1.12; setenv serverip 192.168.1.2
> + uboot> tftpboot 0x81000000 6F01A8C0.img; bootm 0x81000000
>
> Links
> -----
> diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
> index f56c3f724..31d33b3c4 100644
> --- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
> +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
> @@ -102,6 +102,8 @@
> #define AR933X_PLL_CLOCK_CTRL_REG 0x08
> #define AR933X_PLL_DITHER_FRAC_REG 0x10
> #define AR933X_PLL_DITHER_REG 0x14
> +#define AR933X_ETHSW_CLOCK_CONTROL_REG 0x24
> +#define AR933X_ETH_XMII_CONTROL_REG 0x2c
>
> #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
> #define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
> @@ -125,6 +127,16 @@
> #define AR933X_RESET_REG_RESET_MODULE 0x1c
> #define AR933X_RESET_REG_BOOTSTRAP 0xac
>
> +#define AR933X_RESET_GE1_MDIO BIT(23)
> +#define AR933X_RESET_GE0_MDIO BIT(22)
> +#define AR933X_RESET_GE1_MAC BIT(13)
> +#define AR933X_RESET_WMAC BIT(11)
> +#define AR933X_RESET_GE0_MAC BIT(9)
> +#define AR933X_RESET_SWITCH BIT(8)
> +#define AR933X_RESET_USB_HOST BIT(5)
> +#define AR933X_RESET_USB_PHY BIT(4)
> +#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
> +
> #define AR71XX_RESET_FULL_CHIP BIT(24)
>
> #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index c3980e78f..9d69b6aeb 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -204,6 +204,13 @@ config DRIVER_NET_EFI_SNP
> bool "EFI SNP ethernet driver"
> depends on EFI_BOOTUP
>
> +config DRIVER_NET_AG71XX
> + bool "Atheros AG71xx ethernet driver"
> + depends on MACH_MIPS_ATH79
> + select PHYLIB
> + help
> + This option enables support for Atheros AG71XX ethernet chip.
> +
> config DRIVER_NET_TSE
> depends on NIOS2
> bool "Altera TSE ethernet driver"
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index 42ea208e3..86c8ac32f 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -30,3 +30,4 @@ obj-$(CONFIG_DRIVER_NET_SMC91111) += smc91111.o
> obj-$(CONFIG_DRIVER_NET_TAP) += tap.o
> obj-$(CONFIG_DRIVER_NET_TSE) += altera_tse.o
> obj-$(CONFIG_DRIVER_NET_EFI_SNP) += efi-snp.o
> +obj-$(CONFIG_DRIVER_NET_AG71XX) += ag71xx.o
> diff --git a/drivers/net/ag71xx.c b/drivers/net/ag71xx.c
> new file mode 100644
> index 000000000..b2e066be3
> --- /dev/null
> +++ b/drivers/net/ag71xx.c
> @@ -0,0 +1,530 @@
> +/*
> + * Atheros AR71xx built-in ethernet mac driver
> + *
> + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
> + *
> + * Based on Atheros' AG7100 driver
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published
> + * by the Free Software Foundation.
> + */
> +
> +#include <common.h>
> +#include <net.h>
> +#include <dma.h>
> +#include <init.h>
> +#include <io.h>
> +#include <linux/err.h>
> +#include <linux/phy.h>
> +#include <of_net.h>
> +#include <of_address.h>
> +
> +#include <mach/ath79.h>
> +
> +/* Register offsets */
> +#define AG71XX_REG_MAC_CFG1 0x0000
> +#define AG71XX_REG_MAC_CFG2 0x0004
> +#define AG71XX_REG_MAC_IPG 0x0008
> +#define AG71XX_REG_MAC_HDX 0x000c
> +#define AG71XX_REG_MAC_MFL 0x0010
> +#define AG71XX_REG_MII_CFG 0x0020
> +#define AG71XX_REG_MII_CMD 0x0024
> +#define AG71XX_REG_MII_ADDR 0x0028
> +#define AG71XX_REG_MII_CTRL 0x002c
> +#define AG71XX_REG_MII_STATUS 0x0030
> +#define AG71XX_REG_MII_IND 0x0034
> +#define AG71XX_REG_MAC_IFCTL 0x0038
> +#define AG71XX_REG_MAC_ADDR1 0x0040
> +#define AG71XX_REG_MAC_ADDR2 0x0044
> +#define AG71XX_REG_FIFO_CFG0 0x0048
> +#define AG71XX_REG_FIFO_CFG1 0x004c
> +#define AG71XX_REG_FIFO_CFG2 0x0050
> +#define AG71XX_REG_FIFO_CFG3 0x0054
> +#define AG71XX_REG_FIFO_CFG4 0x0058
> +#define AG71XX_REG_FIFO_CFG5 0x005c
> +#define AG71XX_REG_FIFO_RAM0 0x0060
> +#define AG71XX_REG_FIFO_RAM1 0x0064
> +#define AG71XX_REG_FIFO_RAM2 0x0068
> +#define AG71XX_REG_FIFO_RAM3 0x006c
> +#define AG71XX_REG_FIFO_RAM4 0x0070
> +#define AG71XX_REG_FIFO_RAM5 0x0074
> +#define AG71XX_REG_FIFO_RAM6 0x0078
> +#define AG71XX_REG_FIFO_RAM7 0x007c
> +
> +#define AG71XX_REG_TX_CTRL 0x0180
> +#define AG71XX_REG_TX_DESC 0x0184
> +#define AG71XX_REG_TX_STATUS 0x0188
> +#define AG71XX_REG_RX_CTRL 0x018c
> +#define AG71XX_REG_RX_DESC 0x0190
> +#define AG71XX_REG_RX_STATUS 0x0194
> +#define AG71XX_REG_INT_ENABLE 0x0198
> +#define AG71XX_REG_INT_STATUS 0x019c
> +
> +#define AG71XX_REG_FIFO_DEPTH 0x01a8
> +#define AG71XX_REG_RX_SM 0x01b0
> +#define AG71XX_REG_TX_SM 0x01b4
> +
> +#define MAC_CFG1_TXE BIT(0) /* Tx Enable */
> +#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
> +#define MAC_CFG1_RXE BIT(2) /* Rx Enable */
> +#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
> +#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
> +#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
> +#define MAC_CFG1_LB BIT(8) /* Loopback mode */
> +#define MAC_CFG1_TX_RST BIT(18) /* Tx Reset */
> +#define MAC_CFG1_RX_RST BIT(19) /* Rx Reset */
> +#define MAC_CFG1_SR BIT(31) /* Soft Reset */
> +
> +#define MAC_CFG2_FDX BIT(0)
> +#define MAC_CFG2_CRC_EN BIT(1)
> +#define MAC_CFG2_PAD_CRC_EN BIT(2)
> +#define MAC_CFG2_LEN_CHECK BIT(4)
> +#define MAC_CFG2_HUGE_FRAME_EN BIT(5)
> +#define MAC_CFG2_IF_1000 BIT(9)
> +#define MAC_CFG2_IF_10_100 BIT(8)
> +
> +#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
> +#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
> +#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
> +#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
> +#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
> +#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
> + | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
> +
> +#define FIFO_CFG0_ENABLE_SHIFT 8
> +
> +#define FIFO_CFG4_DE BIT(0) /* Drop Event */
> +#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
> +#define FIFO_CFG4_FC BIT(2) /* False Carrier */
> +#define FIFO_CFG4_CE BIT(3) /* Code Error */
> +#define FIFO_CFG4_CR BIT(4) /* CRC error */
> +#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
> +#define FIFO_CFG4_LO BIT(6) /* Length out of range */
> +#define FIFO_CFG4_OK BIT(7) /* Packet is OK */
> +#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
> +#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
> +#define FIFO_CFG4_DR BIT(10) /* Dribble */
> +#define FIFO_CFG4_LE BIT(11) /* Long Event */
> +#define FIFO_CFG4_CF BIT(12) /* Control Frame */
> +#define FIFO_CFG4_PF BIT(13) /* Pause Frame */
> +#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
> +#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
> +#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
> +#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
> +
> +#define FIFO_CFG5_DE BIT(0) /* Drop Event */
> +#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
> +#define FIFO_CFG5_FC BIT(2) /* False Carrier */
> +#define FIFO_CFG5_CE BIT(3) /* Code Error */
> +#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
> +#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
> +#define FIFO_CFG5_OK BIT(6) /* Packet is OK */
> +#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
> +#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
> +#define FIFO_CFG5_DR BIT(9) /* Dribble */
> +#define FIFO_CFG5_CF BIT(10) /* Control Frame */
> +#define FIFO_CFG5_PF BIT(11) /* Pause Frame */
> +#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
> +#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
> +#define FIFO_CFG5_LE BIT(14) /* Long Event */
> +#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
> +#define FIFO_CFG5_16 BIT(16) /* unknown */
> +#define FIFO_CFG5_17 BIT(17) /* unknown */
> +#define FIFO_CFG5_SF BIT(18) /* Short Frame */
> +#define FIFO_CFG5_BM BIT(19) /* Byte Mode */
> +
> +#define AG71XX_INT_TX_PS BIT(0)
> +#define AG71XX_INT_TX_UR BIT(1)
> +#define AG71XX_INT_TX_BE BIT(3)
> +#define AG71XX_INT_RX_PR BIT(4)
> +#define AG71XX_INT_RX_OF BIT(6)
> +#define AG71XX_INT_RX_BE BIT(7)
> +
> +#define MAC_IFCTL_SPEED BIT(16)
> +
> +#define MII_CFG_CLK_DIV_4 0
> +#define MII_CFG_CLK_DIV_6 2
> +#define MII_CFG_CLK_DIV_8 3
> +#define MII_CFG_CLK_DIV_10 4
> +#define MII_CFG_CLK_DIV_14 5
> +#define MII_CFG_CLK_DIV_20 6
> +#define MII_CFG_CLK_DIV_28 7
> +#define MII_CFG_CLK_DIV_34 8
> +#define MII_CFG_CLK_DIV_42 9
> +#define MII_CFG_CLK_DIV_50 10
> +#define MII_CFG_CLK_DIV_58 11
> +#define MII_CFG_CLK_DIV_66 12
> +#define MII_CFG_CLK_DIV_74 13
> +#define MII_CFG_CLK_DIV_82 14
> +#define MII_CFG_CLK_DIV_98 15
> +#define MII_CFG_RESET BIT(31)
> +
> +#define MII_CMD_WRITE 0x0
> +#define MII_CMD_READ 0x1
> +#define MII_ADDR_SHIFT 8
> +#define MII_IND_BUSY BIT(0)
> +#define MII_IND_INVALID BIT(2)
> +
> +#define TX_CTRL_TXE BIT(0) /* Tx Enable */
> +
> +#define TX_STATUS_PS BIT(0) /* Packet Sent */
> +#define TX_STATUS_UR BIT(1) /* Tx Underrun */
> +#define TX_STATUS_BE BIT(3) /* Bus Error */
> +
> +#define RX_CTRL_RXE BIT(0) /* Rx Enable */
> +
> +#define RX_STATUS_PR BIT(0) /* Packet Received */
> +#define RX_STATUS_OF BIT(2) /* Rx Overflow */
> +#define RX_STATUS_BE BIT(3) /* Bus Error */
> +
> +/*
> + * GMAC register macros
> + */
> +#define AG71XX_ETH_CFG_RGMII_GE0 (1<<0)
> +#define AG71XX_ETH_CFG_MII_GE0_SLAVE (1<<4)
> +
> +/*
> + * h/w descriptor
> + */
> +typedef struct {
> + uint32_t pkt_start_addr;
> +
> + uint32_t is_empty : 1;
> + uint32_t res1 : 10;
> + uint32_t ftpp_override : 5;
> + uint32_t res2 : 4;
> + uint32_t pkt_size : 12;
> +
> + uint32_t next_desc ;
> +} ag7240_desc_t;
> +
> +#define NO_OF_TX_FIFOS 8
> +#define NO_OF_RX_FIFOS 8
> +#define TX_RING_SZ (NO_OF_TX_FIFOS * sizeof(ag7240_desc_t))
> +#define MAX_RBUFF_SZ 0x600 /* 1518 rounded up */
> +
> +#define MAX_WAIT 1000
> +
> +struct ag71xx {
> + struct device_d *dev;
> + struct eth_device netdev;
> + void __iomem *regs;
> + void __iomem *regs_gmac;
> + struct mii_bus miibus;
> +
> + void *rx_buffer;
> +
> + unsigned char *rx_pkt[NO_OF_RX_FIFOS];
> + ag7240_desc_t *fifo_tx;
> + ag7240_desc_t *fifo_rx;
> +
> + int next_tx;
> + int next_rx;
> +};
> +
> +static inline void ag71xx_check_reg_offset(struct ag71xx *priv, int reg)
> +{
> + switch (reg) {
> + case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
> + case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM:
> + case AG71XX_REG_MII_CFG:
> + break;
> +
> + default:
> + BUG();
> + }
> +}
> +
> +static inline u32 ag71xx_gmac_rr(struct ag71xx *dev, int reg)
> +{
> + return __raw_readl(dev->regs_gmac + reg);
> +}
> +
> +static inline void ag71xx_gmac_wr(struct ag71xx *dev, int reg, u32 val)
> +{
> + __raw_writel(val, dev->regs_gmac + reg);
> +}
> +
> +static inline u32 ag71xx_rr(struct ag71xx *priv, int reg)
> +{
> + ag71xx_check_reg_offset(priv, reg);
> +
> + return __raw_readl(priv->regs + reg);
> +}
> +
> +static inline void ag71xx_wr(struct ag71xx *priv, int reg, u32 val)
> +{
> + ag71xx_check_reg_offset(priv, reg);
> +
> + __raw_writel(val, priv->regs + reg);
> + /* flush write */
> + (void)__raw_readl(priv->regs + reg);
> +}
> +
> +static int ag71xx_ether_mii_read(struct mii_bus *miidev, int addr, int reg)
> +{
> + return 0xffff;
> +}
> +
> +static int ag71xx_ether_mii_write(struct mii_bus *miidev, int addr, int reg, u16 val)
> +{
> + return 0;
> +}
> +
> +static int ag71xx_ether_set_ethaddr(struct eth_device *edev, const unsigned char *adr)
> +{
> + return 0;
> +}
> +
> +static int ag71xx_ether_get_ethaddr(struct eth_device *edev, unsigned char *adr)
> +{
> + /* We have no eeprom */
> + return -1;
> +}
> +
> +static void ag71xx_ether_halt(struct eth_device *edev)
> +{
> + struct ag71xx *priv = edev->priv;
> +
> + ag71xx_wr(priv, AG71XX_REG_RX_CTRL, 0);
> + while (ag71xx_rr(priv, AG71XX_REG_RX_CTRL))
> + ;
> +}
> +
> +static int ag71xx_ether_rx(struct eth_device *edev)
> +{
> + struct ag71xx *priv = edev->priv;
> + ag7240_desc_t *f;
> + unsigned int work_done;
> +
> + for (work_done = 0; work_done < NO_OF_RX_FIFOS; work_done++) {
> + unsigned int pktlen;
> + unsigned char *rx_pkt;
> +
> + f = &priv->fifo_rx[priv->next_rx];
> +
> + if (f->is_empty)
> + break;
> +
> + pktlen = f->pkt_size;
> + rx_pkt = priv->rx_pkt[priv->next_rx];
> +
> + /* invalidate */
> + dma_sync_single_for_cpu((unsigned long)rx_pkt, pktlen,
> + DMA_FROM_DEVICE);
> +
> + net_receive(edev, rx_pkt, pktlen - 4);
> +
> + f->is_empty = 1;
> +
> + priv->next_rx = (priv->next_rx + 1) % NO_OF_RX_FIFOS;
> + }
> +
> + if (!(ag71xx_rr(priv, AG71XX_REG_RX_CTRL) & RX_CTRL_RXE)) {
> + f = &priv->fifo_rx[priv->next_rx];
> + ag71xx_wr(priv, AG71XX_REG_RX_DESC, virt_to_phys(f));
> + ag71xx_wr(priv, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
> + }
> +
> + return work_done;
> +}
> +
> +static int ag71xx_ether_send(struct eth_device *edev, void *packet, int length)
> +{
> + struct ag71xx *priv = edev->priv;
> + struct device_d *dev = priv->dev;
> + ag7240_desc_t *f = &priv->fifo_tx[priv->next_tx];
> + int i;
> +
> + /* flush */
> + dma_sync_single_for_device((unsigned long)packet, length, DMA_TO_DEVICE);
> +
> + f->pkt_start_addr = virt_to_phys(packet);
A couple of remarks regarding this code:
Despite the fact that this code should work fine, it violates the Linux DMA
API, which the Barebox tends to conform to. The problem is that the Barebox is
missing dma_map_*() functions, which should be used instead of virt_to_phys()
here.
Another DMA-related Barebox issue is the type of the first argument to
dma_sync_*() functions, which should be dma_addr_t (just like the return value
of dma_map_*() functions), instead of unsigned long. This is of no importance
for 32 bit architectures, however it will break for 64 bit targets.
> + f->res1 = 0;
> + f->pkt_size = length;
> + f->is_empty = 0;
> + ag71xx_wr(priv, AG71XX_REG_TX_DESC, virt_to_phys(f));
> + ag71xx_wr(priv, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
> +
> + /* flush again?! */
> + dma_sync_single_for_cpu((unsigned long)packet, length, DMA_TO_DEVICE);
> +
> + for (i = 0; i < MAX_WAIT; i++) {
> + udelay(100);
> + if (f->is_empty) {
> + break;
> + }
> + }
> +
> + if (i == MAX_WAIT) {
> + dev_err(dev, "Tx Timed out\n");
> + }
> +
> + f->pkt_start_addr = 0;
> + f->pkt_size = 0;
> +
> + priv->next_tx = (priv->next_tx + 1) % NO_OF_TX_FIFOS;
> +
> + return 0;
> +}
> +
> +static int ag71xx_ether_open(struct eth_device *edev)
> +{
> + return 0;
> +}
> +
> +static int ag71xx_ether_init(struct eth_device *edev)
> +{
> + struct ag71xx *priv = edev->priv;
> + int i;
> + void *rxbuf = priv->rx_buffer;
> +
> + priv->next_rx = 0;
> +
> + for (i = 0; i < NO_OF_RX_FIFOS; i++) {
> + ag7240_desc_t *fr = &priv->fifo_rx[i];
> +
> + priv->rx_pkt[i] = rxbuf;
> + fr->pkt_start_addr = virt_to_phys(rxbuf);
> + fr->pkt_size = MAX_RBUFF_SZ;
> + fr->is_empty = 1;
> + fr->next_desc = virt_to_phys(&priv->fifo_rx[(i + 1) % NO_OF_RX_FIFOS]);
> +
> + /* invalidate */
> + dma_sync_single_for_device((unsigned long)rxbuf, MAX_RBUFF_SZ,
> + DMA_FROM_DEVICE);
> +
> + rxbuf += MAX_RBUFF_SZ;
> + }
> +
> + /* Clean Tx BD's */
> + memset(priv->fifo_tx, 0, TX_RING_SZ);
> +
> + ag71xx_wr(priv, AG71XX_REG_RX_DESC, virt_to_phys(priv->fifo_rx));
> + ag71xx_wr(priv, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
> +
> + return 1;
> +}
> +
> +static int ag71xx_mii_setup(struct ag71xx *priv)
> +{
> + u32 rd;
> +
> + rd = ag71xx_gmac_rr(priv, 0);
> + rd |= AG71XX_ETH_CFG_MII_GE0_SLAVE;
> + ag71xx_gmac_wr(priv, 0, rd);
> +
> + return 0;
> +}
> +
> +static int ag71xx_probe(struct device_d *dev)
> +{
> + void __iomem *regs, *regs_gmac;
> + struct mii_bus *miibus;
> + struct eth_device *edev;
> + struct ag71xx *priv;
> + u32 mac_h, mac_l;
> + u32 rd;
> +
> + regs_gmac = dev_request_mem_region_by_name(dev, "gmac");
> + if (IS_ERR(regs_gmac))
> + return PTR_ERR(regs_gmac);
> +
> + regs = dev_request_mem_region_by_name(dev, "ge0");
> + if (IS_ERR(regs))
> + return PTR_ERR(regs);
> +
> + priv = xzalloc(sizeof(struct ag71xx));
> + edev = &priv->netdev;
> + miibus = &priv->miibus;
> + edev->priv = priv;
> +
> + edev->init = ag71xx_ether_init;
> + edev->open = ag71xx_ether_open;
> + edev->send = ag71xx_ether_send;
> + edev->recv = ag71xx_ether_rx;
> + edev->halt = ag71xx_ether_halt;
> + edev->get_ethaddr = ag71xx_ether_get_ethaddr;
> + edev->set_ethaddr = ag71xx_ether_set_ethaddr;
> +
> + priv->dev = dev;
> + priv->regs = regs;
> + priv->regs_gmac = regs_gmac;
> +
> + miibus->read = ag71xx_ether_mii_read;
> + miibus->write = ag71xx_ether_mii_write;
> + miibus->priv = priv;
> +
> + /* enable switch core */
> + rd = __raw_readl((char *)KSEG1ADDR(AR71XX_PLL_BASE + AR933X_ETHSW_CLOCK_CONTROL_REG)) & ~(0x1f);
> + rd |= 0x10;
> + __raw_writel(rd, (char *)KSEG1ADDR(AR71XX_PLL_BASE + AR933X_ETHSW_CLOCK_CONTROL_REG));
> +
> + if (ath79_reset_rr(AR933X_RESET_REG_RESET_MODULE) != 0)
> + ath79_reset_wr(AR933X_RESET_REG_RESET_MODULE, 0);
> +
> + /* reset GE0 MAC and MDIO */
> + rd = ath79_reset_rr(AR933X_RESET_REG_RESET_MODULE);
> + rd |= AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO | AR933X_RESET_SWITCH;
> + ath79_reset_wr(AR933X_RESET_REG_RESET_MODULE, rd);
> + mdelay(100);
> +
> + rd = ath79_reset_rr(AR933X_RESET_REG_RESET_MODULE);
> + rd &= ~(AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO | AR933X_RESET_SWITCH);
> + ath79_reset_wr(AR933X_RESET_REG_RESET_MODULE, rd);
> + mdelay(100);
> +
> + ag71xx_wr(priv, AG71XX_REG_MAC_CFG1, (MAC_CFG1_SR | MAC_CFG1_TX_RST | MAC_CFG1_RX_RST));
> + ag71xx_wr(priv, AG71XX_REG_MAC_CFG1, (MAC_CFG1_RXE | MAC_CFG1_TXE));
> +
> + rd = ag71xx_rr(priv, AG71XX_REG_MAC_CFG2);
> + rd |= (MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK | MAC_CFG2_IF_10_100);
> + ag71xx_wr(priv, AG71XX_REG_MAC_CFG2, rd);
> +
> + /* config FIFOs */
> + ag71xx_wr(priv, AG71XX_REG_FIFO_CFG0, 0x1f00);
> +
> + ag71xx_mii_setup(priv);
> +
> + ag71xx_wr(priv, AG71XX_REG_FIFO_CFG1, 0x10ffff);
> + ag71xx_wr(priv, AG71XX_REG_FIFO_CFG2, 0xAAA0555);
> +
> + ag71xx_wr(priv, AG71XX_REG_FIFO_CFG4, 0x3ffff);
> + ag71xx_wr(priv, AG71XX_REG_FIFO_CFG5, 0x66b82);
> + ag71xx_wr(priv, AG71XX_REG_FIFO_CFG3, 0x1f00140);
> +
> + priv->rx_buffer = xmemalign(PAGE_SIZE, NO_OF_RX_FIFOS * MAX_RBUFF_SZ);
> + priv->fifo_tx = dma_alloc_coherent(NO_OF_TX_FIFOS * sizeof(ag7240_desc_t), DMA_ADDRESS_BROKEN);
> + priv->fifo_rx = dma_alloc_coherent(NO_OF_RX_FIFOS * sizeof(ag7240_desc_t), DMA_ADDRESS_BROKEN);
> + priv->next_tx = 0;
> +
> + mac_l = 0x3344;
> + mac_h = 0x0004d980;
> +
> + ag71xx_wr(priv, AG71XX_REG_MAC_ADDR1, mac_l);
> + ag71xx_wr(priv, AG71XX_REG_MAC_ADDR2, mac_h);
> +
> + mdiobus_register(miibus);
> + eth_register(edev);
> +
> + dev_info(dev, "network device registered\n");
> +
> + return 0;
> +}
> +
> +static __maybe_unused struct of_device_id ag71xx_dt_ids[] = {
> + {
> + .compatible = "qca,ar7100-gmac",
> + }, {
> + /* sentinel */
> + }
> +};
> +
> +static struct driver_d ag71xx_driver = {
> + .name = "ag71xx-gmac",
> + .probe = ag71xx_probe,
> + .of_compatible = DRV_OF_COMPAT(ag71xx_dt_ids),
> +};
> +device_platform_driver(ag71xx_driver);
> --
> 2.11.0
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 05/13] net: ath79: add ag71xx Ethernet driver
2017-08-07 20:45 ` Peter Mamonov
@ 2017-08-08 7:50 ` Lucas Stach
0 siblings, 0 replies; 17+ messages in thread
From: Lucas Stach @ 2017-08-08 7:50 UTC (permalink / raw)
To: Peter Mamonov; +Cc: barebox, Oleksij Rempel
Hi Peter,
Am Montag, den 07.08.2017, 23:45 +0300 schrieb Peter Mamonov:
> On Mon, Aug 07, 2017 at 04:39:19PM +0200, Oleksij Rempel wrote:
> > From: Yegor Yefremov <yegorslists@googlemail.com>
> >
> > Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
> > Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> > ---
[...]
> > +static int ag71xx_ether_send(struct eth_device *edev, void *packet, int length)
> > +{
> > + struct ag71xx *priv = edev->priv;
> > + struct device_d *dev = priv->dev;
> > + ag7240_desc_t *f = &priv->fifo_tx[priv->next_tx];
> > + int i;
> > +
>
> > + /* flush */
> > + dma_sync_single_for_device((unsigned long)packet, length, DMA_TO_DEVICE);
> > +
> > + f->pkt_start_addr = virt_to_phys(packet);
>
> A couple of remarks regarding this code:
>
> Despite the fact that this code should work fine, it violates the Linux DMA
> API, which the Barebox tends to conform to. The problem is that the Barebox is
> missing dma_map_*() functions, which should be used instead of virt_to_phys()
> here.
>
> Another DMA-related Barebox issue is the type of the first argument to
> dma_sync_*() functions, which should be dma_addr_t (just like the return value
> of dma_map_*() functions), instead of unsigned long. This is of no importance
> for 32 bit architectures, however it will break for 64 bit targets.
A slight correction: unsigned long will work fine for pure 64bit
targets, as it maps to a 64bit type there. The only way this could break
is on 32bit LPAE targets, where long is a 32bit type, but the DMA
addresses could be above the 4GB mark.
Regards,
Lucas
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 01/13] MIPS: ath79: provide CONFIG_SOC_QCA_AR9331 option
2017-08-07 14:39 [PATCH v2 01/13] MIPS: ath79: provide CONFIG_SOC_QCA_AR9331 option Oleksij Rempel
` (11 preceding siblings ...)
2017-08-07 14:39 ` [PATCH v2 13/13] filetype: fix file type detection for Barebox MIPS Oleksij Rempel
@ 2017-08-09 15:23 ` Oleksij Rempel
12 siblings, 0 replies; 17+ messages in thread
From: Oleksij Rempel @ 2017-08-09 15:23 UTC (permalink / raw)
To: barebox
[-- Attachment #1.1.1: Type: text/plain, Size: 1168 bytes --]
I assume it was bad idea to push this patches all together.
will split it and send in separate chunks.
Am 07.08.2017 um 16:39 schrieb Oleksij Rempel:
> QCA AR9331 and QCA AR9344 have some similar part but different uart engines.
> We need this flag to provide common debug_ll support.
>
> Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
> ---
> arch/mips/mach-ath79/Kconfig | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
> index 9b8e3946e..f2eae2532 100644
> --- a/arch/mips/mach-ath79/Kconfig
> +++ b/arch/mips/mach-ath79/Kconfig
> @@ -4,17 +4,22 @@ config ARCH_TEXT_BASE
> hex
> default 0xa0800000
>
> +config SOC_QCA_AR9331
> + bool
> +
> choice
> prompt "Board type"
>
> config BOARD_TPLINK_MR3020
> bool "TP-LINK MR3020"
> + select SOC_QCA_AR9331
> select HAVE_PBL_IMAGE
> select HAVE_IMAGE_COMPRESSION
> select HAS_NMON
>
> config BOARD_BLACK_SWIFT
> bool "Black Swift"
> + select SOC_QCA_AR9331
> select HAVE_PBL_IMAGE
> select HAVE_IMAGE_COMPRESSION
> select HAS_NMON
>
--
Regards,
Oleksij
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^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2017-08-09 15:24 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-08-07 14:39 [PATCH v2 01/13] MIPS: ath79: provide CONFIG_SOC_QCA_AR9331 option Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 02/13] MIPS: ath79: add initial QCA AR9344 SoC support Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 03/13] MIPS: ath79: add TP-Link WDR4300 board support Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 04/13] MIPS: add virt_to_phys() and phys_to_virt() Oleksij Rempel
2017-08-07 19:56 ` Peter Mamonov
2017-08-07 14:39 ` [PATCH v2 05/13] net: ath79: add ag71xx Ethernet driver Oleksij Rempel
2017-08-07 20:45 ` Peter Mamonov
2017-08-08 7:50 ` Lucas Stach
2017-08-07 14:39 ` [PATCH v2 06/13] net: ag71xx: bit 19 should be set to 1 for GE0 Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 07/13] MIPS: tplink-mr3020: pbl: move WMAC init after flash addr test Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 08/13] MIPS: tplink-mr3020: pbl: move hornet_mips24k_cp0_setup " Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 09/13] MIPS: tplink-mr3020_defconfig: enable more options Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 10/13] MIPS: tplink-mr3020.dts: add partition table Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 11/13] MIPS: ar9344.dtsi: add ag71xx Ethernet driver Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 12/13] MIPS: ath79: add barebox update handler Oleksij Rempel
2017-08-07 14:39 ` [PATCH v2 13/13] filetype: fix file type detection for Barebox MIPS Oleksij Rempel
2017-08-09 15:23 ` [PATCH v2 01/13] MIPS: ath79: provide CONFIG_SOC_QCA_AR9331 option Oleksij Rempel
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